CN109659296B - Test key for monitoring etching depth of O L ED panel and O L ED large panel - Google Patents
Test key for monitoring etching depth of O L ED panel and O L ED large panel Download PDFInfo
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- CN109659296B CN109659296B CN201811546767.9A CN201811546767A CN109659296B CN 109659296 B CN109659296 B CN 109659296B CN 201811546767 A CN201811546767 A CN 201811546767A CN 109659296 B CN109659296 B CN 109659296B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The invention discloses a test key for monitoring the etching depth of an O L ED panel and an O L ED large panel, wherein the test key comprises a scanning base line area, a film structure of the scanning base line area sequentially comprises a light-transmitting base material, a blocking buffer layer, an active layer, a first grid insulation layer, a first grid metal layer, a second grid insulation layer, a second grid metal layer and an interlayer insulation layer, and an interlayer insulation layer etching area adjacent to the scanning base line area, and the film structure of the interlayer insulation layer etching area sequentially comprises the light-transmitting base material and the blocking buffer layer.
Description
Technical Field
The invention relates to the technical field of display, in particular to a test key for monitoring the etching depth of an O L ED panel and an O L ED large panel.
Background
In the O L ED panel process, it is necessary to monitor the etching depth of each etching process to determine whether the etching process is completed and whether etching residues occur, conventionally, a method of measuring an etching test key (Testkey) is adopted to determine, the O L ED panel is uniformly provided with test keys, a height difference between a film layer scanning base line region 2 and an interlayer insulating layer etching region 3 is measured by using a surface differential instrument 1, as shown in fig. 1A and 1B, an arrow 500 is a scanning path, and whether residues occur is determined by comparing the height difference with a standard film layer thickness.
The layer structure of the O L ED panel includes a transparent substrate/Barrier Buffer layer (Barrier & Buffer layer)/active layer/first gate insulating layer (GI 1)/first gate metal layer (GE 1)/second gate insulating layer (GI 2)/second gate metal layer (GE 2)/interlayer insulating layer (I L D). referring to fig. 1A and 1B, the layer structure of the conventional measurement technique of the scanning base line region 2 is transparent substrate/Barrier Buffer layer/active layer/first gate insulating layer/second gate insulating layer/interlayer insulating layer, and the layer structure of the interlayer insulating layer etching region 3 is transparent substrate/Barrier Buffer layer/active layer, i.e. GE1 and GE2 in the scanning base line region are etched and removed, but such step has an over-etching problem, and the GI thicknesses of the GI1 and GI2 are lost after GE1 and GE2 etching, so that the thicknesses of the GI1 and GI2 are different from the thicknesses in the original design, which results in height difference between the scanning base line region and the interlayer insulating layer, and thus it is difficult to monitor the etching depth precisely.
Therefore, it is desirable to provide a test key for monitoring an etching depth of an O L ED panel and an O L ED panel to solve the problems of the prior art.
Disclosure of Invention
The invention aims to provide a test key for monitoring an etching depth of an O L ED panel and an O L ED large panel, wherein a scanning base line region of the test key can eliminate the over-etching problem when a first grid metal layer (GE1) and a second grid metal layer (GE2) are removed, so that the thicknesses of GI1 and GI2 are not lost, thereby avoiding the error between the actual height difference between the scanning base line region and an interlayer insulating layer etching region and the height difference during design, and further improving the accuracy and convenience of interlayer insulating layer etching monitoring.
To achieve the above objects, the present invention provides a test key for monitoring an etching depth of an O L ED panel, the test key comprising:
a scanning baseline region, a film structure of the scanning baseline region sequentially comprising: the light-transmitting substrate, the blocking buffer layer, the active layer, the first grid insulating layer, the first grid metal layer, the second grid insulating layer, the second grid metal layer and the interlayer insulating layer are arranged on the substrate; and
an inter-layer insulation layer etching area adjacent to the scanning base line area, wherein a film structure of the inter-layer insulation layer etching area sequentially comprises: the light-transmitting substrate, the blocking buffer layer and the active layer.
According to an embodiment of the present invention, the material of the light-transmitting substrate includes glass or polyimide.
According to an embodiment of the present invention, the interlayer insulating layer etched region has an interlayer insulating layer via hole exposing a portion of the active layer.
The present invention also provides a test key for monitoring an etch depth of an O L ED panel, the test key comprising:
a scanning baseline region, a film structure of the scanning baseline region comprising: a light-transmitting substrate, a barrier buffer layer disposed on the light-transmitting substrate, an active layer patterning process disposed on the barrier buffer layer, a first gate insulating layer disposed on the active layer and the barrier buffer layer, a first gate metal layer patterning process disposed on the first gate insulating layer, a second gate insulating layer disposed on the first gate metal layer and the first gate insulating layer, a second gate metal layer patterning process disposed on the second gate insulating layer, and an interlayer insulating layer disposed on the second gate metal layer, the second gate insulating layer, and the barrier buffer layer; and
and the interlayer insulating layer etching area is adjacent to the scanning base line area, and part of the active layer is exposed out of the interlayer insulating layer etching area.
According to an embodiment of the present invention, the material of the light-transmitting substrate includes glass or polyimide.
According to an embodiment of the present invention, a film structure of the interlayer insulating layer etching region includes: the light-transmitting substrate, the blocking buffer layer and the active layer.
According to an embodiment of the present invention, the material of the active layer includes silicon or polysilicon.
According to an embodiment of the present invention, the interlayer insulating layer etched region has an interlayer insulating layer via hole.
The invention also provides an O L ED large plate, wherein the O L ED large plate comprises:
a plurality of O L ED panels arranged in an array, and
a plurality of test keys for monitoring an etching depth of the plurality of O L ED panels, the plurality of test keys being correspondingly disposed around the plurality of O L ED panels, the plurality of test keys comprising:
a scanning baseline region, a film structure of the scanning baseline region sequentially comprising: the light-transmitting substrate, the blocking buffer layer, the active layer, the first grid insulating layer, the first grid metal layer, the second grid insulating layer, the second grid metal layer and the interlayer insulating layer are arranged on the substrate; and
an inter-layer insulation layer etching area adjacent to the scanning base line area, wherein a film structure of the inter-layer insulation layer etching area sequentially comprises: the light-transmitting substrate, the blocking buffer layer and the active layer.
According to an embodiment of the invention, the O L ED panel further includes a plurality of cutting channels disposed between adjacent O L ED panels, and the plurality of test keys are correspondingly disposed on the plurality of cutting channels.
The invention has the advantages that the etching test key of the interlayer insulating layer via hole on the existing O L ED large board is improved, the scanning base line area is provided with the first grid metal layer GE1 and the second grid metal layer GE2, the over-etching problem when the first grid metal layer GE1 and the second grid metal layer GE2 are removed is eliminated, and the thicknesses of the first grid insulating layer GI1 and the second grid insulating layer GI2 cannot be lost.
Drawings
In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:
FIG. 1A is a top view of a prior art test key.
FIG. 1B is a cross-sectional view of a prior art test key.
FIG. 2 is a top view of an O L ED panel of the present invention.
FIG. 3A is a top view of a test key of the present invention for monitoring an etch depth of an O L ED panel.
FIG. 3B is a cross-sectional view of a test key of the present invention for monitoring an etch depth of an O L ED panel.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. Furthermore, directional phrases used herein, such as, for example, upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, lateral, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., refer only to the orientation of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
In this document, the terms (process, apparatus, device, apparatus, system, etc.) and variations thereof are to be construed as being inclusive (i.e., non-exclusive) such that a process, method, apparatus, device or system (system) described herein is not limited to the recitation of such a function, portion, component or step, but may include other elements, functions, portions or steps without explicitly listed or inherent to such a step, method, article or device. Furthermore, the terms a, an, and the like, as used herein, are intended to mean one or more, unless explicitly stated otherwise. Moreover, the terms first, second, third and the like are used merely as labels, and do not impose numerical requirements or an established order.
Referring to fig. 1A and 1B, fig. 1A is a top view and fig. 1B is a cross-sectional view of a conventional test key, in which the film structures of a conventional O L ED panel sequentially include a transparent substrate 110, a barrier buffer layer 120, an active layer 130, a first gate insulating layer 140, a first gate metal layer (not shown), a second gate insulating layer 160, a second gate metal layer (not shown), and an interlayer insulating layer 180.
Referring to fig. 2, fig. 2 is a top view of an O L ED board according to the present invention, the present invention provides an O L ED board 10, and the O L ED board 10 includes a plurality of O L ED panels 20, a plurality of scribe lines 30, and a plurality of test keys 200.
A plurality of O L ED panels 20 are arranged in an array to form the O L ED panel 10. that is, the O L ED panel 10 has a plurality of O L ED panels 20 before being cut.
The plurality of scribe lines 30 are disposed between the adjacent O L ED panels 20, as shown in fig. 2, the scribe lines 30 may include a horizontal scribe line and a vertical scribe line, and the test keys 200 are correspondingly disposed on the scribe lines 30, for example, on the horizontal scribe line.
A plurality of test keys 200 are used for monitoring an etching depth of the O L ED panels 20, the test keys 200 are correspondingly disposed around the O L ED panels, for example, on the scribe lines 30 disposed around the O L ED panels 20, so as to effectively monitor the etching depth of the O L ED panel 10 during etching and not to affect the area of the O L ED panels 20 produced by the O L ED panel 10. referring to FIGS. 3A and 3B, each of the test keys 200 includes a scan baseline region 2 and an inter-layer insulation etching region 3.
A film structure of the scanning baseline region 2 sequentially comprises: a transparent substrate 210, a barrier buffer layer 220, an active layer 230, a first gate insulating layer 240, a first gate metal layer 250, a second gate insulating layer 260, a second gate metal layer 270, and an interlayer insulating layer 280. The material of the light-transmitting substrate 210 may include glass or polyimide. The blocking buffer layer 220 is disposed on the transparent substrate 210, and the blocking buffer layer 220 may be used to block moisture and oxygen. The barrier buffer layer 220 may include a water oxygen barrier layer and a buffer layer. The material of the blocking buffer layer 220 may be silicon oxide, silicon nitride, or other materials with the effect of blocking moisture and oxygen.
The active layer 230 is disposed on the barrier buffer layer 220 by a patterning process. The material of the active layer 230 includes silicon or polysilicon. The first gate insulating layer 240 is disposed on the active layer 230 and the barrier buffer layer 220. The first gate metal layer 250 is disposed on the first gate insulation layer 240 by a patterning process. The second gate insulating layer 260 is disposed on the first gate metal layer 250 and the first gate insulating layer 240. The second gate metal layer 270 is disposed on the second gate insulation layer 260 by a patterning process. The interlayer insulating layer 280 is disposed on the second gate metal layer 270, the second gate insulating layer 260, and the blocking buffer layer 220.
The interlayer insulating layer etching region 3 is adjacent to the scanning baseline region 2, and a film structure of the interlayer insulating layer etching region 3 sequentially includes: the light-transmitting substrate 210, the barrier buffer layer 220, and the active layer 230. The ild etched region 3 has an ild via 281 exposing a portion of the active layer 230.
The film structures of the scanning base line region 2 and the interlayer insulating layer etching region 3 can be formed by the interaction of a thin film deposition process, a patterning process and an etching process. The thin film deposition process may utilize physical vapor deposition, chemical vapor deposition, evaporation, sputtering, or other suitable techniques. The patterning process may be performed by photolithography or other similar techniques that define the position and shape of the pattern. The etching process may be performed by wet etching or dry etching.
As an example, assuming that the thicknesses of seven layers, i.e., the barrier buffer layer 220/the active layer 230/the first gate insulating layer 240/the first gate metal layer 250/the second gate insulating layer 260/the second gate metal layer 270/the interlayer insulating layer 280, on the transparent substrate 210 in the O L ED panel are 8500 Å/900 Å/1300 Å/2500 Å/1100 Å/2500 Å/5000 Å, since the first gate metal layer 250 and the second gate metal layer 270 remain in the scanning baseline region 2, the height difference between the scanning baseline region 2 and the interlayer insulating layer etching region 3 is 12400 Å only in the transparent substrate 210, the barrier buffer layer 220 and the active layer 230, as shown in fig. 3A, after being measured by a scanning path of an arrow 500 through a surface profile analyzer 1, the height difference is smaller than 12400 Å, thereby the etching depth of the interlayer insulating layer 280 can be estimated to be insufficient.
The invention has the advantages that the etching test key of the interlayer insulating layer via hole on the existing O L ED large board is improved, the scanning base line area is provided with the first grid metal layer and the second grid metal layer, the over-etching problem when the first grid metal layer and the second grid metal layer are removed is eliminated, and the thickness of the first grid insulating layer and the second grid insulating layer is not lost.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (5)
1. A test key for monitoring an etch depth of an O L ED panel, the test key comprising:
a scanning baseline region, a film structure of the scanning baseline region sequentially comprising: the light-transmitting substrate, the blocking buffer layer, the active layer, the first grid insulating layer, the first grid metal layer, the second grid insulating layer, the second grid metal layer and the interlayer insulating layer are arranged on the substrate; and
an inter-layer insulation layer etching area adjacent to the scanning base line area, wherein a film structure of the inter-layer insulation layer etching area sequentially comprises: the light-transmitting substrate, the blocking buffer layer and the active layer, wherein the interlayer insulating layer etching area is provided with an interlayer insulating layer through hole, and part of the active layer is exposed.
2. The test key of claim 1, wherein: the material of the light-transmitting substrate includes glass or polyimide.
3. The test key of claim 1, wherein: the material of the active layer comprises silicon.
4. An O L ED large plate, characterized in that the O L ED large plate comprises:
a plurality of O L ED panels arranged in an array, and
a plurality of test keys for monitoring an etching depth of the plurality of O L ED panels, the plurality of test keys being correspondingly disposed around the plurality of O L ED panels, the plurality of test keys comprising:
a scanning baseline region, a film structure of the scanning baseline region sequentially comprising: the light-transmitting substrate, the blocking buffer layer, the active layer, the first grid insulating layer, the first grid metal layer, the second grid insulating layer, the second grid metal layer and the interlayer insulating layer are arranged on the substrate; and
an inter-layer insulation layer etching area adjacent to the scanning base line area, wherein a film structure of the inter-layer insulation layer etching area sequentially comprises: the light-transmitting substrate, the blocking buffer layer and the active layer, wherein the interlayer insulating layer etching area is provided with an interlayer insulating layer through hole, and part of the active layer is exposed.
5. The O L ED large plate as claimed in claim 4, wherein the O L ED large plate further comprises:
a plurality of cutting channels disposed between the adjacent O L ED panels, and the plurality of test keys are correspondingly disposed on the plurality of cutting channels.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811546767.9A CN109659296B (en) | 2018-12-18 | 2018-12-18 | Test key for monitoring etching depth of O L ED panel and O L ED large panel |
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| CN201811546767.9A CN109659296B (en) | 2018-12-18 | 2018-12-18 | Test key for monitoring etching depth of O L ED panel and O L ED large panel |
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| CN109659296B true CN109659296B (en) | 2020-07-10 |
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| US6339955B1 (en) * | 2000-03-31 | 2002-01-22 | Advanced Micro Devices, Inc. | Thickness measurement using AFM for next generation lithography |
| DE10103061B4 (en) * | 2001-01-24 | 2010-04-08 | Advanced Micro Devices, Inc., Sunnyvale | A method of inspecting the depth of an opening in a dielectric material layer |
| CN102097286B (en) * | 2009-12-15 | 2012-04-25 | 北大方正集团有限公司 | Method for monitoring step profiler in measuring accuracy of chip groove depth |
| CN102110586B (en) * | 2009-12-24 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for monitoring silicon damage in semiconductor substrate |
| TWI562258B (en) * | 2011-11-01 | 2016-12-11 | United Microelectronics Corp | Testkey structure and method for measuring step height by such testkey structure |
| CN106920812B (en) * | 2015-12-25 | 2019-10-25 | 上海和辉光电有限公司 | A kind of OLED display panel and preparation method thereof |
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