CN106920812B - A kind of OLED display panel and preparation method thereof - Google Patents
A kind of OLED display panel and preparation method thereof Download PDFInfo
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- CN106920812B CN106920812B CN201510996394.5A CN201510996394A CN106920812B CN 106920812 B CN106920812 B CN 106920812B CN 201510996394 A CN201510996394 A CN 201510996394A CN 106920812 B CN106920812 B CN 106920812B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
Abstract
The present invention relates to display technology fields, more particularly to a kind of OLED display panel and preparation method thereof, using source-drain electrode layer as exposure mask, the method being etched with buffer layer of the HF medical fluid to the contact hole structure bottom for being located at encapsulation region, it does not need an additional light shield and can etch to achieve the purpose that encapsulation positioned at the second contact hole of encapsulation region, production cost can be saved while simplifying technique, the top of catalytic oxidation silicon layer is arranged in contact silicon nitride layer by the present invention simultaneously, that is first etching contact silicon nitride layer, catalytic oxidation silicon layer is etched afterwards, avoid contact with the excessive loss for causing product yield of damage of layer.
Description
Technical field
The present invention relates to display technology fields more particularly to a kind of OLED display panel and preparation method thereof.
Background technique
Second contact hole (CT2) is low temperature polycrystalline silicon (in (Low Temperature Poly Silicon, abbreviation LTPS)
One important processing procedure, the importing of CT2 will lead to the increase of production cost, and the design and production of CT2 light shield need manpower and money
The investment of gold, and the importing of yellow light and etching work procedure also will increase the usage amount of production indirect material, this is for large-scale production
It is unfavorable.
In recent years, the etch process of the second contact hole (CT2) is the upper photoresist after SP (Spacer, source-drain electrode layer) layer
And it is exposed development with the light shield of CT2, it reuses wet process (WET)+dry method (DRY) etching mode and etches the hole of CT2.This
The shortcomings that kind way is: every product requires the light shield for more opening a CT2, improves the fixed cost of production；Except this it
Outside, it is also necessary to which yellow light carries out photoresist/exposure/development, increases the usage amount of photoresist and developer solution；And it etches and needs using HF liquid
And CF4Gas can equally improve cost；Meanwhile more layers (Layer) can be such that processing procedure complicates, and increase yield loss
A possibility that (Yield Loss), this is that those skilled in the art are unwilling to see.
Summary of the invention
In view of the above problems, the present invention discloses a kind of OLED display panel, comprising:
One substrate is provided with packaging area (region Frit) and display area；
Buffer layer (Buffer), is set on the substrate；
Semiconductor layer is set on the buffer layer of the display area, and is arranged in the semiconductor layer active
Polar region/drain region and channel region；
First grid insulating layer is set on the semiconductor layer and the part buffer layer；
Grid layer, it is corresponding with the channel region to be set on the first grid insulating layer；
Second grid insulating layer is set on the grid layer and part the first grid insulating layer；
Contact layer is set on the second grid insulating layer；
First contact hole is located in the display area, and through the contact layer to the source area or drain region
Upper surface is with the circuit for connecting the display area；
Second contact hole is located in the packaging area, and is used to connect into the buffer layer through the contact layer
Connect the circuit of the packaging area；
Source-drain electrode layer (Data Line, abbreviation DL), the portion of upper surface and described first for being set to the contact layer contact
The bottom in hole and its side wall；
Above-mentioned OLED display panel, wherein the buffer layer includes buffering silicon nitride layer and buffering silicon oxide layer；
Wherein, the buffer oxide silicon layer is located at the top of the buffering silicon nitride layer or the buffering silicon nitride layer is located at
The top of the buffer oxide silicon layer.
Above-mentioned OLED display panel, wherein the first grid insulating layer includes gate oxidation silicon layer and is located at described
Gate nitridation silicon layer on gate oxidation silicon layer, the gate nitridation silicon layer be located at display area interior raceway groove area just on
Side.
Above-mentioned OLED display panel, wherein the material of the grid layer is molybdenum (Mo).
Above-mentioned OLED display panel, wherein the material of the second grid insulating layer is silicon nitride.
Above-mentioned OLED display panel, wherein the contact layer include catalytic oxidation silicon layer and be located at the catalytic oxidation
The contact silicon nitride layer of silicon layer upper surface.
The invention also discloses a kind of preparation methods of OLED display panel, and described method includes following steps:
One substrate for being provided with packaging area and display area is provided；
Buffer layer is formed on the substrate；
The semiconductor with source/drain region and channel region is formed on the buffer layer of the display area
Layer；
First grid insulating layer is formed in the upper surface of the semiconductor layer and buffer layer exposure；
Grid layer corresponding with the channel region is formed in first grid insulating layer upper surface；
It deposits to form second in the surface of surface and part the first grid insulating layer exposing of grid layer exposure
Gate insulating layer；
Contact layer is formed in the surface of the part second grid insulating layer；
The contact layer, the second grid insulating layer and the first grid are sequentially etched according to sequence from top to bottom
Insulating layer is located at the source area or drain region upper surface for connecting the display area to be formed in the display area
First contact hole of circuit, and the contact hole structure being located above the buffer layer is formed in the packaging area；
Source-drain electrode layer is formed in the portion of upper surface of the contact layer, and the source-drain electrode layer covers first contact hole
Bottom and its side wall, and the contact hole structure is exposed；
Using the source-drain electrode layer as exposure mask, etching is located at the buffer layer of the contact hole structure bottom, to form use
In the second contact hole for connecting circuit in the packaging area.
The preparation method of above-mentioned OLED display panel, wherein etch to form second contact hole by HF medical fluid.
The preparation method of above-mentioned OLED display panel, wherein the contact layer include catalytic oxidation silicon layer and be located at institute
State the contact silicon nitride layer of catalytic oxidation silicon layer upper surface；
In the method, include: in the step of surface of the part second grid insulating layer forms the contact layer
It deposits to form the catalytic oxidation silicon layer in the surface of the part second grid insulating layer；
It deposits to form the contact silicon nitride layer in the upper surface of the catalytic oxidation silicon layer.
The preparation method of above-mentioned OLED display panel, wherein the upper surface of Yu Suoshu catalytic oxidation silicon layer deposits to be formed
When contacting silicon nitride layer, used NH3And SiH4Proportion be 1:1.
The preparation method of above-mentioned OLED display panel, wherein the buffer layer includes buffering silicon nitride layer and buffering oxygen
SiClx layer；
Wherein, the buffer oxide silicon layer is located at the top of the buffering silicon nitride layer or the buffering silicon nitride layer is located at
The top of the buffer oxide silicon layer.
The preparation method of above-mentioned OLED display panel, wherein the first grid insulating layer includes gate oxidation silicon layer
With the gate nitridation silicon layer being located on the gate oxidation silicon layer, the gate nitridation silicon layer is located at the display area septal fossula
The surface in road area.
The preparation method of above-mentioned OLED display panel, wherein the material of the grid layer is molybdenum.
The preparation method of above-mentioned OLED display panel, wherein the material of the second grid insulating layer is silicon nitride.
Foregoing invention is with the following advantages or beneficial effects:
The invention discloses a kind of OLED display panels and preparation method thereof, using source-drain electrode layer (DL layers) as exposure mask
(Mask), the method being etched with buffer layer of the HF medical fluid to the contact hole structure bottom for being located at encapsulation region does not need additional
The second contact hole (CT2) that can etch positioned at encapsulation region of a light shield achieve the purpose that encapsulation, technique can simplified
While save production cost, the while top that the present invention will contact silicon nitride layer catalytic oxidation silicon layer is arranged in first etches
Silicon nitride layer is contacted, it is rear to etch catalytic oxidation silicon layer, avoid contact with the excessive loss (loss) for causing product yield of damage of layer.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in all the attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the gist of the present invention.
Fig. 1 is the structural schematic diagram of OLED display panel in the embodiment of the present invention；
Fig. 2~12 are the flowage structure schematic diagrames of the preparation method of OLED display panel in the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated with specific embodiment with reference to the accompanying drawing, but not as limit of the invention
It is fixed.
Embodiment one:
The present invention discloses a kind of OLED display panel, which includes being provided with packaging area and display area
Substrate, be set on substrate buffer layer, be set on the buffer layer of display area, and be provided with source area/drain electrode
The semiconductor layer of area and channel region, the first grid insulating layer being set on semiconductor layer and portion of buffer layer and channel region
The corresponding grid layer being set on first grid insulating layer is set on grid layer and part first grid insulating layer
Second grid insulating layer, is located in display area the contact layer being set on second grid insulating layer, and extremely through contact layer
The upper surface of source area or drain region with the first contact hole of the circuit for connecting display area, be located at packaging area in, and
With the second contact hole of the circuit for connecting packaging area and the portion of contact layer is set into buffer layer through contact layer
Divide the bottom of upper surface and the first contact hole and its source-drain electrode layer of side wall.
In a preferred embodiment of the invention, above-mentioned buffer layer includes buffering silicon nitride layer and buffering silicon oxide layer；
Wherein, the buffer oxide silicon layer is located at the top of the buffering silicon nitride layer or the buffering silicon nitride layer is located at the buffering
The top of silicon oxide layer.
In a preferred embodiment of the invention, above-mentioned first grid insulating layer includes gate oxidation silicon layer and is located at grid
Gate nitridation silicon layer on the silicon oxide layer of pole, gate nitridation silicon layer are located at the surface in display area interior raceway groove area.
In a preferred embodiment of the invention, the material of above-mentioned grid layer is molybdenum (Mo).
In a preferred embodiment of the invention, the material of above-mentioned second grid insulating layer is silicon nitride.
In a preferred embodiment of the invention, above-mentioned contact layer includes catalytic oxidation silicon layer and is located at catalytic oxidation silicon
The contact silicon nitride layer of layer upper surface.
OLED display panel of the present invention is further elaborated with specific embodiment with reference to the accompanying drawing:
As shown in Figure 1, the present embodiment is related to a kind of OLED display panel, which includes being provided with encapsulation region
The substrate 1 of domain and display area the buffer layer 2 being set on substrate 1, is set on the buffer layer 2 of display area, and sets
Be equipped with the semiconductor layer 3 of source/drain region 31 and channel region 32, be set to semiconductor layer 3 and portion of buffer layer 2 on
One gate insulating layer 4, is set to grid layer at the grid layer 5 being set on first grid insulating layer 4 corresponding with channel region 32
5 and part first grid insulating layer 4 on second grid insulating layer 6, the contact layer that is set on second grid insulating layer 6
7, it is located in display area, and runs through contact layer 7 to the upper surface of source area or drain region 31 for connecting display area
First contact hole 8 of circuit is located in packaging area, and runs through contact layer 7 into buffer layer 2 for connecting packaging area
Second contact hole 11 of circuit and it is set to the portion of upper surface of contact layer 7 and the bottom of the first contact hole 8 and its side wall
Source-drain electrode layer 10.
In an embodiment of the present invention, contact layer 7 includes catalytic oxidation silicon layer 71 (can be silica) and contact nitrogen
SiClx layer 72, catalytic oxidation silicon layer 71 are set on second grid insulating layer 6, and contact silicon nitride layer 72 is set to catalytic oxidation
The upper surface of silicon layer 71, although this is because the bottom and its side wall of the portion of upper surface of contact layer 7 and the first contact hole 8 are by source
Drain electrode layer 10 protects, but contact layer 7 still it is most of it is exposed outside, etch to form the second contact hole using HF medical fluid subsequent
It is contacted when 11 with HF medical fluid, and HF medical fluid is much higher than the rate of etch to silicon nitride to the rate of etch of oxide, therefore, if contact layer
7 be still oxide upper, and silicon nitride is under, then contact layer 7 has biggish loss in etching process, and the present embodiment will
Oxide and silicon nitride are inverted, so that contact silicon nitride layer is located on catalytic oxidation silicon layer, to avoid the damage of contact layer 7
The excessive yield loss for causing product of vector.
In an embodiment of the present invention, above-mentioned buffer layer 2 includes buffering silicon nitride layer 21 and covering buffering silicon nitride layer 21
The buffer oxide silicon layer 22 (the buffer oxide silicon layer 22 can be silica) of upper surface, in the other embodiment of the present invention
In, silicon nitride layer 21 can also be buffered in the buffer layer 2 upper, under, this has no effect on of the invention buffer oxide silicon layer 22
Purpose.
In an embodiment of the present invention, above-mentioned first grid insulating layer 4 including gate oxidation silicon layer 41 and is located at grid oxygen
Gate nitridation silicon layer 42 on SiClx layer, and gate nitridation silicon layer 42 is located at the surface in display area interior raceway groove area 32.
In an embodiment of the present invention, the material of above-mentioned grid layer 5 is molybdenum (Mo), or other conductive materials.
In an embodiment of the present invention, the material of above-mentioned second grid insulating layer 6 is silicon nitride.
In an embodiment of the present invention, above-mentioned source-drain electrode layer 10 is composite construction, it is preferred that source-drain electrode layer 10 be include the
The sandwich structure (the first titanium layer, aluminium layer and the second titanium layer are not shown in the figure) of one titanium layer (Ti), aluminium layer (Al) and the second titanium layer,
That is the structure that aluminium layer is clipped in the middle by two layers of titanium layer, certain source-drain electrode layer 10 or other conductive materials, other structures,
As long as being able to achieve the purpose of the present invention.
In one embodiment of the invention, above-mentioned buffering silicon nitride layer 21 with a thickness of Buffer oxide silicon layer
22 with a thickness ofGate oxidation silicon layer 41 with a thickness ofGate nitridation silicon layer 42 with a thickness of
Contact silicon nitride layer 72 with a thickness ofCatalytic oxidation silicon layer 71 with a thickness ofAnd 11 bottom of the second contact hole
The distance between portion and buffering 21 bottom of silicon nitride layer areCertainly it is required according to specific product, each tunic thickness can not
Together, this has no influence to the present invention.
Embodiment two:
The invention also discloses a kind of preparation methods of OLED display panel, and this method comprises the following steps:
One substrate for being provided with packaging area and display area is provided；
Buffer layer is formed on substrate；
The semiconductor layer with source/drain region and channel region is formed on the buffer layer of display area；
First grid insulating layer is formed in the upper surface of semiconductor layer and buffer layer exposure；
Grid layer corresponding with channel region is formed in first grid insulating layer upper surface；
It deposits to form second grid insulation in the surface of grid layer exposure and the surface of part first grid insulating layer exposing
Layer；
Contact layer is formed in the surface of part second grid insulating layer；
Be sequentially etched contact layer, second grid insulating layer and first grid insulating layer according to sequence from top to bottom, with
It is formed in display area and is used to connect the first contact hole of display area circuit positioned at source area or drain region upper surface, and sealed
Fill the contact hole structure for being formed and being located above buffer layer in region；
Source-drain electrode layer is formed in the portion of upper surface of contact layer, and source-drain electrode layer covers the bottom and its side of the first contact hole
Wall, and contact hole structure is exposed；
Using source-drain electrode layer as exposure mask, etching is located at the buffer layer of contact hole structure bottom, to be formed for connecting encapsulation region
Second contact hole of circuit in domain.
In a preferred embodiment of the invention, etch to form above-mentioned second contact hole by HF medical fluid.
In a preferred embodiment of the invention, above-mentioned contact layer includes catalytic oxidation silicon layer and is located at catalytic oxidation silicon
The contact silicon nitride layer of layer upper surface；
In the above method, include: in the step of surface of part second grid insulating layer forms contact layer
It deposits to form catalytic oxidation silicon layer in the surface of part second grid insulating layer；
It deposits to form contact silicon nitride layer in the upper surface of catalytic oxidation silicon layer.
In a preferred embodiment of the invention, deposit to form contact silicon nitride layer in the upper surface of catalytic oxidation silicon layer
When, used NH3And SiH4Proportion be 1:1.
In a preferred embodiment of the invention, above-mentioned buffer layer includes buffering silicon nitride layer and buffering silicon oxide layer；
Wherein, the buffer oxide silicon layer is located at the top of the buffering silicon nitride layer or the buffering silicon nitride layer is located at
The top of the buffer oxide silicon layer.
In a preferred embodiment of the invention, above-mentioned first grid insulating layer includes gate oxidation silicon layer and is located at grid
Gate nitridation silicon layer on the silicon oxide layer of pole, gate nitridation silicon layer are located at the surface in display area interior raceway groove area.
In a preferred embodiment of the invention, the material of above-mentioned grid layer is molybdenum.
In a preferred embodiment of the invention, the material of above-mentioned second grid insulating layer is silicon nitride.
It is further explained with preparation method work of the specific embodiment to OLED display panel of the present invention with reference to the accompanying drawing
It states:
The present embodiment is related to a kind of preparation method of OLED display panel, and this method comprises the following steps:
Step S1 provides one and is provided with packaging area and display area (packaging area and display area be not in figure
Indicate) substrate 1, it is preferred that the substrate 1 be glass substrate, structure as shown in Figure 2.
Step S2, in forming buffer layer 2 on substrate 1, which includes buffering silicon nitride layer 21 and being located to buffer nitridation
The buffer oxide silicon layer 22 (the buffer oxide silicon layer 22 can be silica) of 21 upper surface of silicon layer, in other realities of the invention
It applies in example, silicon nitride layer 21 can also be buffered in the buffer layer 2 upper, for buffer oxide silicon layer 22 under, this has no effect on this hair
Bright purpose.In an embodiment of the present invention, the step of forming buffer layer 2 is specifically, according to sequence from bottom to up in base
Plate 1 is sequentially depositing buffering silicon nitride layer 21 and buffering silicon oxide layer 22, which can be chemical vapor deposition etc.；Such as figure
Structure shown in 3.
Step S3, being formed on display area inner part buffer layer 2 has source/drain region 31 and channel region 32
Semiconductor layer 3；The step specifically: show that the upper surface of inner part buffer oxide silicon layer 22 forms semiconductor material in region first
After the bed of material, the upper surface of the semiconductor material layer only covering part buffer oxide silicon layer 22 is carried out in the semiconductor material layer
Source and drain injection technology forms the semiconductor layer 3 with source/drain region 31 and channel region 32, structure as shown in Figure 4.
Step S4 forms first grid insulating layer 4 in the upper surface of semiconductor layer 3 and the exposure of buffer layer 2, of the invention
In embodiment, first grid insulating layer 4 includes gate oxidation silicon layer 41 and the gate nitridation on gate oxidation silicon layer 41
Silicon layer 42, gate nitridation silicon layer 42 are located at the surface in display area interior raceway groove area 32, structure as shown in Figure 5.
Step S5 forms grid layer 5 corresponding with channel region 32 in 4 upper surface of first grid insulating layer, it is preferred that grid
Pole layer 5 is molybdenum, the grid layer 5 or other conductive materials, this has no effect on the purpose of the present invention.Knot as shown in FIG. 6
Structure.
Step S6 continues to deposit second grid insulating layer 6 so that the surface of the exposure of grid layer 5 and part first grid to be insulated
The surface of 4 exposure of layer is covered, and the material of the second grid insulating layer 6 is silicon nitride, structure as shown in Figure 7.
Step S7 deposits to form (the catalytic oxidation silicon layer 71 of catalytic oxidation silicon layer 71 in 6 upper surface of second grid insulating layer
Can be silica), structure as shown in Figure 8.
Step S8 deposits to form contact silicon nitride layer 72 in 71 surface of catalytic oxidation silicon layer；71 He of catalytic oxidation silicon layer
It contacts silicon nitride layer 72 and forms contact layer 7, and in an embodiment of the present invention, deposit to form contact in catalytic oxidation silicon surface
When silicon nitride layer, NH3And SiH4Proportion be 1:1, or other proportion, as long as being able to achieve the purpose of the present invention；Such as
Structure shown in Fig. 9.
Step S9 is sequentially etched contact silicon nitride layer 72, catalytic oxidation silicon layer 71, second gate according to sequence from top to bottom
Pole insulating layer 6 and first grid insulating layer 4 are located at 4 upper surface of source/drain region for connecting to be formed in display area
The first contact hole 8 of display area circuit is connect, and forms the contact hole structure 9 being located above buffer layer 2 in packaging area；Such as
Structure shown in Fig. 10.
Step S10 forms source-drain electrode layer 10, and the covering of source-drain electrode layer 10 the in the portion of upper surface of contact silicon nitride layer 72
The bottom of one contact hole 8 and its side wall, i.e. part source-drain electrode layer 10 in semiconductor layer 3 source area or drain region 4 be in contact,
The source electrode in the namely OLED display panel of part source-drain electrode layer 10 being in contact with source area or drain region 4 or drain electrode.The source
Drain electrode layer 10 is exposed contact hole structure 9；Preferably, the source-drain electrode layer 10 be include the first titanium layer (Ti), aluminium layer (Al)
With the sandwich structure of the second titanium layer (the specific structure of source-drain electrode layer 10 does not indicate in figure)；Knot as shown in figure 11
Structure.
Step S11 is exposure mask with source-drain electrode layer 10, and the buffer layer 2 of 9 bottom of contact hole structure is located at by HF medical fluid etching
To form the second contact hole 11 for connecting packaging area circuit, and second contact hole 11 can during subsequent encapsulation
So that frame glue preferably fits together with substrate 1, prevent product carry out after packaging RA (Reliability Analysis,
Fail-safe analysis (high temperature/high humidity/high pressure)) when in the encapsulation region (frit) there are serious metal cracks (metal crack)
Or slight water wave shape fold and lead to encapsulation failure (Fail), to reach preferably packaging effect；Knot as shown in figure 12
Structure.
Wherein, in an embodiment of the present invention, above-mentioned buffering silicon nitride layer 21 with a thickness of Buffer oxide silicon layer
22 with a thickness ofGate oxidation silicon layer 41 with a thickness ofGate nitridation silicon layer 42 with a thickness of
Contact silicon nitride layer 72 with a thickness ofCatalytic oxidation silicon layer 71 with a thickness ofAnd 11 bottom of the second contact hole
The distance between portion and buffering 21 bottom of silicon nitride layer areCertainly it is required according to specific product, each tunic thickness can not
Together, this has no influence to the present invention.
It should be noted that catalytic oxidation silicon layer 71 why is first prepared referring to above-mentioned steps S7 and step S8, then
Although preparation contact silicon nitride layer 72 is since the upper surface of contact layer 7 and the bottom of the first contact hole 8 and its side wall are by source and drain
Pole layer 10 protects, but contact layer 7 still it is most of it is exposed outside, when etching to form the second contact hole using HF medical fluid and HF
Medical fluid contact, and HF medical fluid is much higher than the rate of etch to silicon nitride to the rate of etch of oxide, therefore, if contact layer is still oxygen
Compound is upper, and silicon nitride is under, then contact layer 7 has a biggish loss in etching process, and the present embodiment by oxide and
Silicon nitride is inverted, to avoid the excessive yield loss for causing product of loss amount of contact layer 7.
In addition, in an embodiment of the present invention, depositing to form contact nitridation in catalytic oxidation silicon surface referring to step S8
When silicon layer, the NH why uses3And SiH4Proportion be 1:1, be due to HF medical fluid to contact silicon nitride layer rate of etch be
It is smaller compared with catalytic oxidation silicon layer, so also will receive the etching of HF medical fluid when carrying out the etching of the second contact hole and cause
Partial contact layer loss.For this purpose, the NH that the present invention is formed a film by changing chemical vapor deposition (CVD)3And SiH4Gas match
Than changing HF medical fluid to the rate of etch of contact silicon nitride layer so as to adjust the film quality of contact silicon nitride layer.It is tied from actual verifying
Fruit sees that the rate of etch for contacting the rate of etch of silicon nitride layer can be adjusted from 1374A/min to 279A/min, improves obviously, certainly
NH3And SiH4It can also reduce HF medical fluid using other proportions, as long as the film quality of contact silicon nitride layer can be adjusted and contact is nitrogenized
The rate of etch of silicon layer.
It is not difficult to find that the present embodiment is embodiment of the method corresponding with the embodiment of above-mentioned OLED display panel, this reality
Applying example can work in coordination implementation with the embodiment of above-mentioned OLED display panel.It is mentioned in the embodiment of above-mentioned OLED display panel
Relevant technical details are still effective in the present embodiment, and in order to reduce repetition, which is not described herein again.Correspondingly, present embodiment
In the relevant technical details mentioned be also applicable in the embodiment of above-mentioned OLED display panel.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (14)
1. a kind of OLED display panel characterized by comprising
One substrate, is provided with packaging area and display area；
Buffer layer is set on the substrate；
Semiconductor layer is set on the buffer layer of the display area, and be provided in the semiconductor layer source area/
Drain region and channel region；
First grid insulating layer is set on the semiconductor layer and the part buffer layer；
Grid layer, it is corresponding with the channel region to be set on the first grid insulating layer；
Second grid insulating layer is set on the grid layer and part the first grid insulating layer；
Contact layer is set on the second grid insulating layer；
First contact hole is located in the display area, and through the contact layer to the source area or the upper table of drain region
Face is with the circuit for connecting the display area；
Second contact hole is located in the packaging area, and is used to connect institute into the buffer layer through the contact layer
State the circuit of packaging area；
Source-drain electrode layer is set to the portion of upper surface of the contact layer and bottom and its side wall of first contact hole.
2. OLED display panel according to claim 1, which is characterized in that the buffer layer include buffering silicon nitride layer and
Buffer oxide silicon layer；
Wherein, the buffer oxide silicon layer is located at the top for buffering silicon nitride layer or the buffering silicon nitride layer positioned at described
The top of buffer oxide silicon layer.
3. OLED display panel according to claim 1, which is characterized in that the first grid insulating layer includes grid oxygen
SiClx layer and the gate nitridation silicon layer on the gate oxidation silicon layer, the gate nitridation silicon layer are located at the viewing area
The surface in domain interior raceway groove area.
4. OLED display panel according to claim 1, which is characterized in that the material of the grid layer is molybdenum.
5. OLED display panel according to claim 1, which is characterized in that the material of the second grid insulating layer is
Silicon nitride.
6. OLED display panel according to claim 1, which is characterized in that the contact layer include catalytic oxidation silicon layer and
Contact silicon nitride layer positioned at catalytic oxidation silicon layer upper surface.
7. a kind of preparation method of OLED display panel, which is characterized in that described method includes following steps:
One substrate for being provided with packaging area and display area is provided；
Buffer layer is formed on the substrate；
The semiconductor layer with source/drain region and channel region is formed on the buffer layer of the display area；
First grid insulating layer is formed in the upper surface of the semiconductor layer and buffer layer exposure；
Grid layer corresponding with the channel region is formed in first grid insulating layer upper surface；
It deposits to form second grid in the surface of surface and part the first grid insulating layer exposing of grid layer exposure
Insulating layer；
Contact layer is formed in the surface of the part second grid insulating layer；
The contact layer, the second grid insulating layer and first grid insulation are sequentially etched according to sequence from top to bottom
Layer is located at the source area or drain region upper surface for connecting the display area circuit to be formed in the display area
The first contact hole, and in the packaging area formed be located at the buffer layer above contact hole structure；
Source-drain electrode layer is formed in the portion of upper surface of the contact layer, and the source-drain electrode layer covers the bottom of first contact hole
Portion and its side wall, and the contact hole structure is exposed；
Using the source-drain electrode layer as exposure mask, etching is located at the buffer layer of the contact hole structure bottom, to be formed for connecting
Connect the second contact hole of circuit in the packaging area.
8. the preparation method of OLED display panel according to claim 7, which is characterized in that etch to be formed by HF medical fluid
Second contact hole.
9. the preparation method of OLED display panel according to claim 7, which is characterized in that the contact layer includes contact
Silicon oxide layer and the contact silicon nitride layer positioned at catalytic oxidation silicon layer upper surface；
In the method, include: in the step of surface of the part second grid insulating layer forms the contact layer
It deposits to form the catalytic oxidation silicon layer in the surface of the part second grid insulating layer；
It deposits to form the contact silicon nitride layer in the upper surface of the catalytic oxidation silicon layer.
10. the preparation method of OLED display panel according to claim 8, which is characterized in that Yu Suoshu catalytic oxidation silicon
When the upper surface of layer deposits to form contact silicon nitride layer, used NH3And SiH4Proportion be 1:1.
11. the preparation method of OLED display panel according to claim 7, which is characterized in that the buffer layer includes slow
Rush silicon nitride layer and buffering silicon oxide layer；
Wherein, the buffer oxide silicon layer is located at the top for buffering silicon nitride layer or the buffering silicon nitride layer positioned at described
The top of buffer oxide silicon layer.
12. the preparation method of OLED display panel according to claim 7, which is characterized in that the first grid insulation
Layer includes gate oxidation silicon layer and the gate nitridation silicon layer on the gate oxidation silicon layer, gate nitridation silicon layer position
In the surface in display area interior raceway groove area.
13. the preparation method of OLED display panel according to claim 7, which is characterized in that the material of the grid layer
For molybdenum.
14. the preparation method of OLED display panel according to claim 7, which is characterized in that the second grid insulation
The material of layer is silicon nitride.
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| CN109659296B (en) * | 2018-12-18 | 2020-07-10 | 武汉华星光电半导体显示技术有限公司 | Test key for monitoring etching depth of O L ED panel and O L ED large panel |
| KR20200115887A (en) | 2019-03-28 | 2020-10-08 | 삼성디스플레이 주식회사 | Display panel and device including the same |
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| CN104465674A (en) * | 2014-12-31 | 2015-03-25 | 深圳市华星光电技术有限公司 | LTPS product structure and manufacturing method thereof |
| CN105161512A (en) * | 2015-08-03 | 2015-12-16 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof, display panel and manufacturing method thereof |
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| CN103531445A (en) * | 2013-10-12 | 2014-01-22 | 上海和辉光电有限公司 | Technique for reducing depth-to-width ratio of LTPS (low temperature poly silicon) contact hole |
| CN104465674A (en) * | 2014-12-31 | 2015-03-25 | 深圳市华星光电技术有限公司 | LTPS product structure and manufacturing method thereof |
| CN105161512A (en) * | 2015-08-03 | 2015-12-16 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof, display panel and manufacturing method thereof |
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