CN108807424A - A kind of production method of array substrate, array substrate and display panel - Google Patents
A kind of production method of array substrate, array substrate and display panel Download PDFInfo
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- CN108807424A CN108807424A CN201810680861.7A CN201810680861A CN108807424A CN 108807424 A CN108807424 A CN 108807424A CN 201810680861 A CN201810680861 A CN 201810680861A CN 108807424 A CN108807424 A CN 108807424A
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000004615 ingredient Substances 0.000 claims description 9
- 229910004205 SiNX Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000012528 membrane Substances 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 51
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- CWYNVVGOOAEACU-UHFFFAOYSA-N Fe2+ Chemical compound [Fe+2] CWYNVVGOOAEACU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 210000003739 neck Anatomy 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
This application discloses a kind of production method of array substrate, array substrate and display panel, this method includes providing a substrate；First grid insulating layer, film layer, second grid insulating layer and gate metal layer are set gradually on substrate；Pattern etched is carried out to gate metal layer and second grid insulating layer successively, and detects whether in etching process to etch into film layer；If etching into film layer, stop etching, is etched to avoid first grid insulating layer；Wherein, film layer material is different from second grid insulating layer material.By the above-mentioned means, the application can improve the uniformity of ion implantation, enhance electrical stability.
Description
Technical field
This application involves display technology fields, and in particular to a kind of production method of array substrate, array substrate and display
Panel.
Background technology
LTPS (Low Temperature Poly-silicon, low temperature polycrystalline silicon) technology is gradually ripe and is widely used in
The high-res product such as mobile phone, current LTPS making technologies are complicated, the very accurate costliness of equipment, therefore to improve production capacity and reduction
Cost can only save light shield to realize by technological improvement.The production of photoresist stripping machine can be promoted by etching (Re-etch) technology again
Can, therefore this technology is all actively being studied by many producers, is maximized in the hope of production capacity.
Present inventor has found in long-term R & D, then there is also some defects for etching technique, mainly due to saving
Slightly after light shield, using grid as auxiliary positioning after be ion implanted, and GI (Gate can be first generated before forming grid layer
Insulator, gate insulating layer) to form MOS-FET (metal-oxide semiconductor Field Effect
Transistor, metal oxide semiconductor field effect tube) structure, therefore needed across GI when ion implantation, current GI thickness
GenerallyIon implantation needs the energy of about 70keV or more, to board stable operation and TFT (Thin
Film Transistor, thin film transistor (TFT)) electrically (mobility and threshold voltage) have larger impact.
It derives later and carries out GI etchings while carrying out grid layer etching, that is, use dry etching to be selected by adjusting gas
It selects and is etched come the GI in addition to being covered except grid than first etching gate shapes, reduce GI thickness, improve ion and plant
Enter process, ion implantation energy can be greatly reduced, it is ensured that steady production.Present inventor is it has furthermore been found that due to right
Metal and nonmetallic priority are etched, it is difficult to take into account the uniformity of grid line width and the gate insulating layer etched away, and then surplus
The extremely difficult control of uniformity of remaining gate insulating layer, easily causes electrical unevenness.
Invention content
The application mainly solves the problems, such as to be to provide a kind of production method of array substrate, array substrate and display panel,
The uniformity that ion implantation can be improved enhances electrical stability.
In order to solve the above technical problems, the application is the technical solution adopted is that provide a kind of production method of array substrate,
This method includes：One substrate is provided；Set gradually on substrate first grid insulating layer, film layer, second grid insulating layer and
Gate metal layer；Pattern etched is carried out to gate metal layer and second grid insulating layer successively, and is detected in etching process
Whether film layer is etched into；If etching into film layer, stop etching, is etched to avoid first grid insulating layer；Wherein,
Film layer material is different from second grid insulating layer material.
In order to solve the above technical problems, another technical solution that the application uses is to provide a kind of array substrate, the array
Substrate includes the substrate being stacked, first grid insulating layer, film layer, second grid insulating layer and gate metal layer, film
Layer material is different from second grid insulating layer material.
In order to solve the above technical problems, another technical solution that the application uses is to provide a kind of display panel, the display
Panel includes the liquid crystal between the color membrane substrates that array substrate and array substrate are oppositely arranged and array substrate and color membrane substrates
Layer, array substrate are above-mentioned array substrate.
Through the above scheme, the advantageous effect of the application is：By making first grid insulating layer, thin successively on substrate
The material of film layer, second grid insulating layer and gate metal layer, film layer is different from the material of second grid insulating layer；Then according to
It is secondary that gate metal layer and second grid insulating layer are etched, and detect whether in etching process to etch into film layer；Such as
Fruit detects etches into film layer at present, then stops etching, be etched to avoid first grid insulating layer；Due in etching process
Whether middle real time monitoring etches into film layer to control progress of etching so that after stopping etching, leaves performance and is guaranteed and does not have
Have and be etched/few first grid the insulating layer of the amount of being etched, improves the uniformity of ion implantation, enhance electrical stability.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.Wherein：
Fig. 1 is the structural schematic diagram of etching normal-gate insulating layer, polysilicon layer and gate metal layer in the prior art；
Fig. 2 is the structural schematic diagram of etching post tensioned unbonded prestressed concrete insulating layer, polysilicon layer and gate metal layer in the prior art；
Fig. 3 is the flow diagram of one embodiment of production method of array substrate provided by the present application；
Fig. 4 be array substrate provided by the present application one embodiment of production method in etch before array substrate structural representation
Figure；
Fig. 5 be array substrate provided by the present application one embodiment of production method in etch after array substrate structural representation
Figure；
Fig. 6 is the flow diagram of another embodiment of production method of array substrate provided by the present application；
Fig. 7 be array substrate provided by the present application another embodiment of production method in etch before the structure of array substrate show
It is intended to；
Fig. 8 be array substrate provided by the present application another embodiment of production method in etch after the structure of array substrate show
It is intended to；
Fig. 9 is the structural schematic diagram of one embodiment of array substrate provided by the present application；
Figure 10 is the structural schematic diagram of one embodiment of display panel provided by the present application.
Specific implementation mode
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making performing creative labour
Embodiment shall fall in the protection scope of this application.
Film layer structure before gate etch is as shown in Figure 1, due to needing to be etched gate metal layer 11, then carries out grid
Insulating layer 12 etches, and is related to metal and nonmetallic etching, therefore is difficult to ensure the uniformity of the gate insulating layer 12 after etching, is formed
The structure being illustrated in fig. 2 shown below, the upper surface that gate insulating layer 12 is not covered by gate metal layer 11 is not in the same horizontal line；?
The depth of the ion of implanted polysilicon layer 13 and dosage will appear difference when carrying out heavy doping, easily cause electric characteristic abnormality.
It is the flow diagram of one embodiment of production method of array substrate provided by the present application refering to Fig. 3 to Fig. 5, Fig. 3,
This method includes：
Step 31：One substrate 41 is provided.
The substrate 41 is transparent substrate, it is therefore preferable to glass substrate；Substrate 41 can be pre-processed, such as：Successively
Substrate 41 is cleaned using acetone, methanol, deionized water, then removes the impurity and oxide layer on 41 surface of substrate.
Step 32：First grid insulating layer 42, film layer 43,44 and of second grid insulating layer are set gradually on substrate 41
Gate metal layer 45.
Using chemical vapour deposition technique or physical vaporous deposition sequentially formed on substrate 41 first grid insulating layer 42,
Film layer 43, second grid insulating layer 44 and gate metal layer 45, as shown in Figure 4.
The material of film layer 43 is different from the material of second grid insulating layer 44, and certainly, film layer 43 and second grid are exhausted
Part chemical element can also be identical in the material of edge layer 44；Film layer 43 is that one layer and its thin film layer, thickness are much small
In the thickness of first grid insulating layer 42 and second grid insulating layer 44；The material of gate metal layer 45 can be molybdenum, aluminium, copper,
It is one or more in titanium.
Step 33：Pattern etched is carried out to gate metal layer 45 and second grid insulating layer 44 successively, and etched
It detects whether to etch into film layer 43 in journey.
After foring gate metal layer 45, gate metal layer 45 and second grid insulating layer 44 are patterned successively
Processing, loses the subregion of gate metal layer 45 and second grid insulating layer 44 using dry etching or wet etching
It carves, in order not to etch into first grid insulating layer 44, detects whether using instrument to etch into film layer 43 in etching process.
Step 34：If etching into film layer 43, stop etching, is etched to avoid first grid insulating layer 42.
In etching process, film layer 43 is etched at present if detected, is stopped etching, it is exhausted to avoid first grid
Edge layer 42 is etched, and since the thickness of film layer 43 is extremely thin, thickness can be ignored, and ensures the film layer left after etching
The upper surface that (first grid insulating layer 42) is uncovered is in same level, and thickness is identical, as shown in Figure 5.
When the depth of ion implantation meets predetermined depth, carrier mobility is larger, and the depth being ion implanted is too low
Or when excessively high, carrier mobility is smaller；Thus when the gate insulating layer thickness left is relatively low or higher, carrier mobility
It can reduce.
After stopping etching, the preferable first grid insulating layer of uniformity 42 is left.Due to first grid insulating layer 42
Thickness is not etched to not less than the minimum thickness ensured needed for performance；Moreover, the key parameter of GI films be its film thickness and
Dielectric constant, the guaranteed GI films of thickness are conducive to improve the threshold voltage of TFT, while uniformity improves can improve ion
The uniformity of implantation promotes carrier mobility, and then enhances the electrical stability of TFT.
Be different from the prior art, present embodiments provide a kind of production method of array substrate, by substrate 41 according to
Secondary making first grid insulating layer 42, film layer 43, second grid insulating layer 44 and gate metal layer 45, the material of film layer 43
It is different from the material of second grid insulating layer 44；Then gate metal layer 45 and second grid insulating layer 44 are lost successively
It carves, and detects whether in etching process to etch into film layer 43；If detecting and etching into film layer 43 at present, stop losing
It carves, is etched to avoid first grid insulating layer 42；Due to monitored in real time in etching process whether etch into film layer 43 with
Control progress of etching so that after stopping etching, leave performance be guaranteed and be not etched/amount of being etched it is few first
Gate insulating layer 42 improves the uniformity of ion implantation, enhances the electrical stability of TFT.
It is the flow signal of another embodiment of production method of array substrate provided by the present application refering to Fig. 6 to Fig. 8, Fig. 6
Figure, this method include：
Step 61：One substrate 71 is provided.
Step 62：Light shielding layer 72, buffer layer 73 and polysilicon layer 74 are sequentially formed on substrate 71.
Light shielding layer 72 can be made of ferrous material；Buffer layer 73 may include the SiN being stackedxLayer 731
And SiOxLayer 732, SiNxThe main function of layer 731 is the impurity completely cut off on substrate 71, buffer interface stress, SiOxLayer 732 is used for
Do the insulating layer of laser annealing；It, can first deposition of amorphous silicon layers (show in figure on buffer layer 73 after forming light shielding layer 72
Go out), then method for annealing is (such as：Quasi-molecule laser annealing method) convert amorphous silicon layer to polysilicon layer 74.
Step 63：First grid insulating layer 75, film layer 76, second grid insulating layer are set gradually on polysilicon layer 74
77 and gate metal layer 78.
First grid insulating layer 75, film layer 76 and second grid insulating layer are respectively formed using chemical vapour deposition technique
77, gate metal layer 78 is formed using physical vaporous deposition, as shown in Figure 7；Wherein, first grid insulating layer 75, film layer
76 and second grid insulating layer 77 thickness summation it is identical as the thickness of gate insulating layer in the prior art.
It, can be by adjusting pressure, power, TEOS when using chemical vapor deposition first grid insulating layer 75
(tetraethyl silicate resin) and O2Amount etc. form the very high first grid insulating layer 75 of one layer of consistency, formed using TEOS materials
Uniform film quality is easily formed when first grid insulating layer 75 and stablizes film thickness, and the material of first grid insulating layer 75 is SiOxOr SiOx
And SiNxAliasing；After the thickness of first grid insulating layer 75 is etched with gate insulating layer in the prior art ideally
Remaining thickness is identical, and the performance of first grid insulating layer 75 be guaranteed and was not etched/and the amount of being etched is few.
It is formed after first grid insulating layer 75, the processing of short time is carried out to the interface of first grid insulating layer 75, it can
To utilize NH3、N2Or N2The plasma of the gases such as O reacts to form extremely thin film layer with 75 surface of first grid insulating layer
76；The material of film layer 76 is different from the material of second grid insulating layer 77；The material of film layer 76 is SiNx, thickness is less than
The material of second grid insulating layer 77 is SiOx, the consistency of first grid insulating layer 75 is more than second grid insulation
The consistency of layer 77.
Step 64：Pattern etched is carried out to gate metal layer 78 and second grid insulating layer 77 successively.
After forming gate metal layer 78, dry etching can be utilized to gate metal layer 78 and second grid insulating layer
77 carry out pattern etched.
Step 65：Whether detected in etching process in the film layer etched into has predicted elemental ingredient.
In etching process, the film etched into is detected using etching end point monitor (EPD, End point detector)
Elemental composition in layer, etching end point monitor can detect the ingredient in film layer, so as to according in etching process at
The variation divided stops controlling etch process.
Step 66：If detecting has predicted elemental ingredient in the film layer etched into, stop etching, to avoid first
Gate insulating layer 75 is etched.
If the material of first grid insulating layer 75 is SiOxAnd SiNxAliasing or SiOx, the material of film layer 76 is
SiNx, the material of second grid insulating layer 77 is SiOx, then predicted elemental ingredient is nitrogen；It is examined when with etching end point monitor
Measure current etch to film layer in containing nitrogen when, just stop etching processing procedure, is eclipsed to avoid first grid insulating layer 75
It carves.
Be different from the prior art, present embodiments provide a kind of production method of array substrate, first on substrate 71 according to
Secondary making sequentially forms light shielding layer 72, buffer layer 73 and polysilicon layer 74, first grid insulating layer 75, film layer 76, second
Gate insulating layer 77 and gate metal layer 78；Then gate metal layer 78 and second grid insulating layer 77 are patterned successively
Etching, and detect in the film layer etched into whether there is predicted elemental ingredient in etching process；If detecting current etching
Film layer in have predicted elemental ingredient, then stop etching, be etched to avoid first grid insulating layer 75；Due to etched
Monitored in real time in journey and whether etch into film layer 76 to control progress of etching, leave performance be guaranteed and be not etched/
The few first grid insulating layer 75 of the amount of being etched, improves the uniformity of ion implantation, enhances electrical stability.
It is the structural schematic diagram of one embodiment of array substrate provided by the present application refering to Fig. 9, Fig. 9, which includes
Substrate 91, first grid insulating layer 92, film layer 93, second grid insulating layer 94 and the gate metal layer 95 being stacked are thin
The material of film layer 93 is different from the material of second grid insulating layer 94.
0, Figure 10 is that the structural schematic diagram of one embodiment of the display panel provided by the present application display panel includes refering to fig. 1
Array substrate 101, the color membrane substrates 102 being oppositely arranged with array substrate 101 and array substrate 101 and color membrane substrates 102 it
Between liquid crystal layer 103, array substrate 101 be above-described embodiment in array substrate.
Array substrate 101 include be stacked substrate, first grid insulating layer, film layer, second grid insulating layer and
Gate metal layer (not shown)；Wherein, the thickness of first grid insulating layer meets the thickness condition needed for ion doping,
Thickness is not less than the minimum thickness needed for performance.
It these are only embodiments herein, be not intended to limit the scope of the claims of the application, it is every to be said using the application
Equivalent structure or equivalent flow shift made by bright book and accompanying drawing content is applied directly or indirectly in other relevant technology necks
Domain includes similarly in the scope of patent protection of the application.
Claims (10)
1. a kind of production method of array substrate, which is characterized in that including：
One substrate is provided；
First grid insulating layer, film layer, second grid insulating layer and gate metal layer are set gradually over the substrate, it is described
Film layer material is different from the second grid insulating layer material；
Pattern etched is carried out to the gate metal layer and the second grid insulating layer successively, and is detected in etching process
Whether the film layer is etched into；
If etching into the film layer, stop etching, is etched to avoid the first grid insulating layer.
2. the production method of array substrate according to claim 1, which is characterized in that
The material of the film layer is SiNx, thickness is less thanThe material of first grid insulating layer is SiOxOr SiOxWith
SiNxAliasing, the material of the second grid insulating layer is SiOx。
3. the production method of array substrate according to claim 2, which is characterized in that
The consistency of the first grid insulating layer is more than the consistency of the second grid insulating layer.
4. the production method of array substrate according to claim 1, which is characterized in that
Described the step of detecting whether to etch into the film layer, including：
Whether detect in the film layer etched into has predicted elemental ingredient；
If described etch into the film layer, the step of stopping etching, including：
If detecting has predicted elemental ingredient in the film layer etched into, stop etching.
5. the production method of array substrate according to claim 4, which is characterized in that
Elemental composition in the film layer etched into using the detecting of etching end point monitor, the predicted elemental ingredient are nitrogen.
6. the production method of array substrate according to claim 1, which is characterized in that
The first grid insulating layer, the film layer and second grid insulation are respectively formed using chemical vapour deposition technique
Layer, the gate metal layer is formed using physical vaporous deposition；Using dry etching to the gate metal layer and described
Two gate insulating layers carry out pattern etched.
7. the production method of array substrate according to claim 1, which is characterized in that
It is described to set gradually first grid insulating layer, film layer, second grid insulating layer and gate metal layer over the substrate
The step of before, including：
Light shielding layer, buffer layer and polysilicon layer are sequentially formed over the substrate；Wherein, the buffer layer includes being stacked
SiNxLayer and SiOxLayer.
8. a kind of array substrate, including be stacked substrate, first grid insulating layer, film layer, second grid insulating layer and
Gate metal layer, the film layer material are different from the second grid insulating layer material.
9. a kind of display panel, which is characterized in that the color membrane substrates being oppositely arranged including array substrate, with the array substrate with
And the liquid crystal layer between the array substrate and the color membrane substrates, the array substrate are battle array as described in claim 8
Row substrate.
10. display panel according to claim 9, which is characterized in that
The array substrate includes the substrate being stacked, first grid insulating layer, film layer, second grid insulating layer and grid
Metal layer, wherein the thickness of the first grid insulating layer meets the thickness condition needed for ion doping.
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| CN114730534A (en) * | 2019-11-20 | 2022-07-08 | Lg伊诺特有限公司 | Substrate for display |
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