CN103531445A - Technique for reducing depth-to-width ratio of LTPS (low temperature poly silicon) contact hole - Google Patents

Technique for reducing depth-to-width ratio of LTPS (low temperature poly silicon) contact hole Download PDF

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CN103531445A
CN103531445A CN201310475842.8A CN201310475842A CN103531445A CN 103531445 A CN103531445 A CN 103531445A CN 201310475842 A CN201310475842 A CN 201310475842A CN 103531445 A CN103531445 A CN 103531445A
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contact hole
ltps
width ratio
etching
technique
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CN103531445B (en
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杨东伦
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EverDisplay Optronics Shanghai Co Ltd
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EverDisplay Optronics Shanghai Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Inorganic Chemistry (AREA)
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Abstract

The invention discloses a technique for reducing a depth-to-width ratio of an LTPS (low temperature poly silicon) contact hole. The technique comprises a pre-etching step, wherein the pre-etching step is as follows: etching a preset thickness in the surface of a film downwards to form a reference surface, wherein the vertical height of the reference surface is smaller than that of the surface of the film; manufacturing the LTPS contact hole in the reference surface downwards. According to the technique for reducing the depth-to-width ratio of the LTPS contact hole, which is disclosed by the invention, the pre-etching step is added to an LTPS contact manufacturing technique, so that the thickness of the film of the contact hole area is reduced, a dip angle of the finally formed contact hole is also reduced, and the performances of devices are improved.

Description

A kind of process that reduces LTPS contact hole depth-to-width ratio
Technical field
The present invention, about a kind of LTPS process, refers in particular to a kind of process of the LTPS of reducing contact hole depth-to-width ratio.
Background technology
At common LTPS(low temperature polycrystalline silicon) in technique, the manufacture craft of contact hole (Contact Hole, CT) is generally:
CT layer: PECVD film forming-photoetching-etching, be etched to metal level and polysilicon layer, form contact hole;
DL layer: Sputter film forming-photoetching-etching, etches away unnecessary interconnecting metal.
Coordinate shown in Figure 1ly, the computing formula at LTPS contact hole inclination angle is:
θ = arctan h 0.5 ( W up - W down )
Wherein, θ is contact hole inclination angle, and h is the thickness that needs the contact hole of etching, W upfor the length of side size of contact hole upper opening, W downlength of side size for contact hole lower openings.
Cooperation is referring to shown in Fig. 2, and common LTPS film layer structure respectively was from lower to upper before second grid layer (Gate Line2, GL2) is made: glass substrate 1, a SiNx layer 2, SiO 2layer the 3, the 2nd SiNx layer 4, wherein, SiO 2in layer 3, also comprise polysilicon layer 5(Poly-Si), the 2nd SiNx layer 4 also comprises shown in metal level 6(figure being metal M o).
Under common process, the darkest contact hole needs downward etching to surpass
Figure BDA0000394612720000012
rete, the length of side of contact hole upper opening is 2.5 μ m, the length of side of contact hole lower openings is 0.5 μ m, by above-mentioned computing formula, can be obtained, the limit inclination angle of contact hole is 38.66 °.
Complicated along with technological design, the size of contact hole constantly declines, and contact hole needs the thickness of etching also constantly to increase, and the decline of contact hole size can make the depth-to-width ratio of contact hole expand, and cannot produce comparatively mild contact hole inclination angle.If the inclination angle of contact hole is excessive, may causes the rete on it to cover inequality, thereby cause fracture.If obtain less contact hole inclination angle, just must reduce the area of contact hole lower openings, can affect interlinking reliability so again.
Summary of the invention
In view of the problems referred to above, the invention provides a kind of process of the LTPS of reducing contact hole depth-to-width ratio, the method has a pre-etch step, and described pre-etch step comprises:
On film surface, etching one is set thickness downwards, forms a vertical height lower than the datum level on described film surface;
From described datum level, make downwards and form LTPS contact hole.
Further improvement of the present invention is, described pre-etch step further comprises:
1) on described film surface, form a metal level;
2) using this metal level as mask, implement described pre-etch step.
Further improvement of the present invention is, adopts the photoetching process of half-penetration type mask or gray tone mask, metal level described in etching.
The present invention, by increase the pre-etch step of a step in LTPS contact hole manufacture craft, reduces the thickness in contact hole region, and the inclination angle of the contact hole finally forming also reduces thereupon, has improved the performance of device.
Accompanying drawing explanation
Fig. 1 is the enlarged diagram of common LTPS contact hole.
Fig. 2 is the schematic diagram of common LTPS film layer structure before GL2 layer is made.
Fig. 3 is that in a kind of embodiment of the present invention, LTPS film layer structure completes making formation metal level schematic diagram afterwards.
Fig. 4 is that in a kind of embodiment of the present invention, LTPS film layer structure completes pre-etch step schematic diagram afterwards
Fig. 5 forms the GL2 layer schematic diagram of LTPS film layer structure afterwards in a kind of embodiment of the present invention.
Fig. 6 is the first effect schematic diagram that utilizes the contact hole that the present invention produces.
Fig. 7 is the second effect schematic diagram that utilizes the contact hole that the present invention produces.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Preferably, a kind of process that reduces LTPS contact hole depth-to-width ratio of the present invention, when making the GL2 layer of LTPS, implements described pre-etch step, comprises the following steps:
1) coordinate referring to shown in Fig. 3, the film surface in LTPS contact hole region beyond 7, adopts the photoetching process of half-penetration type mask (HTM) or gray tone mask (GTM), makes to form one and have the poor metal level of certain altitude 8;
2) using this metal level 8 as mask, on the film surface of described LTPS contact hole to be formed, the 71 downward etchings one in region are set thickness, to reduce the thickness in contact hole region 7, cooperation is referring to shown in Fig. 4, form the trapezoidal pre-etched volume 72 that a upper shed size is greater than under shed size after etching, and in the bottom surface of this pre-etched volume 72, form a vertical height lower than the film surface 71 of described LTPS contact hole for making the datum level 73 of contact hole;
3) coordinate referring to shown in Fig. 5, described metal level 8 is carried out to whole etching, leave the figure needing, form the GL2 layer 9 of LTPS.From described datum level 73, make downwards and form described LTPS contact hole again.
The present invention carries out pre-etch step when making GL2 layer, is because the etching precision of GL1 layer requires highlyer, adopts the formation of half-penetration type mask or the wayward nitride of gray tone masking process.Using the metal level for making GL2 layer as mask, in contact hole region, first pre-etching one is set the rete of thickness, the thickness in contact hole region is reduced, form described datum level, afterwards by the whole etching of metal level, leave the figure needing, form the GL2 layer of LTPS, finally from described datum level, make downwards and form LTPS contact hole again.
By method of the present invention, LTPS contact hole region, through after pre-etching, has effectively reduced the thickness of the contact hole that needs etching.In a preferred embodiment, after pre-etching, the thickness of contact hole has reduced
Figure BDA0000394612720000031
also need the thickness h' of the contact hole of etching to be
Figure BDA0000394612720000032
Cooperation is referring to shown in Fig. 6, is the first effect schematic diagram that utilizes the contact hole that the present invention produces, and guaranteeing the length of side size W of contact hole upper opening upand the length of side of contact hole lower openings size W downin constant situation, the contact hole of the making face of contact hole after original film surface 71 drops to pre-etching made datum level 73, and thickness has reduced
Figure BDA0000394612720000033
also need the thickness h' of the contact hole of etching to be computing formula by contact hole inclination angle can obtain, and after pre-etching, the inclination angle theta of contact hole is decreased to 30.96 °, can generate better other retes thereon.
Cooperation is referring to shown in Fig. 7, is the second effect schematic diagram that utilizes the contact hole that the present invention produces, and guaranteeing the length of side size W of contact hole inclination angle theta and contact hole upper opening upin constant situation, the contact hole of the making face of contact hole after original film surface 71 drops to pre-etching made datum level 73, and thickness has reduced
Figure BDA0000394612720000035
also need the thickness h' of the contact hole of etching to be
Figure BDA0000394612720000036
computing formula by contact hole inclination angle can obtain, after pre-etching, and the length of side of contact hole lower openings size W' downbe increased to 1 μ m, compare and expanded 2 times before, the area of contact hole lower openings is compared and has been expanded 4 times before, can greatly promote interlinking reliability.
The above is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, within not departing from the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.

Claims (3)

1. a process that reduces LTPS contact hole depth-to-width ratio, is characterized in that: the method has a pre-etch step, and described pre-etch step comprises:
On film surface, etching one is set thickness downwards, forms a vertical height lower than the datum level on described film surface;
From described datum level, make downwards and form LTPS contact hole.
2. the process that reduces LTPS contact hole depth-to-width ratio as claimed in claim 1, is characterized in that: described pre-etch step further comprises:
1) on described film surface, form a metal level;
2) using this metal level as mask, implement described pre-etch step.
3. the process that reduces LTPS contact hole depth-to-width ratio as claimed in claim 2, is characterized in that adopting the photoetching process of half-penetration type mask or gray tone mask, metal level described in etching.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106920812A (en) * 2015-12-25 2017-07-04 上海和辉光电有限公司 A kind of OLED display panel and preparation method thereof
CN110828485A (en) * 2019-11-19 2020-02-21 京东方科技集团股份有限公司 Display substrate, preparation method thereof and display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59191334A (en) * 1983-04-13 1984-10-30 Mitsubishi Electric Corp Etching method for semiconductor substrate
JPS61280632A (en) * 1985-05-08 1986-12-11 Sanyo Electric Co Ltd Semiconductor device
TW201310525A (en) * 2011-05-12 2013-03-01 Lam Res Corp Method for achieving smooth side walls after Bosch etch process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59191334A (en) * 1983-04-13 1984-10-30 Mitsubishi Electric Corp Etching method for semiconductor substrate
JPS61280632A (en) * 1985-05-08 1986-12-11 Sanyo Electric Co Ltd Semiconductor device
TW201310525A (en) * 2011-05-12 2013-03-01 Lam Res Corp Method for achieving smooth side walls after Bosch etch process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106920812A (en) * 2015-12-25 2017-07-04 上海和辉光电有限公司 A kind of OLED display panel and preparation method thereof
CN106920812B (en) * 2015-12-25 2019-10-25 上海和辉光电有限公司 A kind of OLED display panel and preparation method thereof
CN110828485A (en) * 2019-11-19 2020-02-21 京东方科技集团股份有限公司 Display substrate, preparation method thereof and display device

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Address after: 1568 Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201506

Patentee after: Shanghai Hehui optoelectronic Co., Ltd

Address before: 201508, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District

Patentee before: EverDisplay Optronics (Shanghai) Ltd.