CN104022063A - Method for forming shallow trench - Google Patents
Method for forming shallow trench Download PDFInfo
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- CN104022063A CN104022063A CN201310066219.7A CN201310066219A CN104022063A CN 104022063 A CN104022063 A CN 104022063A CN 201310066219 A CN201310066219 A CN 201310066219A CN 104022063 A CN104022063 A CN 104022063A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000010410 layer Substances 0.000 claims abstract description 112
- 238000005530 etching Methods 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000011241 protective layer Substances 0.000 claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 34
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 238000006902 nitrogenation reaction Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a method for forming a shallow trench. The method for forming the shallow trench includes: providing a semiconductor substrate having a grid layer and a mask layer stacked in sequence from bottom to top; selectively removing the mask layer to form a mask graph; etching the grid layer to form a grid; forming a protective layer on a side wall of the grid; and etching the semiconductor substrate to form a shallow trench. The method for forming the shallow trench provided by the invention can enable the grid to have a smooth and flat side wall, thereby ensuring electrical performance of the grid.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of shallow slot.
Background technology
Etching technics (etching process) is removed the thin layer of not sheltered by mask layer, thereby on film, obtains the technique with identical figure on mask layer.In ic manufacturing process, through mask alignment, exposure and development, on mask layer, run off required figure, or be directly depicted in and on mask layer, produce figure with electron beam, then dielectric film (as silica, silicon nitride, polysilicon) or the metallic film (as aluminium and alloy thereof) this figure accurately transferred to below mask layer get on, and produce required thin layer pattern.Etching be exactly with chemistry, method physics or that simultaneously use chemistry and physics, selectively that a part of thin layer of not sheltered by mask layer is removed, thus on film, obtain with mask layer on all four figure.
Desirable etching technics must have following characteristics: 1. anisotropic etching, only have vertical etching, and there is no horizontal undercutting.Like this guarantee accurately on the film being etched, copy with mask layer on all four geometric figure; 2. good Etch selectivity, all much smaller than the etch rate of the film that is etched to the etch rate of the mask layer as mask and another layer film under it or material, with the validity that guarantees that in etching process, mask layer is sheltered, unlikely generation damages the other materials below film because of over etching; 3. manufacturing batch is large, controls easily, and cost is low, and environmental pollution is few, is applicable to industrial production.
But in actual mechanical process, because the restriction of each side condition can cause etching cannot reach desirable effect.For example, in the process for fabrication of semiconductor device of leading portion, when utilizing etching technics to prepare grid or shallow-trench isolation, there will be problem as shown in Figure 1, in Fig. 1, on substrate 110, there is the grid 120 obtaining according to mask pattern 130 etchings, between described grid 120, by the shallow slot 111 in substrate 110, realize isolation, but the sidewall 121 of described grid 120 there will be neck shape (necking, as shown in annular region), thereby affect the electrical property of device.
Therefore, how to provide a kind of formation method of shallow slot, can make grid there is smooth, smooth sidewall, thereby guarantee the electrical property of device, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the present invention is to provide a kind of formation method of shallow slot, can make grid there is smooth, smooth sidewall, thereby guarantee the electrical property of device.
For solving the problems of the technologies described above, the invention provides a kind of formation method of shallow slot, the formation method of described shallow slot comprises:
Semiconductor substrate is provided, in described Semiconductor substrate, there is the grid layer and the mask layer that stack gradually from bottom to top;
Mask layer described in selective removal, to form mask pattern;
Described grid layer is carried out to etching, to form grid;
Sidewall at described grid forms a protective layer; And
Described Semiconductor substrate is carried out to etching, to form shallow slot.
Preferably, the step that forms a protective layer at the sidewall of described grid comprises:
Described grid is carried out to nitrogen treatment to form described protective layer.
Preferably, the step that forms a protective layer at the sidewall of described grid comprises:
In described grid, described mask pattern and described Semiconductor substrate, prepare a sacrifice layer;
Sacrifice layer described in etching, and retain the described sacrifice layer on the sidewall of described grid, to form described protective layer.
Preferably, adopt the method for chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald, in described grid, described mask pattern and described Semiconductor substrate, prepare a sacrifice layer.
Preferably, the material of described protective layer is one or more the combination in silicon dioxide, silicon nitride, amorphous carbon, organic substance or metal.
Preferably, between described Semiconductor substrate and described grid layer, also comprise an etching stop layer.
Preferably, described mask layer is individual layer mask layer or multi-layer mask layer.
Preferably, nitride mask layer and the oxide mask layer of described multi-layer mask layer for stacking gradually from bottom to top.
Preferably, described grid layer is phosphorus doping grid layer.
Preferably, in described grid layer, the doping content of phosphorus is 1E19/cm
3～1E20/cm
3.
Compared with prior art, the formation method of shallow slot provided by the invention has the following advantages:
The formation method of shallow slot provided by the invention; first carry out the etching of grid; then the sidewall at described grid forms after a protective layer; again described Semiconductor substrate is carried out to etching, to form shallow slot, compared with prior art; when described Semiconductor substrate is carried out to etching; described protective layer can protect described grid not to be damaged, and makes described grid have smooth, smooth sidewall, thereby guarantees the electrical property of described grid.
Accompanying drawing explanation
Fig. 1 is the profile of grid structure of the prior art;
Fig. 2 is the flow chart of formation method of the shallow slot of one embodiment of the invention;
The schematic diagram of the formation method of the shallow slot that Fig. 3 a-Fig. 3 e is one embodiment of the invention;
The schematic diagram of the formation method of the shallow slot that Fig. 4 a-Fig. 4 c is another embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, the manufacture method of the formation method of shallow slot of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In the following passage, with reference to accompanying drawing, with way of example, the present invention is more specifically described.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is to provide a kind of formation method of shallow slot; the formation method of this shallow slot is first carried out etching to grid layer; to form grid; then the sidewall at described grid forms a protective layer; finally described Semiconductor substrate is carried out to etching, to form shallow slot, because described protective layer is when carrying out etching to described Semiconductor substrate; can protect described grid not to be damaged, make described grid there is smooth, smooth sidewall.
In conjunction with above-mentioned core concept, the invention provides a kind of formation method of shallow slot, comprising:
Step S01, provides Semiconductor substrate, has the grid layer and the mask layer that stack gradually from bottom to top in described Semiconductor substrate;
Step S02, mask layer described in selective removal, to form mask pattern;
Step S03, carries out etching to described grid layer, to form grid;
Step S04, forms a protective layer at the sidewall of described grid, and described grid is carried out to nitrogen treatment to form described protective layer;
Step S05, carries out etching to described Semiconductor substrate, to form shallow slot.
Below enumerate several embodiment of the formation method of described shallow slot, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by those of ordinary skills' routine techniques means are also within thought range of the present invention.
[the first embodiment]
In the present embodiment by described grid being carried out to nitrogen treatment to form described protective layer.
Below in conjunction with Fig. 2 and Fig. 3 a-Fig. 3 e, illustrate the formation method of the shallow slot of the present embodiment, wherein, the flow chart of the formation method of the shallow slot that Fig. 2 is one embodiment of the invention, the schematic diagram of the formation method of the shallow slot that Fig. 3 a-Fig. 3 e is one embodiment of the invention.
First, carry out step S01, Semiconductor substrate 210 is provided, in described Semiconductor substrate 210, there is the grid layer 220A and the mask layer 230A that stack gradually from bottom to top, as shown in Figure 3 a.Described mask layer 230A can be individual layer mask layer or multi-layer mask layer, in the present embodiment, nitride mask layer 231A and the oxide mask layer 232A of described multi-layer mask layer for stacking gradually from bottom to top, can guarantee that the grid forming in step S03 has good shape.Wherein, the material of described grid layer 220A does not limit, in the present embodiment, the material of described grid layer 220A is polysilicon, but the material of described grid layer 220A is not limited to polysilicon, if metal etc. is also within thought range of the present invention, described grid layer 220A can be doping grid layer or non-doping grid layer, and preferred, described grid layer 220A is phosphorus doping grid layer, can form N-type polysilicon, in described grid layer 220A, the doping content of phosphorus is 1E19/cm
3～1E20/cm
3, but the doping content of described grid layer 220A is not limited to this, as long as can realize the function of grid, also within thought range of the present invention.
Preferably, between described Semiconductor substrate 210 and described grid layer 220A, also comprise an etching stop layer 240, the material of described etching stop layer 240 should be selected to select higher material with described Semiconductor substrate 210 materials, can guarantee in step S03, during to described grid layer 220A etching, etching can stop on described etching stop layer 240, avoids the etching to described Semiconductor substrate 210.
Then, carry out step S02, adopt mask layer 230A described in conventional method selective removal, to form mask pattern 230, as shown in Figure 3 b.
Then, carry out step S03, adopt conventional method, using described mask pattern 230 as the mask of grid, described grid layer 220A is carried out to etching, to form grid 220, as shown in Figure 3 c.
Subsequently; carry out step S04; described grid 220 is carried out to nitrogen treatment; with sidewall 221 outer surfaces at described grid 220, form described protective layer 250; wherein; concrete nitrogenation treatment technology does not limit; as the plasma with nitrogen carries out nitrogen treatment; or carry out the techniques such as nitrogen treatment with the plasma of ammonia; as long as make the material nitrogenize of sidewall 221 outer surfaces of described grid 220; can form nitride, can protect the sidewall 221 of described grid 220 not to be damaged at step S05, also within thought range of the present invention.Due to nitride mask layer 231A and the oxide mask layer 232A for stacking gradually from bottom to top of described mask layer 230A in the present embodiment; so when described grid 220 is carried out to nitrogen treatment; described nitride mask layer 231A also can be nitrided simultaneously; so described protective layer 250 is also positioned at the outer surface of described nitride mask layer 231A, as shown in Figure 3 d.
Finally, carry out step S05, described Semiconductor substrate 210 is carried out to etching, to form shallow slot 211, when described Semiconductor substrate 210 is carried out to etching, described mask pattern 230 can continue the mask as described shallow slot 211, thereby saves processing step.When described Semiconductor substrate 210 is carried out to etching; because sidewall 221 outer surfaces of described grid 220 have described protective layer 250; described protective layer 250 can prevent sidewall 221 damages of described grid 220; thereby make described grid 220 there is smooth, smooth sidewall; thereby guarantee the electrical property of described grid 220, as shown in Figure 3 e.Form after described shallow slot 211, can carry out follow-up processing step, as described in fill isolated material in shallow slot 211 to form shallow-trench isolation.
[the second embodiment]
The second embodiment is on the basis of the first embodiment, and difference is, the step that forms a protective layer at the sidewall of described grid comprises:
In described grid 220, described mask pattern 230 and described Semiconductor substrate 210, prepare a sacrifice layer 250A, as shown in Fig. 4 a, because the present embodiment also comprises an etching stop layer 240, so, can adopt the method for chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald, on described grid 220, described mask pattern 230 and etching stop layer 240, prepare a sacrifice layer 250A, sacrifice layer 250A described in etching, and retain the described sacrifice layer 250A on the sidewall of described mask pattern 230, to form described protective layer 250, as shown in Figure 4 b, when described sacrifice layer 250A is carried out to etching, as long as expose described etching stop layer 240, the described sacrifice layer 250A of described mask pattern 230 sidewalls can also be retained simultaneously, described sacrifice layer 250A on described mask pattern 230 can all get rid of, also can remove part, and retain sacrifice layer 250A described in very thin one deck, can follow-up step not impacted, therefore do not limit, in Fig. 4 b, do not specifically illustrate yet.Preferably; the material of described protective layer 250 can be one or more the combination in silicon dioxide, silicon nitride, amorphous carbon, organic substance or metal; can avoid preferably etching away in step S05; but the material of described protective layer 250 is not limited to as one or more the combination in silicon dioxide, silicon nitride, amorphous carbon, organic substance or metal; so long as the material higher with the selection of the material of described Semiconductor substrate 210; also can realize and avoid etching away in step S05, also within thought range of the present invention.
Described protective layer 250 in the present embodiment can also prevent sidewall 221 damages of described grid 220; thereby make described grid 220 there is smooth, smooth sidewall; thereby guarantee the electrical property of described grid 220, as shown in Fig. 4 c, also within thought range of the present invention.
In sum; the invention provides a kind of formation method of shallow slot; the formation method of this shallow slot is first carried out etching to grid layer; to form grid, then the sidewall at described grid forms a protective layer, finally described Semiconductor substrate is carried out to etching; to form shallow slot; because described protective layer is when carrying out etching to described Semiconductor substrate, can protect described grid not to be damaged, make described grid there is smooth, smooth sidewall.。Compared with prior art, the formation method of shallow slot provided by the invention has the following advantages:
The formation method of shallow slot provided by the invention; first carry out the etching of grid; then the sidewall at described grid forms after a protective layer; again described Semiconductor substrate is carried out to etching, to form shallow slot, compared with prior art; when described Semiconductor substrate is carried out to etching; described protective layer can protect described grid not to be damaged, and makes described grid have smooth, smooth sidewall, thereby guarantees the electrical property of described grid.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. a formation method for shallow slot, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there is the grid layer and the mask layer that stack gradually from bottom to top;
Mask layer described in selective removal, to form mask pattern;
Described grid layer is carried out to etching, to form grid;
Sidewall at described grid forms a protective layer; And
Described Semiconductor substrate is carried out to etching, to form shallow slot.
2. the formation method of shallow slot as claimed in claim 1, is characterized in that, the step that forms a protective layer at the sidewall of described grid comprises:
Described grid is carried out to nitrogen treatment to form described protective layer.
3. the formation method of the formation method shallow slot of grid as claimed in claim 1, is characterized in that, the step that forms a protective layer at the sidewall of described grid comprises:
In described grid, described mask pattern and described Semiconductor substrate, prepare a sacrifice layer;
Sacrifice layer described in etching, and retain the described sacrifice layer on the sidewall of described grid, to form described protective layer.
4. the formation method of shallow slot as claimed in claim 3, is characterized in that, adopts the method for chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald, in described grid, described mask pattern and described Semiconductor substrate, prepares a sacrifice layer.
5. the formation method of shallow slot as claimed in claim 3, is characterized in that, the material of described protective layer is one or more the combination in silicon dioxide, silicon nitride, amorphous carbon, organic substance or metal.
6. the formation method of the shallow slot as described in any one in claim 1 to 5, is characterized in that, between described Semiconductor substrate and described grid layer, also comprises an etching stop layer.
7. the formation method of shallow slot as claimed in claim 1, is characterized in that, described mask layer is individual layer mask layer or multi-layer mask layer.
8. the formation method of shallow slot as claimed in claim 7, is characterized in that, nitride mask layer and the oxide mask layer of described multi-layer mask layer for stacking gradually from bottom to top.
9. the formation method of shallow slot as claimed in claim 1, is characterized in that, described grid layer is phosphorus doping grid layer.
10. the formation method of shallow slot as claimed in claim 9, is characterized in that, in described grid layer, the doping content of phosphorus is 1E19/cm
3～1E20/cm
3.
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| CN201310066219.7A CN104022063B (en) | 2013-03-01 | 2013-03-01 | The forming method of shallow slot |
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| CN201310066219.7A CN104022063B (en) | 2013-03-01 | 2013-03-01 | The forming method of shallow slot |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105206525A (en) * | 2015-09-28 | 2015-12-30 | 上海华力微电子有限公司 | Method for overcoming defects of grid vertex corner in germanium-silicon growing process |
| CN108831919A (en) * | 2018-05-04 | 2018-11-16 | 上海华力集成电路制造有限公司 | Flat-grid MOSFET |
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| CN101807600A (en) * | 2009-02-13 | 2010-08-18 | 株式会社半导体能源研究所 | Transistor, have this transistorized semiconductor device and their manufacture method |
| US20120214281A1 (en) * | 2011-02-23 | 2012-08-23 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| US20120256264A1 (en) * | 2011-04-05 | 2012-10-11 | Fujitsu Semiconductor Limited | Semiconductor device and fabrication method |
| CN102810513A (en) * | 2011-05-31 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming transistor |
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| CN105206525A (en) * | 2015-09-28 | 2015-12-30 | 上海华力微电子有限公司 | Method for overcoming defects of grid vertex corner in germanium-silicon growing process |
| CN108831919A (en) * | 2018-05-04 | 2018-11-16 | 上海华力集成电路制造有限公司 | Flat-grid MOSFET |
| CN108831919B (en) * | 2018-05-04 | 2021-10-15 | 上海华力集成电路制造有限公司 | Planar gate MOSFET |
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