CN103928313A - Manufacturing method for small-sized graph - Google Patents
Manufacturing method for small-sized graph Download PDFInfo
- Publication number
- CN103928313A CN103928313A CN201410161247.1A CN201410161247A CN103928313A CN 103928313 A CN103928313 A CN 103928313A CN 201410161247 A CN201410161247 A CN 201410161247A CN 103928313 A CN103928313 A CN 103928313A
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- small size
- layer
- etching
- silicon nitride
- manufacture method
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 70
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 35
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 17
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 238000001020 plasma etching Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- 229920005591 polysilicon Polymers 0.000 claims description 37
- 239000007789 gas Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 8
- 239000003595 mist Substances 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000000427 thin-film deposition Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method for a small-sized graph. The manufacturing method comprises the steps that at first, the thin-film deposition process and the etching process are adopted for forming a large-sized graph and a first small-sized graph, and secondly, on the basis of the first small-sized graph, the thin-film deposition process and the etching process are adopted again for forming a second small-sized graph. The process of forming the second small-sized graph comprises the steps that a silicon oxide layer is deposited on the surface of a wafer, the plasma etching process is adopted for etching and removing the portion, on the top and the bottom of the side silicon nitride wall, of the silicon oxide layer, a side silicon oxide wall is formed on the side wall of the side silicon nitride wall, and the wet etching process is adopted for removing the side silicon nitride wall, so that the second small-sized graph is formed. As the two-time self-alignment process is adopted, the graph with the size smaller than that of a traditional small-sized graph can be manufactured, the device integration level is increased, the process window is enlarged, and the process difficulty is lowered.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of manufacture method of small size figure.
Background technology
Along with process constantly dwindles, particularly 20nm and following, because grid width further reduces, the ability to mask aligner and the requirement of photoetching process are more and more higher.According to Moore's Law, in order further to reduce device critical size, improve its integrated level, industry occurs various for making the method for small size figure.
Under normal circumstances, refer to Fig. 1, Fig. 1 is the schematic flow sheet of the manufacture method of traditional small size figure, and it comprises the following steps:
Step L01: deposit hard dielectric layer, polysilicon layer, bottom anti-reflection layer and photoresist at crystal column surface successively;
Step L02: adopt photoetching and plasma etch process, etching photoresist, bottom anti-reflection layer and polysilicon layer successively forms large scale figure in polysilicon layer;
Step L03: at polysilicon layer surface and hard dielectric layer surface deposition one deck silicon nitride layer;
Step L04: using plasma etching technics, etch away the silicon nitride layer of polysilicon layer top and bottom, form silicon nitride side wall;
Step L05: remove polysilicon layer, thereby form small size figure.
Above-mentioned is double-deck figure (SADP) technique of current most popular autoregistration.According to initial 100 nanometer spacing (pitch), can form 25 nano-scale linewidth figures in 50 nanometer pitch the insides through a SADP.
But, in actual etching technics, in 20nm and following technology thereof, there is lithographic capabilities deficiency and the less problem of process window, therefore, be badly in need of a kind of method that improves lithographic process window, reduction critical size of research, thereby increase substantially the integrated level of device.
Summary of the invention
In order to overcome the problems referred to above, the present invention aims to provide a kind of manufacture method of small size figure, thereby realizes the live width size below 10nm.
The manufacture method that the invention provides a kind of small size figure, it comprises:
Step S01: deposit hard dielectric layer, polysilicon layer, bottom anti-reflection layer and photoresist at crystal column surface successively;
Step S02: adopt photoetching and plasma etch process, photoresist, described bottom anti-reflection layer and described polysilicon layer described in etching form large scale figure in described polysilicon layer successively;
Step S03: at described polysilicon layer surface and described hard dielectric layer surface deposition one deck silicon nitride layer;
Step S04: using plasma etching technics, etch away the described silicon nitride layer of described polysilicon layer top and bottom, form silicon nitride side wall;
Step S05: remove described polysilicon layer, thereby form the first small size figure;
Step S06: at described crystal column surface deposition one deck silicon oxide layer;
Step S07: using plasma etching technics, etching is got rid of the described silicon oxide layer of described silicon nitride side wall top and bottom, forms monox lateral wall at the sidewall of described silicon nitride side wall;
Step S08: adopt wet-etching technology, remove described silicon nitride side wall, thereby form the second small size figure.
Preferably, in described step S06, adopt Atomic layer deposition method to deposit described silicon oxide layer.
Preferably, the thickness of described silicon oxide layer is less than 10nm.
Preferably, in described step S07, the reaction pressure adopting is 10-150mTorr, and the reaction temperature adopting is 30-80 DEG C, and the etch period adopting is 10-30 second, and the top electrode radio-frequency power adopting is 100-400 watt.
Preferably, the etching gas adopting is the mist of fluoro-gas and oxygen.
Preferably, described etching gas comprises CF
4and/or C
4f
8, and O
2.
Preferably, in described fluoro-gas, described C
4f
8flow be 30-100sccm, described CF
4flow be 20-40sccm, described O
2flow be 10-15sccm.
Preferably, in described step S08, the wet etching liquid adopting is hot phosphoric acid solution.
Preferably, in described step S08, in described hot phosphoric acid solution, H
3pO
4with H
2the mass ratio of O is 70%-90%, and the temperature range adopting is 150-170 DEG C.
The manufacture method of a kind of small size figure of the present invention, realizes small size graphic structure by adopting twice self-registered technology to form double-deck figure, comprising: comprehensively adopt thin film deposition and dry etching technology, first form large scale figure; Then, on the basis of large scale figure, adopt thin film deposition and dry etching technology, form the first small size figure; Finally, deposition is less than the silicon oxide film of 10nm, form monox lateral wall through etching again, then adopt wet etching technique, remove silicon nitride side wall, thereby form the second small size figure, that is to say the small size figure that will make in the present invention, the size of the small size figure of made is less than 10nm, thereby has increased process window, the live width that has effectively reduced the small size figure in traditional handicraft, has improved device integrated level.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the manufacture method of traditional small size figure
Fig. 2 is the schematic flow sheet of the manufacture method of the small size figure of a preferred embodiment of the present invention
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Below with reference to specific embodiments and the drawings 2, the manufacture method of small size figure of the present invention is described in further detail.Fig. 2 is the schematic flow sheet of the manufacture method of the small size figure of a preferred embodiment of the present invention.
Refer to Fig. 2, the manufacture method of the small size figure of the present embodiment of the present invention, comprises the following steps:
Step S01: deposit hard dielectric layer, polysilicon layer, bottom anti-reflection layer and photoresist at crystal column surface successively;
Here, the effect of hard dielectric layer is in order to protect crystal column surface injury-free in follow-up dry etching, and this is that the etching selection of polysilicon and wafer substrate is lower, such as monocrystalline substrate because in follow-up dry etching.
Here, in the present embodiment, can be, but not limited to adopt chemical vapour deposition technique to deposit hard dielectric layer and polysilicon layer, the deposition of bottom anti-reflection layer and photoresist can be, but not limited to adopt physical method, such as techniques such as spin coatings, the present invention does not impose any restrictions this.In the present embodiment, the material of hard dielectric layer can be, but not limited to the material into SiOC.
Step S02: adopt photoetching and plasma etch process, etching photoresist, bottom anti-reflection layer and polysilicon layer successively forms large scale figure in polysilicon layer;
Concrete, in the present embodiment, this step can comprise following process:
The first process: adopt photoetching process, photoresist is exposed, thus this photoresist of patterning;
The second process: taking the photoresist of patterning as mask, using plasma dry etch process, etching bottom anti-reflection layer; Here can adopt Cl,
2, HBr, O
2, CF
4deng etching gas, bottom anti-reflection layer is carried out to etching, this etching process stops on polysilicon layer;
The 3rd process: using plasma dry etch process etch polysilicon layer; Here the etching gas adopting, can be, but not limited to as Cl
2, HBr, O
2mist, this etching process stops on hard dielectric layer; It should be noted that, in the process of etch polysilicon layer, photoresist or bottom anti-reflection layer are also subject to etching simultaneously, and after the process of etch polysilicon layer stops, photoresist or bottom anti-reflection layer may be etched away; If photoresist or bottom anti-reflection layer are not all etched away, tackle it and remove; The gas that removal photoresist and bottom anti-reflection layer adopt is for containing O
2etching gas.
Step S03: at polysilicon layer surface and hard dielectric layer surface deposition one deck silicon nitride layer;
Concrete, in the present embodiment, can adopt Atomic layer deposition method to form silicon nitride layer, the thickness of silicon nitride layer can be less than 20nm.The concrete technology parameter adopting in deposition process can require to set according to actual process, and the present invention is not restricted this.
Step S04: using plasma etching technics, etch away the silicon nitride layer of polysilicon layer top and bottom, form silicon nitride side wall;
Concrete, in the present embodiment, can be, but not limited to adopt comprise CF
4, CHF
3and CH
2f
2mist etch away the silicon nitride layer of polysilicon layer top and bottom as etching gas, thereby form silicon nitride side wall at the sidewall of polysilicon layer.The concrete technology parameter adopting in this etching process can require to set according to actual process, and the present invention is not restricted this.
Step S05: remove polysilicon layer, thereby form the first small size figure;
Concrete, in the present embodiment, can adopt and contain Cl
2, HBr, O
2mist get rid of polysilicon layer as etching gas etching; Herein, selected etching gas is to polysilicon layer and silicon nitride, and should be higher to the selection ratio of polysilicon layer and hard dielectric layer, thereby in etch polysilicon layer, silicon nitride side wall is not etched away.The concrete technology parameter adopting in this etching process can require to set according to actual process, and the present invention is not restricted this.
It should be noted that, the size of the first small size figure is here greater than the size of the second small size figure, for example, the thickness of silicon nitride layer is 20nm, the first small size figure is of a size of 20nm, and the size of the second small size figure is less than 20nm, for example, can be 10nm.
Step S06: at crystal column surface deposition one deck silicon oxide layer;
Concrete, in the present embodiment, in order to realize less live width and dimension of picture, can adopt Atomic layer deposition method to form silicon oxide layer, in the present embodiment, the thickness of silicon oxide layer is less than 10nm.The concrete technology parameter adopting in deposition process can require to set according to actual process, and the present invention is not restricted this.
Step S07: using plasma etching technics, the silicon oxide layer of etch silicon nitride side wall top and bottom, forms monox lateral wall at the sidewall of silicon nitride side wall;
Concrete, in the present embodiment, the etching gas adopting is the mist of fluoro-gas and oxygen, can be for comprising CF
4and/or C
4f
8, and O
2mist, wherein, C
4f
8flow be 30-100sccm, CF
4flow be 20-40sccm, O
2flow be 10-15sccm, but this is not used in and limits the scope of the invention.
In the present embodiment, the etching technics parameter adopting can be, but not limited to following scope: the reaction pressure adopting is 10-150mTorr, the reaction temperature adopting is 30-80 DEG C, and the etch period adopting is 10-30 second, and the top electrode radio-frequency power adopting is 100-400 watt.
Step S08: adopt wet-etching technology, remove silicon nitride side wall, thereby form the second small size figure.
Here, in the present invention, should adopt silicon nitride and polysilicon and the high liquid of etching selection ratio of silicon nitride and hard dielectric layer is carried out to wet etching, like this, in removing silicon nitride side wall, protecting monox lateral wall not to be etched away.Concrete, in the present embodiment, the wet etching liquid adopting is hot phosphoric acid solution, preferably, in hot phosphoric acid solution, H
3pO
4with H
2the mass ratio 70%-90% of O, the temperature range adopting is 150-170 DEG C.
Like this, the second small size figure forming is of a size of the thickness of silicon oxide film, and this size is less than 10nm, thereby the size of the small size figure of preparing with respect to conventional method is dwindled greatly; And the method, in preparation process, has avoided directly carrying out the etching of small size figure, has expanded process window.
In sum, the manufacture method of small size figure of the present invention, by adopting self-registered technology twice, first form large scale figure, then form the first small size figure, on the basis of the first small size figure, further adopt thin film deposition and etching technics, form than the second less small size figure of size of the first small size figure, thereby realized than the less figure of traditional small size dimension of picture, dwindle live width and critical size structure, improved the integrated level of device; And expanded process window, reduce technology difficulty.
Although the present invention discloses as above with preferred embodiment; right described embodiment only gives an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (9)
1. a manufacture method for small size figure, is characterized in that, comprising:
Step S01: deposit hard dielectric layer, polysilicon layer, bottom anti-reflection layer and photoresist at crystal column surface successively;
Step S02: adopt photoetching and plasma etch process, photoresist, described bottom anti-reflection layer and described polysilicon layer described in etching form large scale figure in described polysilicon layer successively;
Step S03: at described polysilicon layer surface and described hard dielectric layer surface deposition one deck silicon nitride layer;
Step S04: using plasma etching technics, etch away the described silicon nitride layer of described polysilicon layer top and bottom, form silicon nitride side wall;
Step S05: remove described polysilicon layer, thereby form the first small size figure;
Step S06: at described crystal column surface deposition one deck silicon oxide layer;
Step S07: using plasma etching technics, etching is got rid of the described silicon oxide layer of described silicon nitride side wall top and bottom, forms monox lateral wall at the sidewall of described silicon nitride side wall;
Step S08: adopt wet-etching technology, remove described silicon nitride side wall, thereby form the second small size figure.
2. the manufacture method of small size figure according to claim 1, is characterized in that, in described step S06, adopts Atomic layer deposition method to deposit described silicon oxide layer.
3. the manufacture method of small size figure according to claim 1, is characterized in that, the thickness of described silicon oxide layer is less than 10nm.
4. the manufacture method of small size figure according to claim 1, it is characterized in that, in described step S07, the reaction pressure adopting is 10-150mTorr, the reaction temperature adopting is 30-80 DEG C, the etch period adopting is 10-30 second, and the top electrode radio-frequency power adopting is 100-400 watt.
5. the manufacture method of small size figure according to claim 1, is characterized in that, the etching gas adopting is the mist of fluoro-gas and oxygen.
6. the manufacture method of small size figure according to claim 5, is characterized in that, described etching gas comprises CF
4and/or C
4f
8, and O
2.
7. the manufacture method of small size figure according to claim 6, is characterized in that, in described fluoro-gas, and described C
4f
8flow be 30-100sccm, described CF
4flow be 20-40sccm, described O
2flow be 10-15sccm.
8. the manufacture method of small size figure according to claim 1, is characterized in that, in described step S08, the wet etching liquid adopting is hot phosphoric acid solution.
9. the manufacture method of small size figure according to claim 8, is characterized in that, in described step S08, and in described hot phosphoric acid solution, H
3pO
4with H
2the mass ratio of O is 70%-90%, and the temperature range adopting is 150-170 DEG C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410161247.1A CN103928313B (en) | 2014-04-22 | 2014-04-22 | A kind of preparation method of small size figure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410161247.1A CN103928313B (en) | 2014-04-22 | 2014-04-22 | A kind of preparation method of small size figure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103928313A true CN103928313A (en) | 2014-07-16 |
| CN103928313B CN103928313B (en) | 2017-12-15 |
Family
ID=51146495
Family Applications (1)
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201100A (en) * | 2014-09-23 | 2014-12-10 | 上海华力微电子有限公司 | Small-sized graph making method |
| CN104347362A (en) * | 2014-09-23 | 2015-02-11 | 上海华力微电子有限公司 | Manufacturing method of small-dimension pattern |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070148968A1 (en) * | 2005-12-26 | 2007-06-28 | Samsung Electronics Co., Ltd. | Method of forming self-aligned double pattern |
| US20080020576A1 (en) * | 2006-07-24 | 2008-01-24 | Duck-Hwan Kim | Method of forming polysilicon pattern |
| US20090104786A1 (en) * | 2007-10-17 | 2009-04-23 | Kabushiki Kaisha Toshiba | Method of fabricating semiconductor device |
| CN102239541A (en) * | 2008-12-04 | 2011-11-09 | 美光科技公司 | Methods of fabricating substrates |
-
2014
- 2014-04-22 CN CN201410161247.1A patent/CN103928313B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070148968A1 (en) * | 2005-12-26 | 2007-06-28 | Samsung Electronics Co., Ltd. | Method of forming self-aligned double pattern |
| US20080020576A1 (en) * | 2006-07-24 | 2008-01-24 | Duck-Hwan Kim | Method of forming polysilicon pattern |
| US20090104786A1 (en) * | 2007-10-17 | 2009-04-23 | Kabushiki Kaisha Toshiba | Method of fabricating semiconductor device |
| CN102239541A (en) * | 2008-12-04 | 2011-11-09 | 美光科技公司 | Methods of fabricating substrates |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201100A (en) * | 2014-09-23 | 2014-12-10 | 上海华力微电子有限公司 | Small-sized graph making method |
| CN104347362A (en) * | 2014-09-23 | 2015-02-11 | 上海华力微电子有限公司 | Manufacturing method of small-dimension pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103928313B (en) | 2017-12-15 |
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