CN1921087A - Producing method for strain source leakage CMOS using multilayer film as hard mask and anti-reflecting layer - Google Patents
Producing method for strain source leakage CMOS using multilayer film as hard mask and anti-reflecting layer Download PDFInfo
- Publication number
- CN1921087A CN1921087A CN 200510029095 CN200510029095A CN1921087A CN 1921087 A CN1921087 A CN 1921087A CN 200510029095 CN200510029095 CN 200510029095 CN 200510029095 A CN200510029095 A CN 200510029095A CN 1921087 A CN1921087 A CN 1921087A
- Authority
- CN
- China
- Prior art keywords
- multilayer film
- hard mask
- layer
- silicon
- reflecting layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a multilayer mask and a relative strain source-drain CMOS whose rigid mask and anti-reflective layer are said multilayer masks. Wherein, it comprises: depositing multilayer on the polycrystalline deposit layer; using photo-etching light when the reflectance of liner is low enough; and it can be used as rigid mask and the mask of source-drain silicon concave etching and extending silicon germanium or/and silicon carbon, to protect the polycrystalline grid from silicon germanium or silicon carbon; therefore, after concave etching and extending growing, the multilayer can be removed easily, without significant effect on the separated layer.
Description
Technical field
The present invention relates to have CMOS (Complementary Metal Oxide Semiconductor) (the Complementary Metal Oxide Semiconductor of strain source-drain, CMOS) manufacture method, particularly relate to multilayer film as anti-reflecting layer and the hard mask of polysilicon gate, the manufacture method of removed strain source leakage CMOS after forming strain source-drain.
Background technology
Comprise the formation of gate pattern in the ic manufacturing process, it adopts polysilicon as gate conductive structure usually.In its processing procedure, polysilicon layer is deposited on the substrate, and it is that monocrystalline silicon forms through different process processes such as ion injection, gate oxides.The polysilicon of deposit forms gate pattern through photoetching and etching then.For forming gate pattern, as hard mask, plasma chemical vapor deposition grown silicon oxide, silicon oxynitride or nitride and silicon oxynitride etc. are used for the photoresist design transfer to poly-silicon pattern.This silicon oxynitride also can be used as the anti-reflecting layer of photoetching simultaneously.Because the photoresist that the lip-deep hydrogen of silicon oxynitride (SiON) film waves on key and its top reacts, this reaction causes the photoresist pattern development incomplete.Usually, go up oxidation film on silicon oxynitride (SiON) film top, with contacting of isolated silicon oxynitride and photoresist with plasma-reinforced chemical vapor deposition one deck 100～300A.For the application of selective epitaxial growth strained silicon, need carry out silicon dent by reactive ion beam etching (RIBE) at active region and etch into below the surface, the hard mask of polysilicon also needs as silicon dent etching and epitaxially grown hard mask.Hard mask needs to remove after epitaxial growth, and at this moment the inter polysilicon interlayer forms.Wet method is removed silicon oxynitride hard mask need use hot phosphoric acid, and hot phosphoric acid also can corrode nitride spacer layer when removing silicon oxynitride hard mask.Carry out processing procedure control to remove silicon oxynitride hard mask and to keep wall not to be etched very difficult.
Summary of the invention
The manufacture method that the purpose of this invention is to provide strain source leakage CMOS, multi-layer film structure particularly is provided, as the anti-reflecting layer of photoresist photoetching in the strain source leakage CMOS manufacturing process and as being the hard mask of hard mask of polysilicon and silicon dent etching, grow at this silicon dent etching place SiGe or silicon carbon layer are used for the formation of strained silicon.
One aspect of the present invention, multilayer film comprises the steps: as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer
A. on silicon substrate, form P, N well, shallow isolating trough, on silicon substrate, form gate oxide level, polysilicon layer, multilayer film, photoresist layer then successively, this multilayer film comprises Si oxide and silicon nitrogen oxide, the anti-reflecting layer of this multilayer film during as photoetching and the hard mask during the silicon dent etching.
B. photoetching, etching form the polysilicon gate conductive structure;
C. form the polysilicon gate wall;
D. be the polysilicon gate of mask protection PMOS with multilayer film and wall,, the etching that caves in leaked in the PMOS source with photoresist protection nmos area territory;
E. remove photoresist;
F. being the polysilicon of mask protection PMOS with multilayer film and wall, is mask protection nmos area territory with multilayer film and wall, and depression etch areas epitaxial growth SiGe is leaked in the PMOS source;
G. remove multilayer film as hard mask;
H. carry out other successive process.
Another aspect of the present invention, multilayer film comprises the steps: as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer
A. form P, N well, form gate oxide level, polysilicon layer, multilayer film, photoresist layer on the silicon substrate of shallow isolating trough successively, this multilayer film comprises Si oxide and silicon nitrogen oxide, the anti-reflecting layer of this multilayer film during as photoetching and the hard mask during the silicon dent etching.
B. photoetching, etching form the polysilicon gate conductive structure;
C. form the polysilicon gate wall;
D. be the polysilicon gate of mask protection NMOS with multilayer film and wall,, the etching that caves in leaked in the NMOS source with photoresist protection PMOS zone;
E. remove photoresist;
F. being the polysilicon gate of mask protection NMOS with multilayer film and wall, is mask protection PMOS zone with multilayer film and wall, and depression etch areas epitaxial growth silicon-carbon is leaked in the NMOS source;
G. remove multilayer film as hard mask;
H. carry out other successive process;
According to the present invention, multilayer film can also at first leak the epitaxial growth of formation SiGe as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer in the PMOS source, leaks in the NMOS source then to form the silicon-carbon epitaxial growth.
According to the present invention, multilayer film can also at first leak the epitaxial growth of formation silicon-carbon as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer in the NMOS source, leaks in the PMOS source then to form the SiGe epitaxial growth.
The multilayer film that polysilicon top layer of the present invention forms comprises trilamellar membrane, ground floor silicon oxide layer, second layer silicon oxynitride layer and the 3rd layer of silicon oxide layer.These films can be by chemical vapor deposition (Chemical Vapor Deposition, CVD) or other deposition technology, as plasma-reinforced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) and spin coating methods such as (Spin-on) and forming.The thickness of the ground floor silicon oxide layer of employing PECVD deposit is such as being 50～400A.Silicon oxynitride layer can be controlled in processing procedure, as adopting PECVD, so that the thickness of the refractive index n of this silicon oxynitride film, dielectric constant k and film, is used in the reflection of light amount minimum of photoengraving pattern.The thickness of silicon oxynitride is 100～400A.The 3rd layer of silicon oxide film also can adopt PECVD to form, and the thickness of this oxide skin(coating) is 50～250A.Wherein the 3rd layer of silicon oxide film can prevent the reaction between silicon oxynitride and the photoresist, because this reaction can cause forming the residue that can not remove in lithography development process.
Advantage of the present invention is owing to adopt trilamellar membrane to be used for the formation of poly-silicon pattern, by technology controlling and process, to make the multilayer film of formation have suitable refractive index and dielectric constant, thereby have the lower reflectivity that satisfies the photoetching requirement.
Another advantage of the present invention is, because wet etching with the hydrofluoric acid base, the wall that Si oxide is contained silicon nitride has high selectivity, therefore keep as silicon dent etching and epitaxial growth SiGe or silicon-carbon the time as first tunic in the trilamellar membrane of hard mask, silicon oxide layer is removed easily, and can not produce obvious erosion to wall.
Description of drawings
Fig. 1 is the structural representation of the multilayer film of one embodiment of the present of invention and polysilicon, photoresist layer.
Fig. 2 is the analog result schematic diagram of refractive index, dielectric constant and the reflectivity of multilayer film of the present invention, and wherein abscissa is the dielectric constant k of nitrogen oxide, and ordinate is the refractive index n of nitrogen oxide, the reflectivity that the regions of different colours representative is different.
Fig. 3 be form on the silicon substrate after forming P, N well and shallow isolating trough gate oxide, polysilicon, multilayer film, and photoresist after schematic cross-section.
Fig. 4 is the schematic cross-section after photoetching, etching form the photoresist pattern.
Fig. 5 is the schematic cross-section after design transfer arrives the hard mask of multilayer film.
Fig. 6 is polysilicon and oxide skin(coating) etching, with the schematic cross-section of design transfer behind polysilicon and the oxide skin(coating).
Fig. 7 is the schematic cross-section of multilayer film after by an eating away part in polysilicon and the oxide etching process.
Fig. 8 be after forming the gate spacer layer multilayer film further by the schematic cross-section after the eating away part.
Fig. 9 is one embodiment of the present of invention, the schematic cross-section behind the photoresist pattern in formation protection nmos area territory.
Figure 10 is one embodiment of the present of invention, serves as the protection polysilicon gate with the hard mask of multilayer film of polysilicon and wall, the source of PMOS is leaked the schematic cross-section that carries out after the silicon dent etching.
Figure 11 is one embodiment of the present of invention, the schematic cross-section after silicon dent etch areas epitaxial growth SiGe is leaked in the PMOS source.
Figure 12 is one embodiment of the present of invention, the schematic cross-section behind the hard mask of removal multilayer film.
Description of reference numerals
02 polysilicon gate oxide skin(coating) illuvium
03 polysilicon illuvium
The first tunic illuvium of 04 multilayer film
The second tunic illuvium of 05 multilayer film
The trilamellar membrane illuvium of 06 multilayer film
07 photoresist coating
10 silicon substrates
11N well 12PMOS gate oxide
The 13PMOS polysilicon gate
The hard mask of ground floor multilayer film on the 14PMOS polysilicon gate
The hard mask of second layer multilayer film on the 15PMOS polysilicon gate
The hard mask of the 3rd layer multi-layer film on the 16PMOS polysilicon gate
Photoresist protective layer on the 17PMOS polysilicon gate
18PMOS polysilicon gate wall
Depression etching on leak in the 19PMOS source
Epitaxial growth germanium-silicon layer on leak in the 191PMOS source
20 shallow isolating trough
The 21P well
The 22NOMS gate oxide
The 23NMOS polysilicon gate
The hard mask of ground floor multilayer film on the 24NMOS polysilicon gate
The hard mask of second layer multilayer film on the 25NMOS polysilicon gate
The hard mask of the 3rd layer multi-layer film on the 26NMOS polysilicon gate
Photoresist protective layer on the 27NMOS polysilicon gate
28NMOS polysilicon gate wall
The photoresist in 30 protection nmos area territories
Embodiment
Below in conjunction with drawings and Examples the manufacture method of multilayer film as the strain source leakage CMOS of hard mask and anti-reflecting layer is described in more detail.
Embodiment 1
According to one embodiment of present invention, multilayer film comprises the steps: as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer
A) on P type silicon substrate 10, form N well 11, P well 21, shallow isolating trough 20; On silicon substrate 10, at first adopt the plasma-reinforced chemical vapor deposition method to form polysilicon oxide layer 02, polysilicon layer 03 then, the ground floor that forms multilayer film is that silicon oxide layer 04, the second layer are that the oxynitride layer 05, the 3rd layer of silicon is silicon oxide layer 06, form photoresist layer 07 then, as shown in Figure 3.Wherein the thickness of ground floor Si oxide is 150A, the thickness of second layer silicon oxynitride is 200A, the thickness of the 3rd layer of Si oxide is 250A, Fig. 1 shows that this multilayer film can have the analog result of low reflectivity to the scanner that adopts the 193nm light source, and the multilayer film of Xing Chenging has refractive index n=1.7+/-0.1 and dielectric constant k=0.7+/-0.2 like this.
Fig. 2 be in refractive index, dielectric constant and the photoresist of trilamellar membrane reflectivity concern simulation drawing, as can see from Figure 2, under the trilamellar membrane of Fig. 1, the reflectivity in the photoresist is 0.8%, meets very much the requirement of photoetching.When so just having avoided owing to photoetching, exposure light reflects to make in photoresist layer and forms the post ripple in the photoresist pattern, loses the control of critical size.Wherein the 3rd layer of silicon oxide film on the second layer silicon oxynitride top can completely cut off silicon oxynitride and photoresist, prevent to produce reaction between silicon oxynitride and the photoresist, avoided the reaction of silicon oxynitride and photoresist to make photoresist developing not exclusively form the residue that to remove.
B) carry out photoetching, etching and form the photoresist pattern 17,27 that requires, as shown in Figure 4, etching adopts common process, as reactive ion beam etching (RIBE) (reactive ion etch, RIE).
Further adopt the reactive ion beam etching (RIBE) multilayer film, the photoresist design transfer to multilayer film, is removed photoresist 17,27, on PMOS, form the pattern of trilamellar membrane 14,15,16, on NMOS, form trilamellar membrane pattern 24,25,26, as shown in Figure 5.Reactive ion beam etching (RIBE) adopts as carbon tetrafluoride (CF4) or three fluorocarbonss (CF3).
Again polysilicon layer 03 and oxide skin(coating) 02 are carried out reactive ion beam etching (RIBE), design transfer to polysilicon, is formed the polysilicon gate conductive structure, polysilicon gate 13,23, grid oxic horizon 12,22, as shown in Figure 6.Etch chemistries is main etching agent as adopting hydrogen bromide (HBr) or chlorine (Cl2).
Because multilayer film is impaired in above reactive ion beam etching (RIBE) several times, trilamellar membrane is by partial etching, and wherein the 3rd layer of silicon oxide layer 16 lost, and therefore, through the processing procedure of front, it is two- layer 14,24 and 15,25 that multilayer film stays, as shown in Figure 7.
C) form the nitride spacer layer 18,28 of polysilicon gate then, as shown in Figure 8.Be that (the process ion beam eat-backs with wet etching and forms for Low Press Chemical Vapor Deposition, LPCVD) silicon nitride by low-pressure chemical vapor phase deposition.
D) in the etch back process of wall, two membranes also can be lost a part, therefore only stays ground floor silicon oxide film 14 and 24.
At first form the photoresist pattern 30 in protection nmos area territory in the nmos area territory; ground floor silicon oxide layer 14 and wall 18 with multilayer film is mask protection PMOS zone polysilicon gate then; with the reactive ion beam etching (RIBE) method etching that caves in is leaked in the PMOS source; form depression etch areas 19, as shown in Figure 9.
E) remove photoresist, as shown in figure 10.
F) with reserved first layer film 14 and wall 18 be the polysilicon gate 13 of the hard mask protection of autoregistration PMOS; with reserved first layer film 24 and wall 28 is the polysilicon gate 23 of the hard mask protection of autoregistration NMOS; silicon dent etch areas 19 epitaxial growth SiGes at PMOS; form epitaxial growth SiGe zone 191, as shown in figure 11.
G) adopt wet etching to remove the oxide skin(coating) 14 and 24 of the hard mask of conduct, PMOS epitaxial growing strain source is leaked and has just been formed like this.This material is SiGex (the x scope is 0.1 to 0.3).Remove multilayer film 14 and 24, as shown in figure 12 as hard mask.Owing to adopt hydrofluoric acid base wet processing, this technology is Si oxide for the ground floor 14 and 24 of the multilayer film that stays, have higher selectivity than silicon nitride spacers 18 and 28, therefore get rid of easily, and can not produce obvious erosion wall 18 and 28 as 14 and 24 of hard mask.
H) carry out other successive process, comprise ion implantation doping, form metal silicide, metal interconnected etc.
Embodiment 2
Multilayer film is as the manufacture method of the CMOS with strain source-drain NMOS of hard mask and anti-reflecting layer.
Wherein a～the c in the making step is identical with embodiment 1.Other steps are as follows:
D) in the etch back process of wall, two membranes also can be lost a part, therefore only stays ground floor Si oxide 14 and 24.
At first form the photoresist pattern in protection PMOS zone in the PMOS zone; ground floor silicon oxide layer 24 and wall 28 with multilayer film is mask protection nmos area territory polysilicon gate then; with the reactive ion beam etching (RIBE) method etching that caves in is leaked in the NMOS source, form the depression etch areas.
E) remove photoresist.
F) with multilayer film and wall polysilicon gate, silicon dent zone epitaxial growth silicon-carbon is leaked in the source of NMOS as hard mask protection NMOS and PMOS.
G and h step are with embodiment 1.
Embodiment 3
Multilayer film is as the manufacture method of the CMOS with strain source-drain PMOS and strain source-drain NMOS of hard mask and anti-reflecting layer.
Wherein a～the c in the making step is identical with embodiment 1.Other steps are as follows:
D～f) is in the etch back process of wall, and two membranes also can be lost a part, therefore only stays ground floor Si oxide 14 and 24.
At first form the photoresist pattern in protection nmos area territory in the nmos area territory; ground floor silicon oxide layer and wall with multilayer film is mask protection PMOS zone polysilicon gate then; with the reactive ion beam etching (RIBE) method etching that caves in is leaked in the PMOS source, form the depression etch areas.Remove photoresist layer.Multilayer film and wall leak silicon dent zone epitaxial growth SiGe as the polysilicon gate of hard mask protection PMOS and NMOS in the PMOS source.
Form the photoresist pattern in protection PMOS zone in the PMOS zone; ground floor silicon oxide layer and wall with multilayer film is mask protection nmos area territory polysilicon gate then; with the reactive ion beam etching (RIBE) method etching that caves in is leaked in the NMOS source; form the depression etch areas of NMOS; remove photoresist; multilayer film and wall leak silicon dent zone epitaxial growth silicon-carbon as the polysilicon gate of hard mask protection NMOS and PMOS in the NMOS source.
G and h step are with embodiment 1.
Embodiment 4
Multilayer film is as the manufacture method of the CMOS with strain source-drain PMOS and strain source-drain NMOS of hard mask and anti-reflecting layer.
Wherein a～the c in the making step is identical with embodiment 1.Other steps are as follows:
D～f) is in the etch back process of wall, and two membranes also can be lost a part, therefore only stays ground floor Si oxide 14 and 24.
At first form the photoresist pattern in protection PMOS zone in the PMOS zone; ground floor silicon oxide layer and wall with multilayer film is mask protection nmos area territory polysilicon gate then; with the reactive ion beam etching (RIBE) method etching that caves in is leaked in the NMOS source; form the depression etch areas of NMOS; remove photoresist; multilayer film and wall leak silicon dent zone epitaxial growth silicon-carbon as the polysilicon gate of hard mask protection NMOS and PMOS in the NMOS source.
Form the photoresist pattern in protection nmos area territory in the nmos area territory; ground floor silicon oxide layer and wall with multilayer film is mask protection PMOS zone polysilicon gate then; with the reactive ion beam etching (RIBE) method etching that caves in is leaked in the PMOS source, form the depression etch areas.Remove photoresist layer.Multilayer film and wall leak silicon dent zone epitaxial growth SiGe as the polysilicon gate of hard mask protection PMOS and NMOS in the PMOS source.
G and h step are with embodiment 1.
In above technological process, the two kinds of material of second and third layer in the trilamellar membrane are consumed by various ion beam etchings and wet method removal process.Final Si oxide is removed after the epitaxial growth of the SiGe of finishing the source leakage or silicon-carbon.Because hydrofluoric acid base wet etching has high selectivity to oxide with respect to the silicon nitride comprising wall, therefore the trilamellar membrane that keeps is that the ground floor silicon oxide layer is easy to be removed, and can not produce obvious erosion to wall.
Claims (18)
1. multilayer film comprises the steps: as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer
A) form P, N well, form gate oxide level, polysilicon layer, multilayer film, photoresist layer on the silicon substrate of shallow isolating trough successively, this multilayer film comprises Si oxide and silicon nitrogen oxide, the anti-reflecting layer of this multilayer film during as photoetching and the hard mask during the silicon dent etching;
B) photoetching, etching form the polysilicon gate conductive structure;
C) form the polysilicon gate wall;
D) with multilayer film and wall be the polysilicon gate of mask protection PMOS,, the etching that caves in leaked in the PMOS source with photoresist protection nmos area territory;
E) remove photoresist
F) with multilayer film and wall being the polysilicon gate of mask protection PMOS, is mask protection nmos area territory with multilayer film and wall, and depression etch areas epitaxial growth SiGe is leaked in the PMOS source;
G) remove the conduct multilayer film of mask firmly;
H) carry out other successive process.
2. multilayer film according to claim 1 is characterized in that described multilayer film comprises: ground floor silicon oxide layer, second layer silicon oxynitride layer, the 3rd layer of silicon oxide layer as the strain source leakage CMOS manufacture method of hard mask and anti-reflecting layer.
3. multilayer film according to claim 1 is characterized in that as the strain source leakage CMOS manufacture method of hard mask and anti-reflecting layer described multilayer film is to adopt chemical vapor deposition.
4. multilayer film according to claim 1 is characterized in that as the strain source leakage CMOS manufacture method of hard mask and anti-reflecting layer described multilayer film adopts the plasma-reinforced chemical vapor deposition method to form.
5. multilayer film according to claim 1 is characterized in that as the strain source leakage CMOS manufacture method of hard mask and anti-reflecting layer described multilayer film adopts spin coating method to form.
6. multilayer film according to claim 2 is as the strain source leakage CMOS manufacture method of hard mask and anti-reflecting layer, it is characterized in that, described multilayer film, ground floor Si oxide layer thickness is 50～300A, second layer silicon nitrogen oxide layer thickness is 100～400A, and the 3rd layer of Si oxide layer thickness is 50～250A.
7. multilayer film according to claim 1 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer the hard mask of described multilayer film is removed with hydrofluoric acid base wet chemical process.
8. multilayer film comprises the steps: as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer
A. form P, N well, form gate oxide level, polysilicon layer, multilayer film, photoresist layer on the silicon substrate of shallow isolating trough successively, this multilayer film comprises Si oxide and silicon nitrogen oxide, the anti-reflecting layer of this multilayer film during as photoetching and the hard mask during the silicon dent etching;
B. photoetching, etching form the polysilicon gate conductive structure;
C. form the polysilicon gate wall;
D. be the polysilicon gate of mask protection NMOS with multilayer film and wall,, the etching that caves in leaked in the NMOS source with photoresist protection PMOS zone;
E. remove photoresist;
F. being the polysilicon gate of mask protection NMOS with multilayer film and wall, is mask protection PMOS zone with multilayer film and wall, and depression etch areas epitaxial growth silicon-carbon is leaked in the NMOS source;
G. remove multilayer film as hard mask;
H. carry out other successive process.
9. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer described multilayer film is to be made of first silicon oxide layer, the second silicon oxynitride layer, the 3rd silicon oxide layer.
10. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer described multilayer film is to adopt chemical vapor deposition.
11. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer described multilayer film adopts the plasma-reinforced chemical vapor deposition method to form.
12. hard mask of multilayer film conduct according to claim 8 and anti-reflecting layer, it is characterized in that described multilayer film adopts spin coating method to form.
13. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer, described multilayer film, and ground floor Si oxide layer thickness is 50～300A.
14. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer, described multilayer film, and second layer silicon nitrogen oxide layer thickness is 100～400A.
15. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer, described multilayer film, and the 3rd layer of Si oxide layer thickness is 50～250A.
16. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer the hard mask of described multilayer film is removed with hydrofluoric acid base wet processing.
17. multilayer film according to claim 1 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer, can also at first carry out the SiGe epitaxial growth of the source leakage of PMOS, carries out the silicon-carbon epitaxial growth that leak in the NMOS source then.
18. multilayer film according to claim 8 is characterized in that as the manufacture method of the strain source leakage CMOS of hard mask and anti-reflecting layer, can also at first carry out the silicon-carbon epitaxial growth of the source leakage of NMOS, carries out the SiGe epitaxial growth that leak in the PMOS source then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100290950A CN100452354C (en) | 2005-08-25 | 2005-08-25 | Producing method for strain source leakage CMOS using multilayer film as hard mask and anti-reflecting layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100290950A CN100452354C (en) | 2005-08-25 | 2005-08-25 | Producing method for strain source leakage CMOS using multilayer film as hard mask and anti-reflecting layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1921087A true CN1921087A (en) | 2007-02-28 |
| CN100452354C CN100452354C (en) | 2009-01-14 |
Family
ID=37778753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100290950A Active CN100452354C (en) | 2005-08-25 | 2005-08-25 | Producing method for strain source leakage CMOS using multilayer film as hard mask and anti-reflecting layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100452354C (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355054B (en) * | 2007-07-27 | 2010-07-28 | 联华电子股份有限公司 | Method for preparing complementary type metal-oxide-semiconductor transistor |
| CN102842607A (en) * | 2011-06-23 | 2012-12-26 | 上海华虹Nec电子有限公司 | Germanium-silicon triode base region hard mask membrane layer structure and manufacturing method thereof |
| CN103137564A (en) * | 2011-11-22 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device |
| CN102171384B (en) * | 2008-05-28 | 2013-12-25 | 乔治洛德方法研究和开发液化空气有限公司 | Silicon carbide-based antireflective coating |
| CN104022063A (en) * | 2013-03-01 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench |
| CN104064465A (en) * | 2013-03-21 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN104347474A (en) * | 2013-07-25 | 2015-02-11 | 德克萨斯仪器股份有限公司 | Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile |
| CN104064468B (en) * | 2013-03-21 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN108666272A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6657223B1 (en) * | 2002-10-29 | 2003-12-02 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication |
| US6734527B1 (en) * | 2002-12-12 | 2004-05-11 | Advanced Micro Devices, Inc. | CMOS devices with balanced drive currents based on SiGe |
| US6800530B2 (en) * | 2003-01-14 | 2004-10-05 | International Business Machines Corporation | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors |
| US6891192B2 (en) * | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
| CN1328795C (en) * | 2003-10-31 | 2007-07-25 | 北京大学 | Source/drain sink type ultrathin SOIMOS transistor and method for preparing IC |
-
2005
- 2005-08-25 CN CNB2005100290950A patent/CN100452354C/en active Active
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355054B (en) * | 2007-07-27 | 2010-07-28 | 联华电子股份有限公司 | Method for preparing complementary type metal-oxide-semiconductor transistor |
| CN102171384B (en) * | 2008-05-28 | 2013-12-25 | 乔治洛德方法研究和开发液化空气有限公司 | Silicon carbide-based antireflective coating |
| CN102842607A (en) * | 2011-06-23 | 2012-12-26 | 上海华虹Nec电子有限公司 | Germanium-silicon triode base region hard mask membrane layer structure and manufacturing method thereof |
| CN102842607B (en) * | 2011-06-23 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Hard mask membrane layer structure in a kind of germanium silicon triode base and preparation method thereof |
| CN103137564B (en) * | 2011-11-22 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device |
| CN103137564A (en) * | 2011-11-22 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device |
| CN104022063A (en) * | 2013-03-01 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench |
| CN104064465A (en) * | 2013-03-21 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN104064468B (en) * | 2013-03-21 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN104064465B (en) * | 2013-03-21 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN104347474A (en) * | 2013-07-25 | 2015-02-11 | 德克萨斯仪器股份有限公司 | Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile |
| CN104347474B (en) * | 2013-07-25 | 2018-11-13 | 德克萨斯仪器股份有限公司 | The CMOS manufacturing methods using the hard mask of multilayer epitaxial for improved EPI distributions |
| CN108666272A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100452354C (en) | 2009-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1921087A (en) | Producing method for strain source leakage CMOS using multilayer film as hard mask and anti-reflecting layer | |
| CN1229853C (en) | Substrate producing method for semiconductor device and substrate for semiconductor device | |
| CN1893028A (en) | Strain source-drain CMOS integrating method with oxide separation layer | |
| US8603919B2 (en) | Method for fabricating semiconductor device | |
| CN1959957A (en) | Integration design method and structure of using transistors of strain silicon | |
| CN101770974B (en) | Method for fabricating shallow-trench isolation structure | |
| CN1881586A (en) | Semiconductor device and fabrication process thereof | |
| CN1512272A (en) | Method for producing semiconductor device using argon fluoride exposure light source | |
| CN1255860C (en) | Method for forming stack mulberry pattern | |
| CN1270354C (en) | Contact hole forming method of semiconductor component | |
| CN1728346A (en) | Method for forming a resist protect layer on substrate and substrate having blocking protecting layer | |
| CN1707771A (en) | Method for forming contact plug of semiconductor device | |
| CN1697154A (en) | Method for fabricating semiconductor device having trench isolation | |
| CN1433051A (en) | Protective film pattern sorming method and semiconductor device manufacturing process | |
| CN1315173C (en) | Method for fabricating semiconductor device having trench type device isolation layer | |
| CN1921086A (en) | Integrated producing method for strain CMOS | |
| US20040157385A1 (en) | Method for manufacturing a semiconductor device by using a dry etching technique | |
| CN1440049A (en) | Manufacture for semiconductor devices | |
| US7795151B2 (en) | Methods of forming a trench having side surfaces including a uniform slope | |
| CN1309018C (en) | Simple technology for manufacturing semiconductor device | |
| US7338906B2 (en) | Method for fabricating semiconductor device | |
| CN1761072A (en) | Transistor and strained channel element formation method | |
| CN1889236A (en) | Polycrystalline silicon grating doping method | |
| US7473645B2 (en) | Method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate | |
| CN100338761C (en) | Method of manufacturing a layer sequence and a method of manufacturing an integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111129 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111129 Address after: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |