CN102097286B - Method for monitoring step profiler in measuring accuracy of chip groove depth - Google Patents
Method for monitoring step profiler in measuring accuracy of chip groove depth Download PDFInfo
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- CN102097286B CN102097286B CN2009102424888A CN200910242488A CN102097286B CN 102097286 B CN102097286 B CN 102097286B CN 2009102424888 A CN2009102424888 A CN 2009102424888A CN 200910242488 A CN200910242488 A CN 200910242488A CN 102097286 B CN102097286 B CN 102097286B
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Abstract
The invention discloses a method for monitoring a step profiler in measuring the accuracy of chip groove depth, which reduces the delay on monitoring of the chip groove depth, improves the accuracy on monitoring of the groove depth and achieves the purpose of monitoring the step profiler in measuring the accuracy of the chip groove depth. The method comprises the following steps of: selecting a plurality of wafers, and determining the depth of a groove in a wafer chip area through measuring the depth of a groove in a wafer scribing channel area and the thickness of a hard mask layer by the step profiler in allusion to each wafer; and determining whether the accuracy of the groove depth measured by the step profiler reaches the requirements on the accuracy through analyzing the depth value of the groove in the chip area of the plurality of the wafers. By adopting the technical scheme, the time delay on monitoring of the chip depth can be shortened, the accuracy on controlling of the chip groove depth is improved, and the purpose of monitoring the step profiler in measuring the accuracy of the groove depth is realized.
Description
Technical field
The present invention relates to the semiconductor device layout design field, relate in particular to a kind of monitoring step appearance measured chip gash depth method of accuracy.
Background technology
Source drain breakdown voltage Bvdss and source leakage conductance energising resistance Rdson are the comparatively crucial parameters of low pressure groove DMOS (DMOS) device; These two parameters are comparatively responsive each other, and generally speaking, the desired value of Bvdss is 20 volts～100 volts; The desired value of Rdson is for being lower than tens milliohms; Because the value of Bvdss and Rdson is relevant with gash depth, so the gash depth difference may determine the Bvdss and the Rdson of different values, therefore; In dried ditch groove technical process, the degree of depth of groove controlled accurately seem particularly important.
At present, the DMOS of conventional design (Double-diffused Metal Oxide Semiconductor, double-diffused metal oxide semiconductor) trench lithography layer domain only need have groove figure in the chip region of wafer; But the degree of depth of present groove and the ratio of width are bigger; Generally speaking, shown in Fig. 3 A, the width of the groove of chip region is about 0.4um; The degree of depth of groove is about 1.3um～2.5um; And the diameter of the probe of step appearance is generally more than tens um, therefore, if adopt the step appearance degree of depth of chip groove to be measured the internal structure that may destroy chip; Therefore, can't adopt the step appearance that the degree of depth of chip groove is measured at present.At present; The monitoring mode that gash depth adopted is: have a fling at sheet in advance in advance, and the sheet of will going ahead of the rest carries out SEM (Scanning Electron Microscope., scanning electron microscopy) section; When carrying out the groove etching work procedure; Whether the degree of depth of doing the groove that obtains after quarter through scanning SEM observation reaches predetermined degree of depth requirement, if do not have, then through calculating etch rate or increase etch period or reducing etch period and control the degree of depth requirement that the degree of depth of groove reaches setting.
Though can control the degree of depth requirement that the degree of depth of groove reaches setting to a certain extent, still there is following defective in prior art:
(1) because when carrying out etching groove at every turn; All need a large amount of sheets in advance to do the section monitoring, and with SEM the current degree of depth of groove is measured, whether the data decision that measures according to SEM again adjusts the time of dried ditch groove; Therefore, consuming time long.
(2) some quarters, equipment was in the work defective mode; When etch rate has fluctuation; Do not reach the degree of depth requirement of setting in the degree of depth of groove, do the time at quarter and possibly cause the degree of depth of the groove after the etching inaccurate, will cause the yield of product then if adjust according to the etch rate of this fluctuation; In addition, if the measurement data that SEM itself also possibly cause when having the lower problem of measuring accuracy the current degree of depth of groove is measured is inaccurate, thereby cause the degree of depth of the groove after the actual etching can not reach the degree of depth requirement of setting.
Summary of the invention
The embodiment of the invention provides a kind of monitoring step appearance measured chip gash depth method of accuracy, to reduce time delay that the chip gash depth is monitored, to improve the accuracy of gash depth monitoring and reach the purpose that the accuracy of step appearance measured chip gash depth is monitored.
A kind of method of accuracy of monitoring step appearance measured chip gash depth comprises:
Fill each wafer in the multi-disc wafer of polarity same trench depth test module of trench lithography layer of polarity and chip region to the cross ecotone in street district; For said wafer is provided with corresponding etching duration, carry out the gash depth d that following step obtains the chip region of said multi-disc wafer:
Generate layer protecting film at said crystal column surface; Chip region and street district to said wafer carry out trench lithography and etching groove processing; The etching groove duration is the etching duration of the corresponding setting of said wafer; Form first groove in said chip region, in the gash depth test module in said street district, be formed for second groove that the degree of depth to said first groove detects; The degree of depth that adopts the step appearance to measure said second groove is d1; Obtain the depth d of said first groove according to the thickness d 2 of said d1 and said diaphragm;
The degree of depth of second groove in the street district of the said multi-disc wafer of employing scanning electron microscopy measurement is d ';
The depth d of second groove of the said multi-disc wafer that obtains according to the depth d 2 of second groove of the multi-disc wafer that obtains through said step appearance, the first gash depth d and through scanning electron microscopy, whether the accuracy of determining the gash depth in said step appearance measured chip district reaches accuracy requirement.
In the embodiment of the invention; On the one hand; The depth value of first gash depth of the chip region of a plurality of wafers that the step appearance is measured and first groove of the corresponding wafer that scanning electron microscope test obtains compares; Thereby judge that the step appearance measures the accuracy of gash depth and whether meet the requirement of expectation, thereby realized that the accuracy of the step appearance being measured gash depth monitors, with the accuracy of the gash depth value of the chip region that guarantees to measure; On the other hand, introduce the gash depth test module, and the chip region and the street district of wafer all carried out the operation of trench lithography and etching groove, in the gash depth test module in chip region and street district, form groove in the street district of wafer; Measure the degree of depth of the groove in the gash depth test module through the step appearance, and determine the degree of depth of the groove of chip region according to the thickness of the diaphragm of the degree of depth of this groove and crystal column surface.Adopt technical scheme of the present invention; Only need to adopt the step appearance can be in real time, the degree of depth of the groove in monitoring chip district accurately; Thereby overcome and need carry out the degree of depth that slicing treatment measures the chip region groove extremely to sheet in advance through scanning electron microscopy when the chip gash depth is measured at every turn in the prior art, and determined whether to adjust according to the degree of depth of groove and do the time at quarter and cause the problem big to gash depth monitoring time-delay, that accuracy is lower.
Description of drawings
Figure 1A is a monitoring step appearance measured chip gash depth method of accuracy flow process in the embodiment of the invention;
Figure 1B is for measuring the method flow diagram of chip wafer district gash depth in the embodiment of the invention;
Fig. 2 A is the sketch map of crystal column surface in the prior art;
Fig. 2 B is a sketch map of in the street of the cross zone of crystal column surface, introducing the gash depth test module in the embodiment of the invention;
Fig. 3 A is the sketch map that forms groove in the prior art in the chip region of wafer;
Fig. 3 B is the sketch map that forms groove in the chip region and the street district of wafer in the embodiment of the invention;
The data list that Fig. 4 detects for the accuracy that is used in the embodiment of the invention the step appearance test trenches degree of depth;
Fig. 5 be step appearance in the embodiment of the invention, the SEM test trenches degree of depth and calculate gash depth between the corresponding relation curve chart;
Fig. 6 is total etching duration correspondence table of chip wafer gash depth and consumption in the embodiment of the invention.
Embodiment
Below in conjunction with Figure of description the embodiment of the invention is carried out detailed description.
Referring to Figure 1A, be monitoring step appearance measured chip gash depth method of accuracy flow process in the embodiment of the invention, this flow process comprises step:
The depth value of the chip region groove of depth value, the depth value d of chip region groove and these a plurality of wafers that SEM measures of the groove in the street district of step 104, these a plurality of wafers of measuring according to the step appearance confirms that the step appearance measures the accuracy of gash depth and whether meet the expectation requirement.
The concrete realization flow of the step 104 in the above-mentioned flow process is shown in Figure 1B.
Referring to Figure 1B; For measuring the method flow diagram of chip wafer district gash depth in the embodiment of the invention; This flow process is that example describes with any wafer in the above-mentioned multi-disc wafer, and the cross ecotone filling shape at crystal column surface is the module (being the gash depth test module) of cuboid in advance, and the polarity of this module is identical with the polarity of the trench lithography layer of chip region; And when photoetching process, this cuboid module is that the district is opened in photoetching; This flow process may further comprise the steps:
Step 201, generate layer protecting films on wafer 21 surface, like hard mask layer 31.
The structure of the wafer in this step is filling groove depth test module 23 gained in all or part of cross ecotone 22 of existing wafer 21 shown in Fig. 2 A shown in Fig. 2 B.Preferably; In order to reach the effect of better measurement gash depth; In the embodiment of the invention; In the wafer 21 with respect to being filled with gash depth test module 23 in the equally distributed a plurality of cross ecotones 22 of crystal column surface, shown in Fig. 2 B, be filled with gash depth test module 23 in equally distributed 5 cross ecotones 22 in wafer 21 surfaces.Wherein, the width of the upper surface of gash depth test module 23 can be set to 60um, and length is set to 100um, and these a plurality of gash depth test modules 23 that are distributed in wafer 21 surface are processed the reticle that the GDS file is handed over the channeled layer that plate-making factory processes.
In the embodiment of the invention, can also adopt existing comparatively conventional mode to generate hard mask layer 31 with the growth pad oxide as hard mask layer 31, implementation be varied.
Step 202, simultaneously chip region in the wafer 21 and street district are carried out lithography operations, and form the trench lithography figure in chip region and street district respectively.
Step 203, hard mask layer 31 is carried out etching operation, form the etching figure in chip region and street district respectively.
The photoresist layer (photoresist layer marks in the accompanying drawings) on step 204, removal wafer 21 surfaces.
Step 205, simultaneously chip region and street district are carried out etching groove; The setting etching groove duration that etching groove duration and this wafer are corresponding is identical, forms in chip region and is formed for groove 34 that the degree of depth of groove 33 is monitored in groove 33 and the gash depth test module 23 in the street district.
In this step; Shown in Fig. 3 B; (probe of step appearance is a cone shape to the width of the groove 33 that forms less than the maximum gauge of the probe of step appearance 32; The maximum gauge of probe is exactly the bottom surface diameter of a circle of this cone), therefore the width of groove 34 can be measured through the degree of depth of 32 pairs of grooves 34 of step appearance greater than the maximum gauge of the probe of step appearance 32.
Step 206, measure the thickness (representing) of the hard mask layer 31 on wafer 21 surfaces through blooming tester (in the accompanying drawing mark) with d2.
Step 207, measure the degree of depth (representing) of grooves 34 in real time through step appearance 32 with d1.
In this step, the mode of the degree of depth of probe 32 test trenches 34 through the step appearance is following: step appearance probe 32 is streaked the gash depth test module 23 that is positioned at street district cross ecotone 22, and the test data that obtains is the depth value of groove 34.
Step 208, determine the degree of depth (representing) of the groove 33 of chip region according to the thickness d of hard mask layer 31 2 and the depth d 1 of groove 34 with d.
In this step, confirm that the degree of depth of the groove 33 of chip region is specially: the depth d (being d=(d1-d2)) of (d1-d2) being confirmed as groove 33.
When the depth d of step 209, the groove in determining chip region 33 reaches the depth threshold of setting, remove the hard mask layer 31 on wafer 21 surfaces.
Preferably; In order better to monitor the accuracy that the step tester is monitored gash depth; Find in time whether the test of step appearance is accurate; Whether accurately the embodiment of the invention is also set up the degree of depth and the step appearance of the groove 33 in SEM test chip district and is tested the graph of relation of the degree of depth of the groove 34 of drawing the section, road, and whether analyze the test of step appearance through this graph of relation accurate, thereby reach timely monitoring step appearance test purpose.
Whether the accuracy of with a concrete instance the definite step appearance in the above-mentioned process step 104 being measured gash depth below meets expectation requires to carry out detailed description.
In the embodiment of the invention; (numbering is respectively 01#～06#) to be taken at 6 wafer of introducing the gash depth test module in the street district; And be that this 6 wafer is set corresponding etching duration; The etching duration of 01#～06# wafer is linear change, as sets gradually and be 140s, 155s, 170s, 185s, 200s, 215s; And the desired value of the depth value of the groove of the chip region of setting 01#～06# wafer is followed successively by 1.45um, 1.55um, 1.65um, 1.75um, 1.85um, 1.95um.
To each wafer in above-mentioned 6 wafer, carry out following operation:
Etching groove mode in step 1, the above-mentioned flow process of employing is carried out etching processing to the gash depth test module in chip wafer district and the street district; The etching duration of this wafer setting etching duration corresponding with this wafer equated, form groove and in the gash depth test module in this wafer street district, form groove in the chip region of this wafer.
Step 3, adopt SEM directly to measure the degree of depth of groove of the chip region of above-mentioned wafer, the depth value that obtains is d ' and record.
Can obtain three groups of data of 6 wafer through above-mentioned three steps.
Each wafer that data list as shown in Figure 4 is record carries out the duration of etching groove and three groups of data of correspondence thereof; According to the data of list records shown in Figure 4, obtain many curve of approximation graphs of a relation as shown in Figure 5, whether the accuracy that the step appearance is measured gash depth meets expectation requires to judge that judgment mode is following:
The depth value of the chip region groove of 01#～06# wafer that the gash depth in step 3, the street district that will measure through the step appearance obtains connects with broken line, obtains curve of approximation Q2;
Step 4, these three curves are analyzed, relatively confirm that the step appearance measures the accuracy of gash depth.As: comparing data curve Q1 and data and curves Q3 can know; The both is approximate linear change; And these two slope of a curve approximately equals (promptly to each wafer, determine obtain this wafer through the test of step appearance the difference of depth value and the depth value of the chip region groove of measuring this wafer through SEM of chip region groove in the fluctuation range of setting); Comparing data curve Q3 and data and curves Q2 can know that these two curves are identical basically; Thereby can determine through the accuracy of step appearance measurement gash depth higher.
Can know through comparative analysis; The depth value that the gash depth of measuring wafer street district through the step appearance obtains the groove of chip region equates with the depth value of the groove of the direct chip region that measures through SEM basically; Therefore, the accuracy of the degree of depth of the groove in chip wafer district being monitored through the step appearance is higher.If obtain the step appearance to the measurement of gash depth when inaccurate according to above-mentioned three tracing analysis, then need be to operations such as the step appearance overhaul, the accuracy of the degree of depth of the groove of chip region being monitored with further assurance step appearance.
Preferably; For in the depth accuracy of the formed groove of chip region, shortening required debug time and debugging number of times and shortening product operation time delay in the etching groove process in the further assurance practical application; The embodiment of the invention is being determined accuracy that the step appearance measures gash depth when higher according to aforesaid way, may further comprise the steps:
When the degree of depth that adopts the step appearance to monitor the groove in chip wafer district reached the depth threshold of setting, record carried out total etching duration of etching groove institute actual consumption to the chip of this wafer, and sets up this total etching duration and the corresponding relation of depth threshold; When follow-up chip region to other wafers is carried out etching groove; Directly according to this corresponding relation; The etching duration of etching groove is carried out in adjustment to the chip region of above-mentioned other wafers; So that the degree of depth of the groove of chip region reaches the depth threshold of setting, do not need again the degree of depth of frequent groove according to current chip region to adjust etch period so that the degree of depth of the groove of chip region reaches the depth threshold of setting.Adopt this kind mode when guaranteeing to obtain accurately gash depth, also to have shortened chip is carried out required debug time and debugging number of times in the etching groove process, thereby further improve product operation time delay, raise the efficiency.When in practical application, in batches wafer being carried out etching groove, effect is particularly remarkable.
With 6 wafer of enumerating in the embodiment of the invention is that example is carried out detailed description to above-mentioned mode, as:
Be respectively 01#～corresponding gash depth threshold value of 06# wafer setting and be respectively 1.55um, 1.65um, 1.75um, 1.85um, 1.95um, 2.05um.
Continuation is carried out etching to the groove of the chip region of above-mentioned 01#～06# wafer; Adopt the gash depth of the chip region of step appearance monitoring 01#～06# wafer; When the gash depth of the chip region that monitors this 6 wafer reaches 1.55um, 1.65um, 1.75um, 1.85um, 1.95um, 2.05um respectively; Record is respectively t1, t2, t3, t4, t5, t6 to total etching duration (this total etching duration is total duration that gash depth is consumed from 0～gash depth threshold value) that this 01#～06# wafer carries out etching groove institute actual consumption, and it is as shown in Figure 6 to set up the corresponding relation of total etching duration of above-mentioned wafer and corresponding gash depth threshold value and actual consumption.Need carry out etching groove to other wafer the time, only need can adjust the duration that above-mentioned other wafers is carried out etching groove follow-up according to corresponding relation as shown in Figure 6.
Technical scheme of the present invention is mainly used in and is not limited in the DMOS device, also can be applicable in IGBT (Insulated Gate Bipolar Transistor, the insulated gate bipolar transistor) device.
In the embodiment of the invention; On the one hand; The depth value of first gash depth of the chip region of a plurality of wafers that the step appearance is measured and first groove of the corresponding wafer that scanning electron microscope test obtains compares; Thereby judge that the step appearance measures the accuracy of gash depth and whether meet the requirement of expectation, thereby realized that the accuracy of the step appearance being measured gash depth monitors, with the accuracy of the gash depth value of the chip region that guarantees to measure; On the other hand, introduce the gash depth test module, and the chip region and the street district of wafer all carried out the operation of trench lithography and etching groove, in the gash depth test module in chip region and street district, form groove in the street district of wafer; Measure the degree of depth of the groove in the gash depth test module through the step appearance, and determine the degree of depth of the groove of chip region according to the thickness of the diaphragm of the degree of depth of this groove and crystal column surface.Adopt technical scheme of the present invention; Only need to adopt the step appearance can be in real time, the degree of depth of the groove in monitoring chip district accurately; Thereby overcome and need carry out the degree of depth that slicing treatment measures the chip region groove extremely to sheet in advance through scanning electron microscopy when the chip gash depth is measured at every turn in the prior art, and determined whether to adjust according to the degree of depth of groove and do the time at quarter and cause the problem big to gash depth monitoring time-delay, that accuracy is lower; Again on the one hand; In the embodiment of the invention; Obtain accuracy that the step appearance measures gash depth when higher in analysis; When the degree of depth that adopts the step appearance to monitor the groove in chip wafer district reached the depth threshold of setting, record carried out the etching duration of etching groove institute actual consumption to the chip of this wafer, and sets up the corresponding relation of this etching duration and depth threshold; When follow-up chip region to other wafers is carried out etching groove; Directly according to this corresponding relation; The etching duration of etching groove is carried out in adjustment to the chip region of above-mentioned other wafers; Do not need again the degree of depth of frequent groove according to current chip region to adjust etch period so that the degree of depth of the groove of chip region reaches the depth threshold of setting; Thereby when guaranteeing to obtain accurately gash depth, also shortened chip has been carried out required adjustment time and adjustment number of times in the etching groove process, thereby further shortened product operation time delay, raised the efficiency.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. a method of accuracy of monitoring step appearance measured chip gash depth is characterized in that, comprising:
Fill each wafer in the multi-disc wafer of polarity same trench depth test module of trench lithography layer of polarity and chip region to the cross ecotone in street district; For said wafer is provided with corresponding etching duration, carry out the gash depth d that following step obtains the chip region of said multi-disc wafer:
Generate layer protecting film at said crystal column surface; Chip region and street district to said wafer carry out trench lithography and etching groove processing; The etching groove duration is the etching duration of the corresponding setting of said wafer; Form at least one first groove in said chip region, in the gash depth test module in said street district, be formed for second groove that the degree of depth to said first groove detects; The degree of depth that adopts the step appearance to measure said second groove is d1; Obtain the depth d of said first groove according to the thickness d 2 of said d1 and said diaphragm;
The degree of depth of second groove in the street district of the said multi-disc wafer of employing scanning electron microscopy measurement is d ';
The depth d of second groove of the said multi-disc wafer that obtains according to the depth d 2 of second groove of the multi-disc wafer that obtains through said step appearance, the first gash depth d and through scanning electron microscopy, whether the accuracy of determining the gash depth in said step appearance measured chip district reaches accuracy requirement.
2. the method for claim 1 is characterized in that, the etching duration of the setting that said multi-disc wafer is corresponding is linear change;
The said accuracy of determining the gash depth in said step appearance measured chip district is specially:
Etching duration from low to high the order of said a plurality of wafers according to correspondence sorted;
Change if the depth value d1 of second groove of the said a plurality of wafers after the ordering is equal difference successively, and (d-d ') of each wafer in the fluctuation range of setting the time, confirm that then said step appearance measures the accuracy of gash depth and reach accuracy requirement.
3. the method for claim 1 is characterized in that, the cross ecotone filling groove depth test module in the street district of each wafer in the said multi-disc wafer is specially:
In crystal column surface with respect to being filled with the gash depth test module in the equally distributed a plurality of cross ecotones of crystal column surface.
4. the method for claim 1 is characterized in that, said first groove and said second groove are cuboid;
The width of said first groove is less than the maximum gauge of the probe of said step appearance, and the width of said second groove is greater than the maximum gauge of the probe of said step appearance.
5. the method for claim 1 is characterized in that, obtains the depth d of said first groove according to the thickness d 2 of said d1 and said diaphragm, is specially:
The difference of said d1 and d2 is confirmed as the depth d of said first groove.
6. like each described method of claim 1～5, it is characterized in that, obtain the thickness d 2 of the diaphragm of said crystal column surface, be specially:
Adopt the blooming tester to measure the thickness of said diaphragm, and the measurement data of said blooming tester is confirmed as the thickness d 2 of said diaphragm.
7. like each described method of claim 1～5, it is characterized in that, also comprise:
To each wafer in the said multi-disc wafer, after the chip region of said wafer and street district obtain first groove and second groove respectively, remove the diaphragm of said crystal column surface.
8. like each described method of claim 1～5, it is characterized in that said diaphragm is a hard mask layer.
9. like each described method of claim 1～5, it is characterized in that, after the accuracy of the groove of determining said step appearance measured chip district reaches accuracy requirement, also comprise step:
For said multi-disc wafer is set corresponding gash depth threshold value d respectively ", and the corresponding gash depth threshold value d of each wafer " greater than the depth value d of separately first groove;
To each wafer in the said multi-disc wafer; Continuation is carried out etching to first groove of this wafer; The degree of depth that measures first groove of said wafer through the step appearance reaches d " time; the degree of depth that writes down first groove of this wafer arrives d from d " the second etching duration, the degree of depth of confirming as first groove of said wafer with value of the setting etching duration that said wafer is corresponding and the duration of said second etching reaches d " total duration of being consumed;
According to the gash depth threshold value of said multi-disc wafer correspondence and total duration of consumption, set up the gash depth threshold value of each wafer and correspondence thereof and the corresponding relation of total duration.
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| CN102915999B (en) * | 2011-08-03 | 2016-08-03 | 无锡华润上华半导体有限公司 | Trench polisilicon excessive erosion step-on testing figure and forming method thereof |
| CN103247549B (en) * | 2013-04-02 | 2015-11-18 | 中国电子科技集团公司第五十五研究所 | A kind of photosensitive mask etching method of carborundum that shoulder height is monitored in real time |
| CN107316821B (en) * | 2016-04-27 | 2021-03-12 | 中芯国际集成电路制造(上海)有限公司 | Depth stability detection method |
| CN106839937B (en) * | 2017-01-23 | 2019-08-06 | 安徽三安光电有限公司 | A kind of wafer thickness measuring device and its measurement method |
| CN107816949B (en) * | 2017-11-01 | 2019-08-06 | 长江存储科技有限责任公司 | A kind of accumulation layer measured film thickness method for 3D nand memory |
| CN109659296B (en) * | 2018-12-18 | 2020-07-10 | 武汉华星光电半导体显示技术有限公司 | Test key for monitoring etching depth of O L ED panel and O L ED large panel |
| CN112355882B (en) * | 2020-11-09 | 2022-04-22 | 西安奕斯伟硅片技术有限公司 | Method and system for measuring depth of damaged layer on surface of wafer |
| CN115602561B (en) * | 2021-12-23 | 2024-04-09 | 和舰芯片制造(苏州)股份有限公司 | Structure size measuring method and reference pattern for wafer manufacturing process |
| CN116772742B (en) * | 2023-08-23 | 2023-10-27 | 江苏永钢集团有限公司 | Method for measuring vibration mark depth of continuous casting square billet |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001075393A1 (en) * | 2000-03-31 | 2001-10-11 | Advanced Micro Devices, Inc. | Thickness measurement using afm for next generation lithography |
| CN101523287A (en) * | 2006-09-29 | 2009-09-02 | 朗姆研究公司 | Offset correction methods and arrangement for positioning and inspecting substrates |
-
2009
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001075393A1 (en) * | 2000-03-31 | 2001-10-11 | Advanced Micro Devices, Inc. | Thickness measurement using afm for next generation lithography |
| CN101523287A (en) * | 2006-09-29 | 2009-09-02 | 朗姆研究公司 | Offset correction methods and arrangement for positioning and inspecting substrates |
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