KR970011655B1 - Mark fabrication and measurement method lfor alignment measurement - Google Patents

Mark fabrication and measurement method lfor alignment measurement Download PDF

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Publication number
KR970011655B1
KR970011655B1 KR1019940001950A KR19940001950A KR970011655B1 KR 970011655 B1 KR970011655 B1 KR 970011655B1 KR 1019940001950 A KR1019940001950 A KR 1019940001950A KR 19940001950 A KR19940001950 A KR 19940001950A KR 970011655 B1 KR970011655 B1 KR 970011655B1
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South Korea
Prior art keywords
bar
contact hole
alignment
measurement
forming
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KR1019940001950A
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Korean (ko)
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KR950025944A (en
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함영목
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현대전자산업 주식회사
김주용
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Priority to KR1019940001950A priority Critical patent/KR970011655B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

The measurement mark includes the steps of (a) forming the lower level, that is, element separation film, nitride oxide film, polycrystalline silicon layer, silicide layer, and metal layer at the cell region and a material bar(1) which forms a lower level at the scribe line(10) upper region of semiconductor substrate, (b) aligning contact hole at the upper region of a bar(1) and forming measurement signal measuring light intensity based on distance by using CD-SEM. As a result, an measurement mark increases the productivity and reduces the total process time since measuring time has been saved and it is possible to measure alignment with a lower level at the same time without measuring CD line width separate measurement device.

Description

측정마크 및 그 제조방법과 정렬도 측정방법Measurement mark, its manufacturing method and alignment method

제1도는 종래 기술에 의한 실시예로 측정마크를 도시한 평면도.1 is a plan view showing a measurement mark in the embodiment according to the prior art.

제2A도및 제2C도는 본 발명의 실시예로 측정마크 형성공정 및 정렬도 측정방법을 도시한 도면.2A and 2C are diagrams illustrating a measuring mark forming process and an alignment measuring method according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 바아(bar),3 : 콘택홀,1: bar, 3: contact hole,

7 : 바깥박스,10 : 스크라이브 라인7: outer box, 10: scribe line

본 발명은 측정마크 및 그 제조방법과 정렬도 측정방법에 관한 것으로, 셀부분에 형성해야 하는 여러층을 형성할 때 스크라이브 라인의 상부에 같은 물질로 바아(bar) 형태를 형성한 후, 셀부분에 콘택홀을 형성할 때 상기 바아의 상부에 정렬되게 콘택홀을 형성함으로써 측정마크를 형성하고, 상기 바아와 콘택홀이 중첩될 때 상기 바아의 왼쪽끝에서부터 왼쪽을 콘택홀까지의 거리, 즉 좌측 정렬도와 상기 바아의 오른쪽에서부터 오른쪽으로 콘택홀까지의 거리인 우측정렬도의 차에 절대값을 하는 값을 정렬도로 하는 기술로서, 상기 콘택홀을 측정할 때 하층과의 정렬도를 동시에 측정할 수 있고 공정시간을 단축시킬 수 있어 소자의 생산성을 향상시키는 것이다.The present invention relates to a measuring mark, a method of manufacturing the same, and a measuring method of alignment. When forming a plurality of layers to be formed in a cell part, a bar part is formed of the same material on the upper part of the scribe line, and then the cell part is formed. When the contact hole is formed in the contact hole to form a contact mark aligned with the top of the bar, when the bar and the contact hole overlaps the distance from the left end of the bar to the contact hole, that is, left The degree of alignment value of the absolute value of the difference between the degree of alignment and the degree of right alignment, which is the distance from the right side of the bar to the right side of the bar, and the degree of alignment with the lower layer can be measured simultaneously when the contact hole is measured. It is possible to shorten the process time and improve the productivity of the device.

반도체 소자의 콘택층은 상하층을 전기적으로 연결시키는 부분으로서, 공정시 설계마진에 의하여 상하층과의 정렬도를 좋게하여 제품의 특성을 갖추게 한다. 상기 콘택층으로는 다결정실리콘 콘택층, 금속 콘택층, 확산 콘택층 등이 있으며, 이러한 층은 하층물질위에 정확하게 형성되어야 제품의 특성을 살릴 수 있다.The contact layer of the semiconductor device is a part which electrically connects the upper and lower layers. The contact layer of the semiconductor device improves the degree of alignment with the upper and lower layers by the design margin during the process to provide the characteristics of the product. The contact layer may be a polysilicon contact layer, a metal contact layer, a diffusion contact layer, and the like, and such a layer may be formed on the lower layer material to make use of product characteristics.

종래 기술을 도면을 참고로하여 설명하기로 한다.The prior art will be described with reference to the drawings.

제1도는 종래 기술에 의한 측정마크를 도시한 단면도이다.1 is a cross-sectional view showing a measurement mark according to the prior art.

제1도는 공지의 기술로 스크라이브 라인에 형성된 박스 인 박스(box in box)의 측정마크를 도시한 평면도로서, 레이저광을 이용하여 인식함으로써, 정렬도를 측정한다. 여기서, 하부층형성시 형성되는 마크인 바깥박스(7)와 콘택 형성시 형성되는 마크인 안박스(9)를 측정할 때는 각각 측정마크를 측정하여야 하는데, 그로 인하여 별도의 측정시간을 필요로 하게 된다.1 is a plan view showing a measurement mark of a box in a box formed on a scribe line by a known technique, and the alignment degree is measured by recognizing using a laser beam. Here, when measuring the outer box 7 which is a mark formed when forming the lower layer and the inner box 9 which is a mark formed when forming the contact, each measurement mark should be measured, thereby requiring a separate measurement time.

따라서, 본 발명은 소자에 형성되는 하부층을 스크라이브 라인 상부에 형성한 다음, 셀 부위에 콘택홀을 형성할 때 상기 스크라이브 라인에 형성되어 있는 하부층의 상부에 정렬되게 콘택홀을 형성함으로써, 측정마크를 형성하고 콘택홀 및 하부층의 정렬도를 측정하는데 그 목적이 있다.Therefore, the present invention forms a lower layer formed on the device on the scribe line, and then forms contact holes in the upper part of the lower layer formed on the scribe line when forming a contact hole in the cell area, thereby measuring the measurement mark. The purpose is to form and measure the degree of alignment of the contact holes and underlying layers.

이상의 목적을 달성하기 위한 본 발명의 특징은, 셀부분에 형성되는 하부층을 스크라이브 라인상부에 바아 형태로 공정과, 상기 셀부분에 콘택홀을 형성할 때 상기 바아의 상부에 정렬되게 콘택홀을 형성하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is the step of forming a contact hole in the upper portion of the bar when forming a contact hole in the cell form the bottom layer formed on the scribe line on the cell portion, the contact hole is formed It includes the process to do.

이상의 다른 목적을 달성하기 위한 본 발명의 특징은, 셀부에 형성되는 하부층이 바아 형태로 스크라이브 라인에 형성되고 그 상부에 콘택홀이 구비되는 것이다.A feature of the present invention for achieving the above object is that the lower layer formed in the cell portion is formed in the scribe line in the form of a bar and the contact hole is provided on the upper portion.

이상의 또 다른 목적을 달성하기 위한 본 발명의 특징은, 셀부에 형성되는 하부층과 같은 물질로 스크라이브 라인의 상부에 형성된 바아와 셀부의 콘택홀과 같이 상기 바아의 상부에 형성된 콘택홀이 중첩될 때 상기 바아의 왼쪽끝으로부터 왼쪽으로 콘택홀까지의 거리인 좌측정렬도와 상기 바아의 오른쪽끝에서부터 오른쪽으로 콘택홀까지의 거리인 우측정렬도의 차의 절대값을 정렬도로 하는 것이다.A feature of the present invention for achieving the above object is that when the contact hole formed in the upper portion of the bar, such as the contact hole formed in the upper portion of the scribe line and the bar formed of the same material as the lower layer formed in the cell portion The absolute value of the difference between the left alignment, which is the distance from the left end of the bar to the contact hole, and the right alignment, which is the distance from the right end of the bar to the contact hole, to the right.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2A도 내지 제2C도는 본 발명의 실시예로 측정마크 형성공정을 도시한 단면도이다.2A to 2C are cross-sectional views showing a measurement mark forming process in an embodiment of the present invention.

제2A도는 소자의 셀부분에 하부층, 즉 소자분리막, 질화막, 다결정실리콘층, 실리사이드층 및 금속층을 형성할 때 반도체 기판의 스크라이브 라인(10) 상부에 상기의 하부층을 형성하는 물질 바아(bar)(1)를 형성한 것을 도시한 평면도이다. 여기서, 상기 바아(1)는 X축 방향의 측정마크를 형성하기 위하여 형성한 것이고, Y축 방향의 측정마크는 상기 X축방향의 측정마크를 90도 회전시킨 구조로 X축 방향 측정마크를 형성할 때 동시에 형성한다. 그리고, 제2A도는 하부층을 하나의 바아(1)로 도시하였지만 여러층을 적층한 바아의 구조로 하부층을 형성할 수 있다.2A shows a material bar for forming the lower layer above the scribe line 10 of a semiconductor substrate when forming a lower layer, that is, an isolation layer, a nitride film, a polysilicon layer, a silicide layer, and a metal layer in a cell portion of the device ( It is a top view which shows what formed 1). Here, the bar 1 is formed to form a measurement mark in the X-axis direction, the measurement mark in the Y-axis direction forms a measurement mark in the X-axis direction with a structure in which the measurement mark in the X-axis direction is rotated 90 degrees. When forming at the same time. In addition, although FIG. 2A illustrates the lower layer as one bar 1, the lower layer may be formed by a bar structure in which several layers are stacked.

제2B도는 상기 바아(1)의 상부에 정렬되게 콘택홀(3)을 형성한 것을 도시한 평면도이다.2B is a plan view showing that the contact holes 3 are formed to be aligned with the bar 1.

제2C도는 상기 측정마크를 씨디-샘(CD-SEM : Critical Dimension-Scanning Electron Microscope, 이하에서 CD-SEM이라 함)을 사용하여 거리에 따른 빛의 강도를 측정함으로써 측정신호를 형성한 것을 도시한 도면으로, 상기 측정신호를 피크(peak)파로 도시한 것이다. 여기서, 콘택홀의 X축방향 지름(X3)은 콘택홀(3)의 크기를 도시하며, 정렬도(△X)는 제1식과 같이 X1과 X2의 차이에 절대값을 한 것으로서, 수식으로 나타내면 다음과 같다.FIG. 2C shows that the measurement mark is formed by measuring the intensity of light with distance using a CD-SEM (Critical Dimension-Scanning Electron Microscope, hereinafter referred to as CD-SEM). In the drawings, the measurement signal is shown as a peak wave. Here, the X-axis diameter X 3 of the contact hole shows the size of the contact hole 3, and the alignment degree ΔX is the absolute value of the difference between X 1 and X 2 as in the first equation. It is as follows.

△X = ｜X1-X2｜ ------ (제1식)ΔX = ｜ X 1 -X 2 ｜ ------ (Formula 1)

상기 제1식에서 X1, X2은 각각 좌측 정렬도와 우측 정렬도를 도시한 것이다.In Formula 1 , X 1 and X 2 show left alignment and right alignment, respectively.

상기한 본 발명에 의하면, CD 선폭을 측정할 때 하층과의 정렬도를 동시에 측정 가능하여 별도의 측정장치가 필요없으며 측정시간도 절약되어 전체공정시간을 줄이고 생산성을 향상시킨다. 그리고, DRAM이나 SRAM 또는 로직(logic) 등 반도체소자에서 하층부와 콘택홀을 정렬도를 요구하는 부분에 적용할 수 있다.According to the present invention described above, when measuring the CD line width can be measured at the same time the alignment with the lower layer at the same time, there is no need for a separate measuring device and the measurement time is also saved to reduce the overall process time and improve the productivity. In addition, the lower layer and the contact hole may be applied to a portion requiring alignment degree in a semiconductor device such as DRAM, SRAM, or logic.

Claims (5)

측정마크 제조방법에 있어서, 셀부분에 형성되는 하부층을 스크라이브 라인 상부에 바아 형태로 형성하는 공정과, 상기 셀부분에 콘택홀을 형성할 때 상기 바아의 상부에 정렬되게 콘택홀을 형성하는 공정을 포함하는 측정마크 제조방법.A method of manufacturing a measurement mark, the method comprising: forming a bottom layer formed in a cell portion in a bar shape on an upper portion of a scribe line; and forming a contact hole aligned in an upper portion of the bar when forming a contact hole in the cell portion. Measuring mark manufacturing method comprising. 제1항에 있어서, 상기 하부층은 소자분리막, 질화막, 다결정실리콘층, 폴리사이드층 및 금속층을 말하는 것을 특징으로 하는 측정마크 제조방법.The method of claim 1, wherein the lower layer refers to a device isolation film, a nitride film, a polycrystalline silicon layer, a polyside layer, and a metal layer. 제1항에 있어서, 상기 바아는 여러개의 바아들, 즉 다수의 하부층을 중첩시켜 사용하는 것을 특징으로 하는 측정마크 제조방법.The method of claim 1, wherein the bar is formed by overlapping a plurality of bars, that is, a plurality of lower layers. 정렬도 측정방법에 있어서, 셀부에 형성되는 하부층과 같은 물질로 스크라이브 라인의 상부에 형성된 바아와 셀부의 콘택홀과 같이 상기 바아의 상부에 형성된 콘택홀이 중첩될 때 상기 바아의 왼쪽끝으로부터 왼쪽으로 콘택홀까지의 거리인 좌측정렬도와 상기 바아의 오른쪽끝에서부터 오른쪽으로 콘택홀까지의 거리인 우측정렬도의 차의 절대값을 정렬도로 하는 것을 특징으로 하는 정렬도 측정방법.In the alignment measurement method, a bar formed in the upper portion of the scribe line and a contact hole formed in the upper portion of the bar, such as a contact hole in the cell portion, overlapped with the same material as the lower layer formed in the cell portion from the left end of the bar to the left side. And an absolute value of the difference between the left alignment, the distance to the contact hole, and the right alignment, the distance from the right end of the bar to the contact hole, to the right. 제4항에 있어서, 상기 바아는 다수의 하부층을 중첩시켜 사용하는 것을 특징으로 하는 정렬도 측정방법.The method of claim 4, wherein the bar is formed by overlapping a plurality of lower layers.
KR1019940001950A 1994-02-03 1994-02-03 Mark fabrication and measurement method lfor alignment measurement KR970011655B1 (en)

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