KR950025944A - Measurement mark, its manufacturing method and alignment method - Google Patents

Measurement mark, its manufacturing method and alignment method Download PDF

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Publication number
KR950025944A
KR950025944A KR1019940001950A KR19940001950A KR950025944A KR 950025944 A KR950025944 A KR 950025944A KR 1019940001950 A KR1019940001950 A KR 1019940001950A KR 19940001950 A KR19940001950 A KR 19940001950A KR 950025944 A KR950025944 A KR 950025944A
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KR
South Korea
Prior art keywords
bar
contact hole
alignment
forming
manufacturing
Prior art date
Application number
KR1019940001950A
Other languages
Korean (ko)
Other versions
KR970011655B1 (en
Inventor
함영목
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940001950A priority Critical patent/KR970011655B1/en
Publication of KR950025944A publication Critical patent/KR950025944A/en
Application granted granted Critical
Publication of KR970011655B1 publication Critical patent/KR970011655B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 측정마크 및 그 제조방법과 정렬도 측정방법에 관한 것으로, 셀부분에 형성해야하는 여러층을 형성 할 때 스크라이브 라인의 상부에 같은 물질로 바아(bar) 형태를 형성한 후, 셀부분에 콘택홀을 형성할 때 상기 바아의 상부에 정렬되게 콘택홀을 형성함으로써 측정마크를 형성하고, 상기 바아와 콘택홀이 중첩될 때 상기 바아의 왼쪽끝에서부터 왼쪽으로 콘택홀까지의 거리, 즉 좌측정렬도와 상기 바아의 오른쪽에서부터 오른쪽으로 콘택홀까지의 거리인 우측정렬도의 차에 절대값을 하는 값을 정렬도로 하는 기술로서, 상기 콘택홀을 측정할 때 하층과의 정렬도를 동시에 측정할 수 있는 공정시간을 단축시킬 수 있어 소자의 생산성을 향상시키는 것이다.The present invention relates to a measuring mark, a method of manufacturing the same, and a method of measuring alignment, and when forming a plurality of layers to be formed in a cell part, a bar shape is formed of the same material on the upper part of the scribe line, and then When forming the contact hole, the measurement mark is formed by forming the contact hole aligned with the top of the bar, and when the bar and the contact hole overlap, the distance from the left end of the bar to the left contact hole, that is, left alignment Also, the degree of alignment value is a value that makes an absolute value to the difference between the right alignment degree, which is the distance from the right side of the bar to the right side of the bar, and when the contact hole is measured, the degree of alignment with the lower layer can be simultaneously measured. The process time can be shortened to improve the productivity of the device.

Description

측정마크 및 그 제조방법과 정렬도 측정방법Measurement mark, its manufacturing method and alignment method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 2C도는 본 발명의 실시예로 측정마크 형성공정 및 정렬도 측정방법을 도시한 단면.2A to 2C are cross-sectional views illustrating a measuring mark forming process and an alignment measuring method according to an embodiment of the present invention.

Claims (5)

측정마크 제조방법에 있어서, 셀부분에 형성되는 하부층을 스크라이브 라인 상부에 비아 형태로 형성하는 공정과, 상기 셀부분에 콘택홀을 형성할 때 상기 바아의 상부에 정렬되게 콘택홀을 형성하는 공정을 포함하는 측정마크 제조방법.A method of manufacturing a measurement mark, the method comprising: forming a bottom layer formed in a cell portion in a via shape on a scribe line, and forming a contact hole aligned with an upper part of the bar when forming a contact hole in the cell portion. Measuring mark manufacturing method comprising. 제1항에 있어서, 상기 하부층은 소자분리막, 질화막, 다결정실리콘층, 폴리사이드층 및 금속층을 말하는 것을 특징으로하는 측정마크 제조방법.The method of claim 1, wherein the lower layer refers to a device isolation film, a nitride film, a polycrystalline silicon layer, a polyside layer, and a metal layer. 제1항에 있어서, 상기바아는 여러개의 바아를, 즉 다수의 하부층을 중첩시켜 사용하는 것을 특징으로 하는 측정마크 제조방법.The method of claim 1, wherein the bar is formed by using a plurality of bars, that is, a plurality of bottom layers overlapping each other. 정렬도 측정방법에 있어서, 셀부에 형성되는 하부층과 같은 물질로 스크라이브 라인의 상부에 형성된 바아와 셀부의 콘택홀과 같이 상기 바아의 상부에 형성된 콘택홀이 중첩될 때 상기 바아의 왼쪽끝으로부터 왼쪽으로 콘택홀까지의 거리인 좌측정렬도와 상기 바아의 오른쪽끝에서부터 오른쪽으로 콘택홀까지의 거리인 우측정렬도의 차의 절대값을 정렬도로하는 것을 특징으로하는 정렬도 측정방법.In the alignment measurement method, a bar formed in the upper portion of the scribe line and a contact hole formed in the upper portion of the bar, such as a contact hole in the cell portion, overlapped with the same material as the lower layer formed in the cell portion from the left end of the bar to the left side. And an absolute value of the difference between the left alignment, the distance to the contact hole, and the right alignment, the distance from the right end of the bar to the contact hole, to the right. 제4항에 있어서, 상기 바아는 다수의 하부층을 중첩시켜 사용하는 것을 특징으로하는 정렬도 측정방법.The method of claim 4, wherein the bars are formed by overlapping a plurality of lower layers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940001950A 1994-02-03 1994-02-03 Mark fabrication and measurement method lfor alignment measurement KR970011655B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940001950A KR970011655B1 (en) 1994-02-03 1994-02-03 Mark fabrication and measurement method lfor alignment measurement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940001950A KR970011655B1 (en) 1994-02-03 1994-02-03 Mark fabrication and measurement method lfor alignment measurement

Publications (2)

Publication Number Publication Date
KR950025944A true KR950025944A (en) 1995-09-18
KR970011655B1 KR970011655B1 (en) 1997-07-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940001950A KR970011655B1 (en) 1994-02-03 1994-02-03 Mark fabrication and measurement method lfor alignment measurement

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Country Link
KR (1) KR970011655B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801075B1 (en) * 2006-01-27 2008-02-11 삼성전자주식회사 Method for enhancing yield of semiconductor integrate circuit device and system for the same using a hole's systematic fault rate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801075B1 (en) * 2006-01-27 2008-02-11 삼성전자주식회사 Method for enhancing yield of semiconductor integrate circuit device and system for the same using a hole's systematic fault rate

Also Published As

Publication number Publication date
KR970011655B1 (en) 1997-07-12

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