KR940027118A - Method of forming overlapping accuracy measurement mark of semiconductor device - Google Patents

Method of forming overlapping accuracy measurement mark of semiconductor device Download PDF

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Publication number
KR940027118A
KR940027118A KR1019930008674A KR930008674A KR940027118A KR 940027118 A KR940027118 A KR 940027118A KR 1019930008674 A KR1019930008674 A KR 1019930008674A KR 930008674 A KR930008674 A KR 930008674A KR 940027118 A KR940027118 A KR 940027118A
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KR
South Korea
Prior art keywords
forming
semiconductor device
film
layer
measurement mark
Prior art date
Application number
KR1019930008674A
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Korean (ko)
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KR100256265B1 (en
Inventor
임재남
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930008674A priority Critical patent/KR100256265B1/en
Publication of KR940027118A publication Critical patent/KR940027118A/en
Application granted granted Critical
Publication of KR100256265B1 publication Critical patent/KR100256265B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

본 발명은 반도체 소자의 패턴(pattern)의 중첩 정확도를 측정하기 위하여 박스 인 박스(box in box) 측정마크를 형성하는 반도체 소자의 중첩정확도 측정마크 형성 방법있어서, 하층막을 하층내막(2')과 하층외막(")의 이중형으로 동시에 형성하되 하층외막(2")을 상기 하층내막(2')과 매우 근접한 거이에서 형성하는 단계 ; 상기 하층내막(2')상에 상기 하층막 형성과 동일하게 상층내막(1')과 상층외막(1")으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 중첩정확도 측정마크 형성 방법에 관한 것으로, 보다 정확한 중첩정확도 측정으로 인하여 웨이퍼 얼라인을 향상시키므로써 반도체 소자의 신뢰도 및 수율향상을 가져오는 효과가 있다.The present invention provides a method for forming an overlap accuracy measurement mark of a semiconductor device for forming a box in box measurement mark to measure the overlap accuracy of a pattern of the semiconductor device. Simultaneously forming a double layer of a lower outer layer ("), but forming a lower outer layer (2") in close proximity to the lower inner layer (2 '); Forming the upper layer inner film 1 'and the upper layer outer film 1 "on the lower inner film 2' in the same manner as forming the lower layer film. In this regard, the wafer alignment is improved due to the more accurate measurement of overlapping accuracy, thereby improving the reliability and yield of the semiconductor device.

Description

반도체 소자의 중첩정확도 측정마크 형성 방법Method of forming overlapping accuracy measurement mark of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 중첩정확도를 측정하는 측정원리를 나타내는 단면도, 제3도는 본 발명에 따른 중첩정확도 측정마크인 박스 인 박스 평면도 및 단면도, 제4도는 본 발명에 따른 측정마크를 이용하여 중첩정확도를 측정하는 측정원리를 나타내는 단면도.2 is a cross-sectional view showing a measurement principle for measuring overlapping accuracy, and FIG. 3 is a box in box plan view and a cross-sectional view of the overlapping accuracy measuring mark according to the present invention, and FIG. 4 is a measurement for measuring overlapping accuracy using the measurement mark according to the present invention. Section showing the principle.

Claims (1)

반도체 소자의 패턴(pattern)의 중첩 정확도를 측정하기 위하여 박스 인 박스(box in box) 측정마크를 형성하는 반도체 소자의 중첩정확도 측정마크 형성 방법에 있어서, 하층막을 하층내막(2')과 하층외막(")의 이중형으로 동시에 형성하되 하층외막(2")을 상기 하층내막(2')과 매우 근접한 거리에서 형성하는 단계 ; 상기 하층내막(2')상에 상기 하층막 형성과 동일하게 상층내막(1')과 상층외막(1")으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 중첩정확도 측정마크 형성 방법.In the method of forming a superimposition accuracy measurement mark of a semiconductor device for forming a box in box measurement mark for measuring the accuracy of superimposition of a pattern of the semiconductor device, the lower layer film is composed of the lower inner film 2 'and the lower outer film. Forming a double layer (") at the same time but forming a lower outer film (2") at a distance very close to the lower inner film (2 '); Forming the upper layer inner film 1 'and the upper layer outer film 1 "on the lower inner film 2' in the same manner as forming the lower layer film. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930008674A 1993-05-20 1993-05-20 Method of manufacturing mark for measuring overlay accuracy KR100256265B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930008674A KR100256265B1 (en) 1993-05-20 1993-05-20 Method of manufacturing mark for measuring overlay accuracy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930008674A KR100256265B1 (en) 1993-05-20 1993-05-20 Method of manufacturing mark for measuring overlay accuracy

Publications (2)

Publication Number Publication Date
KR940027118A true KR940027118A (en) 1994-12-10
KR100256265B1 KR100256265B1 (en) 2000-05-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930008674A KR100256265B1 (en) 1993-05-20 1993-05-20 Method of manufacturing mark for measuring overlay accuracy

Country Status (1)

Country Link
KR (1) KR100256265B1 (en)

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Publication number Publication date
KR100256265B1 (en) 2000-05-15

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