KR950012598A - Overlap accuracy measurement method using measurement mark - Google Patents

Overlap accuracy measurement method using measurement mark Download PDF

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KR950012598A
KR950012598A KR1019930022682A KR930022682A KR950012598A KR 950012598 A KR950012598 A KR 950012598A KR 1019930022682 A KR1019930022682 A KR 1019930022682A KR 930022682 A KR930022682 A KR 930022682A KR 950012598 A KR950012598 A KR 950012598A
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South Korea
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measurement mark
measurement
intermediate layer
forming
mark
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KR1019930022682A
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Korean (ko)
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함영목
이철승
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김주용
현대전자산업 주식회사
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Priority to KR1019930022682A priority Critical patent/KR950012598A/en
Publication of KR950012598A publication Critical patent/KR950012598A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

반도체소자의 제조방법에서 하부층 상부에 리소그래피(lithography) 공정에 의해 상부층을 중첩시킬 때 측정마크를 이용한 패턴 중첩도를 측정하는 방법에 있어서, 패턴과 패턴사이의 중첩정확도를 정확하게 측정하고, 스크라이브 지역에 형성되는 측정마크의 갯수를 줄이기 위해 하부의 측정마크상에 여러층을 적층시켜 중첩정확도를 측정하는 기술이다.In the method of manufacturing a semiconductor device, a method of measuring pattern overlap using a measurement mark when superimposing an upper layer on a lower layer by a lithography process, accurately measuring overlapping accuracy between the pattern and the scribe area, In order to reduce the number of measurement marks formed, it is a technique of measuring overlapping accuracy by stacking several layers on the lower measurement marks.

Description

측정마크를 이용한 중첩정확도 측정방법Overlap accuracy measurement method using measurement mark

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 제1실시예에 의해 제조된 제1, 제2, 제3 측정마크를 도시한 평면도.3 is a plan view showing first, second and third measurement marks manufactured by the first embodiment of the present invention.

제4a도 내지 제4c도는 본 발명의 제1실시예에 의해 제1,제2,제3 측정마크를 제조하는 공정을 도시한 단면도.4A to 4C are cross-sectional views showing a process of manufacturing the first, second and third measurement marks according to the first embodiment of the present invention.

Claims (12)

측정마크를 이용한 중첩정확도 측정방법에 있어서, 하부층에 일정 깊이를 갖는 사각형 홈으로된 제1측정마크를 형성하는 단계와, 제1중간층상부에 제1측정마크의 내측에 제1감광막패턴으로된 박스형 제2측정마크를 형성하여 제1,제2 측정마크간의 중첩정확도를 측정하는 단계와, 제2측정마크를 마스크로 하여 노출된 제1중간층을 식각하여 제1중간층패턴을 형성한 후, 상기 제2측정마크를 제거하는 단계와, 제2중간층을 형성한 후, 그 상부에 제2측정마크와 중첩되는 제2감광막으로된 박스형 제3측정마크를 형성하여, 제1측정마크와 제3측정마크 또는 제2측정마크와 제3측정마크간의 중첩정확도를 측정하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.A method of measuring overlapping accuracy using measurement marks, the method comprising: forming a first measurement mark having a rectangular groove having a predetermined depth on a lower layer, and a box type having a first photoresist pattern on an inner side of the first measurement mark on the first intermediate layer. Forming a second measurement mark to measure the overlapping accuracy between the first and second measurement marks; and etching the exposed first intermediate layer using the second measurement mark as a mask to form a first intermediate layer pattern. Removing the second measurement mark, and after forming the second intermediate layer, forming a box-shaped third measurement mark made of a second photoresist film overlapping the second measurement mark on the upper portion thereof to form the first measurement mark and the third measurement mark Or measuring overlapping accuracy between the second measurement mark and the third measurement mark. 제1하엥 있어서, 상기 측정마크들을 반도체 기판의 스크라이브 라인 지역에 형성하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.The method of claim 1, wherein the measurement marks are formed in the scribe line region of the semiconductor substrate. 제1항에 있어서, 상기 측정마크들을 반도체 기판의 스크라이브 라인 지역에 다수개 형성하여 인트라필드 에러(intra-field-error)를 측정하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.2. The method of claim 1, wherein a plurality of measurement marks are formed in a scribe line region of a semiconductor substrate to measure intra-field-error. 제1항에 있어서, 상기 중간층은 절연층 또는 도전층으로 형성하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.The method of claim 1, wherein the intermediate layer is formed of an insulating layer or a conductive layer. 측정마크를 이용한 중첩정확도 측정방법에 있어서, 하부층의 예정된 부분에 사각형의 가장자리를 따라 필드산화막으로된 바아형 제1측정마크를 형성하고, 제1중간층을 형성하는 단계와, 상기 제1측정마크의 내측에 중첩되는 감광막패턴으로된 박스형 제2측정마크를 제1중간층 상부에 형성한 다음, 제1측정마크와 제2측정마크를 이용하여 중첩정확도를 측정하는 단계와, 상기 제2측정마크를 마스크로 하여 노출된 제1중간층을 식각하여 제1중간층패턴을 형성하는 단계와, 상기 제2측정마크를 제거한 다음, 제2중간층을 도포하고, 그 상부에 제1중간층패턴과 중첩되는 감광막 패턴으로된 박스형 제3측정마크를 형성하여 제1측정마크와 제3측정마크 또는 제1중간층패턴과 제3측정마크간의 중첩정확도를 측정하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.A method of measuring overlapping accuracy using measurement marks, the method comprising: forming a bar-shaped first measurement mark made of a field oxide film along a rectangular edge in a predetermined portion of a lower layer, and forming a first intermediate layer; Forming a box-shaped second measurement mark having a photoresist pattern overlapping the inside of the first intermediate layer, and then measuring overlapping accuracy using the first measurement mark and the second measurement mark, and masking the second measurement mark. Etching the exposed first intermediate layer to form a first intermediate layer pattern, removing the second measurement mark, applying a second intermediate layer, and forming a photoresist pattern on the upper portion of the first intermediate layer pattern. Forming a box-shaped third measurement mark to measure the overlapping accuracy between the first measurement mark and the third measurement mark or the first intermediate layer pattern and the third measurement mark Accuracy of measurement. 제5항에 있어서, 상기 측정마크들을 반도체 기판의 스크라이브라인지역에 형성하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.The method of claim 5, wherein the measurement marks are formed in a scribe region of the semiconductor substrate. 제5항에 있어서, 상기 측정마크들을 반도체 기판의 스크라이브 라인 지역에 다수개 형성하여 인트라필드 에러(intra-field-error)를 측정하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.6. The method of claim 5, wherein a plurality of measurement marks are formed in a scribe line region of a semiconductor substrate to measure intra-field-error. 제5항에 있어서, 상기 중간층은 절연층 및 도전층으로 적층하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.The method of claim 5, wherein the intermediate layer is laminated with an insulating layer and a conductive layer. 측정마크를 이용한 중첩정확도 측정방법에 있어서, 하부층의 예정된 부분에 사각형 사변 가장자리에 바아 형태의 필드산화막으로된 바아형 제1측정마크를 형성하고 그 상부에 제1중간층을 형성하는 단계와,제1중간층 상부에 제1감광막패턴을 형성하되, 제1측정마크 내측에 바아 형태로 감광막이 제거된 부분을 제2측정마크로 사용하여 제1측정마크와의 중첩정확도를 측정하는 단계와, 상기 제1감광막패턴을 마스크로 하여 노출된 제1중간층을 식각하여 제1중간층패턴을 형성한 다음, 상기 제1감광막패턴을 제거하는 단계와, 제2중간층을 형성하고 그 상부에 제2측정마크 중앙부와 중첩되는 제2감광막패턴으로된 박스형 제3측정마크를 형성하여 제1측정마크와 제3측정마크 또는 제1중간층패턴과 제3측정마크간의 중첩정확도를 측정하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.A method of measuring overlapping accuracy using a measurement mark, the method comprising: forming a bar-type first measurement mark formed of a bar oxide field oxide film at a predetermined edge of a quadrangle at a predetermined portion of a lower layer, and forming a first intermediate layer thereon; Forming a first photoresist pattern on the intermediate layer, and measuring overlapping accuracy with the first measurement mark by using a portion having the photoresist film removed in the form of a bar inside the first measurement mark as a second measurement mark; Etching the exposed first intermediate layer using a pattern as a mask to form a first intermediate layer pattern, and then removing the first photoresist pattern, forming a second intermediate layer and overlapping with a central portion of a second measurement mark thereon By forming a box-shaped third measurement mark made of the second photoresist pattern to measure the overlapping accuracy between the first measurement mark and the third measurement mark or the first intermediate layer pattern and the third measurement mark. The method of measuring overlapping accuracy using the measurement mark. 제9항에 있어서, 상기 측정마크들을 반도체 기판의 스크라이브 라인지역에 형성하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.10. The method of claim 9, wherein the measurement marks are formed in the scribe line region of the semiconductor substrate. 제10항에 있어서, 상기 측정마크들을 반도체 기판의 스크라이브라인 지역에 다수개 형성하여 인트라 필드 에러(intra-filed-error)를 측정하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.11. The method of claim 10, wherein a plurality of measurement marks are formed in a scribe region of a semiconductor substrate to measure intra-filed-error. 제9항에 있어서, 상기 제1중간층은 절연층 및 도전층으로 적층하는 것을 특징으로 하는 측정마크를 이용한 중첩정확도 측정방법.10. The method of claim 9, wherein the first intermediate layer is laminated with an insulating layer and a conductive layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930022682A 1993-10-29 1993-10-29 Overlap accuracy measurement method using measurement mark KR950012598A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990031404A (en) * 1997-10-10 1999-05-06 윤종용 How to measure misalignment between multiple layers
KR100474990B1 (en) * 1997-07-29 2005-05-27 삼성전자주식회사 Alignment Key of Semiconductor Device and Formation Method
KR100688487B1 (en) * 2001-02-02 2007-03-09 삼성전자주식회사 Method of forming overlay key and overlay key thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474990B1 (en) * 1997-07-29 2005-05-27 삼성전자주식회사 Alignment Key of Semiconductor Device and Formation Method
KR19990031404A (en) * 1997-10-10 1999-05-06 윤종용 How to measure misalignment between multiple layers
KR100688487B1 (en) * 2001-02-02 2007-03-09 삼성전자주식회사 Method of forming overlay key and overlay key thereof

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