KR20010008557A - Method For Forming The Pattern For Measuring The Height Of Trench Isolation Oxide Layer - Google Patents
Method For Forming The Pattern For Measuring The Height Of Trench Isolation Oxide Layer Download PDFInfo
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- KR20010008557A KR20010008557A KR1019990026464A KR19990026464A KR20010008557A KR 20010008557 A KR20010008557 A KR 20010008557A KR 1019990026464 A KR1019990026464 A KR 1019990026464A KR 19990026464 A KR19990026464 A KR 19990026464A KR 20010008557 A KR20010008557 A KR 20010008557A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
Description
본 발명은 소자분리막을 형성하는 방법에 관한 것으로서, 특히, 셀영역에 소자분리막을 형성하면서 동시에 스크라이브라인 영역에 일정한 가로 및 세로의 면적을 갖고, 일정한 간격을 갖는 소자분리막을 다수 구비하는 단차측정용패턴을 형성하여서 소자분리막을 형성한 후에 셀영역의 소자분리막을 단차를 용이하게 측정하도록 하는 소자분리막의 단차 측정용 패턴형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film, and more particularly, to form a device isolation film in a cell region, and at the same time, having a plurality of device separation films having a constant horizontal and vertical area in a scribe line region and having a predetermined interval. The present invention relates to a method for forming a step measurement of a step of a device isolation film to easily measure the step of the device separation film of a cell region after forming a pattern to form a device isolation film.
일반적으로, 반도체기판 상에 트랜지스터와 커패시터등을 형성하기 위하여 반도체기판에는 전기적으로 통전이 가능한 활성영역(Active Region)과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역(Isolation region)을 형성하게 된다.In general, in order to form transistors and capacitors on a semiconductor substrate, an isolation region is formed in the semiconductor substrate to prevent electrical conduction with an electrically energized active region and to separate devices from each other. Will form.
이와 같이, 반도체기판에 일정한 깊이를 갖는 트렌치(Trench)를 형성하고서 이 트렌치에 산화막을 증착시키고서 화학기계적연마공정(Chemical Mechanical Polishing)으로 이 산화막을 평탄화한 후 불필요한 부분인 질화막을 식각하므로서 소자분리영역을 반도체기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다.In this way, a trench having a predetermined depth is formed on the semiconductor substrate, an oxide film is deposited on the trench, and the oxide film is planarized by chemical mechanical polishing, followed by etching the nitride film, which is unnecessary. Recently, a shallow trench isolation (STI) process for forming a region on a semiconductor substrate has been used.
종래의 반도체장치에서 트렌치를 형성하여 소자분리막을 형성하는 상태를 개략적으로 설명하면, 반도체기판 상에 소정의 두께를 갖고서 상층의 질화막에 대하여 완충작용을 하도록 패드산화막을 적층하고, 그 위에 화학기계적연마공정의 스토핑 레이어(Stopping Layer) 역할을 하는 질화막을 적층하고서, 그위에 감광막을 도포하여서 식각공정을 통하여 트렌치를 형성한다.In the semiconductor device according to the related art, a trench is formed to form a device isolation film. A pad oxide film is laminated on the semiconductor substrate with a predetermined thickness to buffer the upper nitride film, and chemical mechanical polishing is formed thereon. A nitride film serving as a stopping layer of the process is laminated, and a photoresist is applied thereon to form a trench through an etching process.
그리고, 이 트렌치가 형성된 부분에 전계효과(Field Effect) 집중으로 인한 누설 전류를 방지하기 위하여 트렌치의 내벽면을 산화 성장시켜 트렌치산화막을 형성한 후 소자분리막의 측면부분에 발생되는 모트(Moat)를 방지하기 위하여 라이너산화막(Liner Oxidation)의 트렌치의 내벽면에 재차 형성하도록 한다.Then, in order to prevent leakage current due to the concentration of field effects in the trench, the trench is formed by oxidizing and growing the inner wall of the trench to form a trench oxide film. In order to prevent this, it is formed again on the inner wall surface of the trench of the liner oxide film.
그리고, 연속하여 상기 트렌치내에 갭필링(Gap Filling)공정으로 캡필링산화막을 충진시킨 후에 식각으로 질화막등을 제거하여 소자분리막을 형성하게 되는 것이다.Subsequently, after the capfill oxide film is filled in the trench by a gap filling process, the nitride film is removed by etching to form an isolation layer.
이와 같은 방법을 통하여 반도체기판 상에 소자분리막을 형성한 후 소자부늬막의 단차가 적절하게 형성되었는 지 여부를 판단하기 위하여 소자분리막의 단차를 측정하도록 하였다.After the device isolation film was formed on the semiconductor substrate through the above method, the step difference of the device isolation film was measured to determine whether the step difference between the device spacer film was properly formed.
이때, 소자분리막의 단차를 측정하는 방법에는 SEM사진을 촬영하여 나타난 반도체기판의 단면에서 소자분리막의 단차를 측정하는 방법과, CD-AFM 장비를 사용하여 반도체기판의 소자분리영역과 액티브영역의 을 스캔하여 패턴의 프로파일 (Profile)을 나타내어서 소자분리막의 단차를 측정하는 방법이 있다.At this time, the method of measuring the step difference of the device isolation film is a method of measuring the step of the device isolation film in the cross section of the semiconductor substrate taken by SEM photographs, and using the CD-AFM equipment of the device isolation region and the active area of the. There is a method of measuring the level of the device isolation layer by scanning the profile of the pattern.
그런데, 상기한 소자분리막의 단차를 측정하는 방법중에서 SEM분석을 통한 측정방법은 소자분리막을 형성한 후에 후속공정으로 질화막을 적층하여야 하는 단점을 지니고 있으며, SEM분석용으로 사용되는 시료로 채택되는 웨이퍼를 손상하여야 하며, 소자분리막의 단차가 정확하지 않으며, 분석시간이 많이 소요되는 문제점을 지니고 있었다.However, in the method for measuring the step difference of the device isolation film, the measurement method through SEM analysis has a disadvantage in that a nitride film is laminated in a subsequent process after forming the device isolation film, and the wafer used as a sample used for SEM analysis And the step of the device isolation layer is not accurate, and it takes a long time to analyze.
한편, 상기한 CD-AFM을 이용한 측정방법은 소자분리막의 패턴 사이의 간격이 별차이점이 없을 경우 모니터링에 스캔된 화면만으로는 소자분리막이 반도체기판에서 올라와 있는 지 내려가 있는 지를 파악하는 것이 불가능하므로 CD-AFM을 이용한 측정방법을 적절하게 적용하지 못하는 문제점이 있었다.On the other hand, in the measurement method using the CD-AFM described above, if there is no difference between the patterns of the device isolation layer, it is impossible to determine whether the device isolation layer is raised or lowered from the semiconductor substrate by using only the screen scanned for monitoring. There was a problem that the AFM measurement method is not properly applied.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 셀영역에 소자분리막을 형성하면서 동시에 스크라이브라인 영역에 일정한 가로 및 세로의 면적을 갖고, 일정한 간격을 갖는 소자분리막을 다수 구비하는 단차측정용패턴을 형성하여서 소자분리막의 단차를 용이하게 측정하도록 하는 것이 목적이다.The present invention has been made in view of the above, and forms a device isolation film in the cell region, and at the same time forms a step measurement pattern having a plurality of device isolation films having a constant horizontal and vertical area in the scribe brain region and having a predetermined interval. It is an object to easily measure the level difference of the device isolation film.
도 1 내지 도 4는 본 발명에 따른 소자분리막을 형성하면서 스크라이브라인 영역에 단차측정용 패턴을 형성하는 방법을 순차적으로 보인 도면이고,1 to 4 are views sequentially showing a method for forming a step measurement pattern in the scribe brain region while forming the device isolation film according to the present invention,
도 5는 본 발명에 따른 스크라이브라인 영역에 소자분리막을 이용한 단차 측정용 패턴을 형성한 평면 상태를 도시한 도면이고,5 is a view showing a planar state in which a step measuring pattern using a device isolation film is formed in a scribe brain region according to the present invention;
도 6은 본 발명에 따른 단차측정용 패턴을 스캔한 상태의 프로파일을 보인 도면이다.6 is a view showing a profile of a state of scanning the step measurement pattern according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체기판 20 : 패드산화막10: semiconductor substrate 20: pad oxide film
25 : 질화막 35 : 패턴25 nitride film 35 pattern
40 : 트렌치 50 : 갭필링산화막40: trench 50: gap peeling oxide film
55 : 소자분리막 60 : 소자분리막 스캔프로파일55: device isolation layer 60: device isolation film scan profile
70 : 액티브지역 스캔프로파일 A : 단차측정용 패턴70: active area scan profile A: pattern for step measurement
본 발명의 목적은 셀영역의 반도체기판 상에 패드산화막과 질화막을 적층한 후 마스킹식각하여서 트렌치를 형성하고, 이 트렌치내에 갭필링산화막을 적층하여 연마공정으로 소자분리막을 형성하는 반도체소자의 소자분리막 형성방법에서, 상기 셀영역에 소자분리막을 형성할 때, 동시에 스크라이브라인영역의 반도체기판 상에 일정한 가로 및 세로의 길이를 갖는 소자분리막을 일정한 간격으로 배열시킨 단차측정용패턴을 다수 형성하여 CD-AFM장비로 소자분리막의 단차를 측정하도록 하는 반도체소자의 단차 측정용 패턴 형성방법을 제공함으로써 달성된다.An object isolation film of a semiconductor device is to form a trench by stacking a pad oxide film and a nitride film on a semiconductor substrate in a cell region, masking etching, and stacking a gap peeling oxide film in the trench to form a device isolation film by a polishing process. In the forming method, when the device isolation film is formed in the cell region, a plurality of stepped measurement patterns in which a plurality of device isolation films having a constant horizontal and vertical length are arranged at regular intervals are simultaneously formed on the semiconductor substrate of the scribe line region. It is achieved by providing a method for forming a step measurement step of a semiconductor device to measure the step difference of the device isolation film by AFM equipment.
그리고, 상기 단차 측정용 패턴은 가로 및 세로의 길이가 각각 1.5㎛ × 80㎛ 로 형성하도록 하고, 상기 단차측정용패턴의 간격은 0.3 ∼ 0.7㎛ 인 것이 바람직하다.In addition, the step measurement pattern is preferably formed to have a length of 1.5 μm × 80 μm in length and width, respectively, and the interval of the step measurement pattern is preferably 0.3 to 0.7 μm.
상기 단차측정용 패턴을 45개 이상 형성하여, 단차측정용 패턴 면적 및 그 사이의 면적을 포함한 전체 면적을 80㎛ × 80㎛ 이상으로 형성하도록 한다.45 or more of the step measurement patterns are formed so that the total area including the step measurement pattern area and the area therebetween is formed to be 80 μm × 80 μm or more.
이하, 본 발명에 따른 단차측정용 패턴 형성방법을 일실시예에 의거하여 상세하게 살펴 보도록 한다.Hereinafter, a method for forming a step measurement pattern according to the present invention will be described in detail based on an embodiment.
도 1 내지 도 4는 본 발명에 따른 소자분리막을 형성하면서 스크라이브라인 영역에 단차측정용 패턴을 형성하는 방법을 순차적으로 보인 도면이고, 도 5는 본 발명에 따른 스크라이브라인 영역에 소자분리막을 이용한 단차 측정용 패턴을 형성한 평면 상태를 도시한 도면이며, 도 6은 본 발명에 따른 단차측정용 패턴을 스캔한 상태의 프로파일을 보인 도면이다.1 to 4 are views sequentially showing a method for forming a step measurement pattern in the scribe brain region while forming the device isolation film according to the present invention, Figure 5 is a step using a device isolation film in the scribe brain region according to the present invention FIG. 6 is a view showing a planar state in which a measurement pattern is formed, and FIG. 6 is a view showing a profile of a state in which a step measurement pattern is scanned according to the present invention.
먼저, 셀영역과 스크라이브라인영역에 소자분리막을 형성하는 상태를 순차적으로 살펴 보도록 한다. 도 1은 셀영역과 스크라이브라인 영역의 반도체기판(10)의 상부면에 패드산화막(20)과 질화막(25)을 형성한 상태를 도시하고 있다.First, the state in which the device isolation film is formed in the cell region and the scribe brain region will be described sequentially. FIG. 1 illustrates a state in which a pad oxide film 20 and a nitride film 25 are formed on an upper surface of a semiconductor substrate 10 in a cell region and a scribe line region.
도 2는 반도체기판(10)에서 소자분리막이 형성될 부위에 패턴(35)을 갖도록 감광막(30)을 적층하여서 패턴(35)을 형성시킨 상태를 도시하고 있으며, 스크라이브라인영역에서는 비교적 패턴(35)이 넓도록 형성한다.FIG. 2 illustrates a state in which a pattern 35 is formed by stacking the photoresist layer 30 so as to have a pattern 35 on a portion where a device isolation film is to be formed in the semiconductor substrate 10. ) To be wider.
도 3은 상기 간광막(30)의 패턴을 통하여 반도체기판(10)의 일정 깊이까지 식각되는 트렌치(40)를 형성하여서 갭필링산화막(50)을 트렌치(40)내에 매립하는 상태를 도시하고 있다.3 illustrates a state in which the gap filling oxide film 50 is buried in the trench 40 by forming the trench 40 which is etched to a predetermined depth of the semiconductor substrate 10 through the pattern of the interlayer film 30. .
도 4는 상기 갭필링산화막(50)을 화학기계적연마공정(Chemical Mechanical Polishing)으로 평탄화시킨 후에 잔류된 나머지부분을 식각하여 소자분리막(55)을형성하도록 한다.4 is a planarization of the gap peeling oxide film 50 by chemical mechanical polishing (Chemical Mechanical Polishing) to etch the remaining portion to form a device isolation film 55.
이때, 도 5에 도시된 바와 같이, 반도체기판(10)에 소자분리막(55)을 형성한 후 스크라이브라인영역을 평면 상태로 본 도면으로서, 스크라이브라인 영역에 형성된 소자분리막(55)으로 된 상기 단차 측정용 패턴(A)은 가로(a) 및 세로(b)의 길이가 각각 1.5㎛ × 80㎛ 정도로 형성하는 것이 바람직하다.In this case, as shown in FIG. 5, after the device isolation film 55 is formed on the semiconductor substrate 10, the scribe brain region is viewed in a plan state, and the step of the device isolation film 55 formed in the scribe brain region is shown. It is preferable to form the measurement pattern A about 1.5 micrometer x 80 micrometers in length of the width | variety (a) and the length (b), respectively.
그리고, 상기 단차측정용패턴의 간격은 0.3 ∼ 0.7㎛ 정도로 형성하도록 하고, 상기 단차 측정용 패턴은 가로 및 세로의 길이가 각각 1.5㎛ × 80㎛ 정도로 형성하는 것이 바람직하고, 전체적으로 형성되는 갯수는 45개 이상 형성하는 것이 바람직하다.In addition, it is preferable that the interval of the step measurement pattern is formed to be about 0.3 to 0.7 μm, and the step measurement pattern is preferably formed to have a length of about 1.5 μm × 80 μm in length and width, respectively. It is preferable to form more than two pieces.
한편, 도 5에서 액티브지역(15)으로 표시된 단차 측정용패턴(A) 사이의 간격을 0.3㎛이하로 하지 못하는 이유는 CD-AFM장비가 어떤 부분을 스캔하여 정확한 프로파일(Profile)을 할 수 있는 간격이 0.3㎛이상 이기 때문이다.On the other hand, the reason why the gap between the step difference measurement pattern (A) indicated by the active region 15 in Fig. 5 or less than 0.3㎛ is because the CD-AFM equipment can scan a portion to have an accurate profile (Profile) This is because the interval is 0.3 占 퐉 or more.
이와 같이, 스크라이브라인영역에 있는 소자분리막(55)과 액티브지역(15)의 거리 비율이 5 : 1 정도 이므로 도 6에서와 같이, CD-AFM장비로 소자분리막(55)의 스캔 프로파일(60)이 함몰된 상태로 표시된다.As such, since the distance ratio between the device isolation layer 55 and the active region 15 in the scribe brain region is about 5: 1, as shown in FIG. 6, the scan profile 60 of the device isolation layer 55 is performed by the CD-AFM device. Is shown in a recessed state.
그러므로, 그에 인접한 액티브지역의 스캔프로파일(70) 역시 함몰되어 표시되더라도, 소자분리막(15)의 폭(a)과 액티브지역(15)의 폭(b)이 확연하게 차이가 나므로 소자분리막(55)의 단차를 용이하게 측정할 수 있다.Therefore, even if the scan profile 70 of the active region adjacent thereto is also recessed and displayed, since the width a of the device isolation layer 15 and the width b of the active region 15 are clearly different, the device isolation layer 55 The step difference can be easily measured.
즉, 스크라이브라인영역(특히, 테스트패턴지역)에 형성한 소자분리막(55)의 단차를 용이하게 측정하므로 그와 동시에 동일한 조건으로 형성된 셀영역의 소자분리막의 단차를 용이하게 알 수 있는 것이다.That is, since the step of the device isolation film 55 formed in the scribe brain region (especially the test pattern area) is easily measured, the step of the device isolation film of the cell region formed under the same conditions can be easily known.
따라서, 상기한 바와 같이, 본 고안에 따른 소자분리막의 단차 측정용 패턴형성방법을 이용하게 되면, 셀영역에 소자분리막을 형성하면서 동시에 스크라이브라인 영역에 일정한 가로 및 세로의 면적을 갖고, 일정한 간격을 갖는 소자분리막을 다수 구비하는 단차측정용패턴을 형성하여서 소자분리막을 형성한 후에 셀영역의 소자분리막의 단차를 인 라인(In-Line)에서 용이하게 측정하므로 웨이퍼의 손실을 줄여주고 생산성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the pattern forming method for measuring the step difference of the device isolation film according to the present invention is used, the device isolation film is formed in the cell region, and at the same time, it has a constant horizontal and vertical area in the scribe brain region, and has a constant interval. After forming the device isolation layer by forming a step measurement pattern including a plurality of device isolation layers, the step difference of the device isolation layer in the cell region can be easily measured in-line, thereby reducing wafer loss and improving productivity. It is a very useful and effective invention.
또한, 소자분리막의 단차 측정을 위한 최적의 패턴을 형성하므로 측정된 단차의 값을 신뢰할 수 있을 뿐만 아니라 분석의뢰시간을 줄여주도록 하는 장점을 지닌다.In addition, since the optimum pattern for measuring the step difference of the device isolation layer is formed, it is not only reliable to measure the value of the step difference but also has an advantage of reducing the analysis request time.
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| KR1019990026464A KR20010008557A (en) | 1999-07-02 | 1999-07-02 | Method For Forming The Pattern For Measuring The Height Of Trench Isolation Oxide Layer |
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| KR1019990026464A KR20010008557A (en) | 1999-07-02 | 1999-07-02 | Method For Forming The Pattern For Measuring The Height Of Trench Isolation Oxide Layer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100668742B1 (en) * | 2005-11-25 | 2007-01-29 | 주식회사 하이닉스반도체 | Method of measuring the critical dimension of trench for sphere-typed recess channel |
| KR100835482B1 (en) * | 2007-05-11 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Semiconductor device topology measuring method using atomic force microscope |
| CN110767572A (en) * | 2018-07-27 | 2020-02-07 | 无锡华润上华科技有限公司 | Method for monitoring step height of junction region of active region and isolation structure |
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1999
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100668742B1 (en) * | 2005-11-25 | 2007-01-29 | 주식회사 하이닉스반도체 | Method of measuring the critical dimension of trench for sphere-typed recess channel |
| KR100835482B1 (en) * | 2007-05-11 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Semiconductor device topology measuring method using atomic force microscope |
| CN110767572A (en) * | 2018-07-27 | 2020-02-07 | 无锡华润上华科技有限公司 | Method for monitoring step height of junction region of active region and isolation structure |
| CN110767572B (en) * | 2018-07-27 | 2021-11-05 | 无锡华润上华科技有限公司 | Method for monitoring step height of junction region of active region and isolation structure |
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