KR20010038378A - Method for forming align mark of semiconductor wafer - Google Patents

Method for forming align mark of semiconductor wafer Download PDF

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Publication number
KR20010038378A
KR20010038378A KR1019990046335A KR19990046335A KR20010038378A KR 20010038378 A KR20010038378 A KR 20010038378A KR 1019990046335 A KR1019990046335 A KR 1019990046335A KR 19990046335 A KR19990046335 A KR 19990046335A KR 20010038378 A KR20010038378 A KR 20010038378A
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South Korea
Prior art keywords
alignment mark
deposited layer
layer
alignment
laminated film
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KR1019990046335A
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Korean (ko)
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KR100587035B1 (en
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홍종균
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박종섭
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

PURPOSE: An alignment mark forming method is to improve an accuracy of planarization by reducing an alignment error caused by an over-polishing occurred in the planarization of a structure on which many layers are deposited. CONSTITUTION: The first deposited layer(12) is formed on a semiconductor substrate(11). The first deposited layer is required for fabricating a semiconductor device on a main cell region. An insulating layer such as an oxide layer or a nitride layer or a conductive layer such as a polysilicon is preferably formed as the first deposited layer. After a part of the first deposited layer is etched to be spaced with a distance, it is filled with a material to be used as an alignment mark(13) and is planarized to form many alignment marks. Then, the second deposited layer(14) is formed on the first deposited layer and selectively etched to expose the alignment mark. The second deposited layer is also required for fabricating the semiconductor device on the main cell region as the first deposited layer. Then, the third deposited layer(15) is formed on entire surface of a structure having an exposed alignment mark. The alignment mark is formed in the first process and is exposed in the second process. The planarization is progressed in the third process.

Description

반도체 웨이퍼의 정렬마크 형성방법{METHOD FOR FORMING ALIGN MARK OF SEMICONDUCTOR WAFER}METHODS FOR FORMING ALIGN MARK OF SEMICONDUCTOR WAFER}

본 발명은 반도체 웨이퍼의 정렬마크 형성방법에 관한 것으로, 특히 소자제조에 따라 다수의 층이 적층되는 구조물에 대한 평탄화기술의 과도연마(over-polishing)에 따른 정렬오류를 감소시켜 정밀도를 향상시키기에 적당하도록 한 반도체 웨이퍼의 정렬마크 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an alignment mark of a semiconductor wafer, and in particular, to improve accuracy by reducing alignment error due to over-polishing of a planarization technique for a structure in which a plurality of layers are stacked according to device manufacturing. The present invention relates to a method of forming an alignment mark of a semiconductor wafer so as to be suitable.

일반적으로, 반도체소자의 제조를 위해서는 다수의 패턴 형성이 요구되고, 패턴이 형성되는 공정 사이에 패턴의 정렬을 위한 마크가 사용된다.In general, the manufacture of a semiconductor device requires the formation of a plurality of patterns, and marks for alignment of the patterns are used between the processes in which the patterns are formed.

이와같은 정렬마크와 측정방법은 노광장치의 제조회사에 따라 상이하다.Such alignment marks and measuring methods differ depending on the manufacturer of the exposure apparatus.

첨부된 도1은 캐논사의 웨이퍼 정렬마크(20P-4F) 모양 및 크기를 도시한 것으로, 6개의 바(bar) 마크 중에 안쪽에 형성된 4개의 측정결과를 사용한다.The attached Figure 1 shows the shape and size of Canon's wafer alignment mark 20P-4F, which uses four measurement results formed inside of six bar marks.

즉, 상기 도1의 정렬마크로 부터 TV IMAGE PROCESSING을 이용하면 마크의 밝은 부분 정도에 따라 신호의 세기가 결정되고, 그 신호의 피크(peak)가 도2의 신호파형도와 같이 나타나므로, 4개 피크를 평균하여 전체 정렬마크의 중심을 검출할 수 있게 된다.That is, when TV IMAGE PROCESSING is used from the alignment mark of FIG. 1, the signal intensity is determined according to the degree of bright part of the mark, and the peak of the signal is shown as the signal waveform of FIG. By averaging the center of the whole alignment mark can be detected.

따라서, 이전에 진행된 공정에서 정렬마크를 형성한 다음 이후 공정에서 정렬마크를 검출하여 좌표의 기준점으로 사용하게 되면 이전 공정에 정렬되어 다음 공정을 진행 할 수 있게 된다.Therefore, if the alignment mark is formed in the previous process and then the alignment mark is detected in the subsequent process and used as a reference point of the coordinates, the alignment process may be aligned with the previous process to proceed to the next process.

그러나, 상기한 바와같은 종래 반도체 웨이퍼의 정렬마크 형성방법은 도3a 및 도3b에 도시한 바와같이 정렬마크(2)가 반도체기판(1)의 패턴 밀집도가 낮은 영역에 형성됨에 따라 메인 셀이 형성되는 영역을 타겟으로 하는 과도연마로 인해 정렬마크의 프로파일(profile)이 열화되어 측정 재현성 및 정확성이 감소하는 문제점이 있었다.However, in the method of forming the alignment mark of the conventional semiconductor wafer as described above, as shown in FIGS. 3A and 3B, the main cell is formed as the alignment mark 2 is formed in the region where the pattern density of the semiconductor substrate 1 is low. Due to the overpolishing of the target area, the profile of the alignment mark is degraded, thereby reducing the measurement reproducibility and accuracy.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 다수의 층이 적층되는 구조물에 대한 평탄화기술의 과도연마에 따른 정렬오류를 감소시켜 정밀도를 향상시킬 수 있는 반도체 웨이퍼의 정렬마크 형성방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, an object of the present invention is to improve the accuracy by reducing the alignment error due to the over-polishing of the planarization technology for a structure in which a plurality of layers are laminated The present invention provides a method for forming an alignment mark of a semiconductor wafer.

도1은 캐논사의 웨이퍼 정렬마크를 보인 예시도.1 is an exemplary view showing a wafer alignment mark of Canon Corporation.

도2는 도1의 TV IMAGE PROCESSING에 따른 신호파형도.2 is a signal waveform diagram according to TV IMAGE PROCESSING of FIG.

도3a 및 도3b는 종래의 문제점을 보인 예시도.Figures 3a and 3b is an exemplary view showing a conventional problem.

도4는 본 발명의 일 실시예를 보인 예시도.Figure 4 is an exemplary view showing an embodiment of the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

11:반도체기판 12:제1적층막11: semiconductor substrate 12: first laminated film

13:정렬마크 14:제2적층막13: alignment mark 14: the second laminated film

15:제3적층막15: the third laminated film

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체 웨이퍼의 정렬마크 형성방법은 반도체기판의 상부에 제1적층막을 형성하는 공정과; 상기 제1적층막의 일부를 일정한 거리 이격되도록 식각한 다음 정렬마크 물질을 채워서 다수의 정렬마크를 형성하는 공정과; 상기 정렬마크가 형성된 제1적층막의 상부전면에 제2적층막을 형성한 다음 상기 정렬마크가 노출되도록 식각하는 공정과; 상기 정렬마크가 노출된 구조물의 상부전면에 제3적층막을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.The method of forming an alignment mark of a semiconductor wafer for achieving the object of the present invention as described above comprises the steps of: forming a first laminated film on top of the semiconductor substrate; Etching a portion of the first laminated film to be spaced at a predetermined distance, and then filling the alignment mark material to form a plurality of alignment marks; Forming a second laminated film on an upper surface of the first laminated film on which the alignment mark is formed, and then etching the exposed alignment mark; And forming a third laminated film on the upper surface of the structure in which the alignment mark is exposed.

상기한 바와같은 본 발명에 의한 반도체 웨이퍼의 정렬마크 형성방법을 도4의 단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The method for forming an alignment mark of a semiconductor wafer according to the present invention as described above will be described in detail with reference to the cross-sectional view of FIG. 4 as an embodiment.

먼저, 반도체기판(11)의 상부에 제1적층막(12)을 형성한다. 이때, 제1적층막은 메인셀 영역에 반도체소자를 제조하기 위해 요구되는 막으로 통상적으로 산화막이나 질화막등의 절연막이나 폴리실리콘과 같은 도전성막이 형성된다.First, the first stacked film 12 is formed on the semiconductor substrate 11. At this time, the first laminated film is a film required for manufacturing a semiconductor device in the main cell region, and an insulating film such as an oxide film or a nitride film or a conductive film such as polysilicon is usually formed.

그리고, 상기 제1적층막(12)의 일부를 일정한 거리 이격되도록 식각한 다음 정렬마크로 사용될 물질을 채우고, 평탄화하여 다수개의 정렬마크(13)를 형성한다.A portion of the first laminated film 12 is etched to be spaced apart by a predetermined distance, and then a material to be used as an alignment mark is filled and planarized to form a plurality of alignment marks 13.

그리고, 상기 정렬마크(13)가 형성된 제1적층막(12)의 상부에 제2적층막(14)을 형성한 다음 상기 정렬마크(13)가 노출되도록 선택적으로 식각한다. 이때, 제2적층막(14)은 상기 제1적층막(12)과 마찬가지로 메인셀 영역에 반도체소자를 제조하기 위해 요구되는 막이다.Then, the second laminated film 14 is formed on the first laminated film 12 on which the alignment mark 13 is formed, and then selectively etched to expose the alignment mark 13. At this time, the second laminated film 14 is a film required for manufacturing a semiconductor device in the main cell region similarly to the first laminated film 12.

그리고, 상기 정렬마크(13)가 노출된 구조물의 상부전면에 제3적층막(15)을 형성하며, 도면에 도시하지는 않았지만 이후에 메인셀 영역에 반도체소자 제조에 요구되는 제3적층막(15)의 평탄화가 진행된다.In addition, a third laminated film 15 is formed on the upper surface of the structure where the alignment mark 13 is exposed, and although not shown in the drawing, a third laminated film 15 required for manufacturing a semiconductor device in a main cell region thereafter. ) Is planarized.

따라서, 반도체소자의 제조를 위해 임의로 제1공정에서 제3공정이 진행된다고 가정하면, 먼저 제1공정에서 정렬마크(13)를 형성하고, 제2공정은 상기 정렬마크(13)를 통해 정렬되며, 제2공정에서 정렬마크(13)를 노출시키게 되면, 제3공정에서도 제1공정에서 형성된 정렬마크(13)를 통해 정렬되며, 제3공정에서 평탄화가 진행된다.Therefore, assuming that the third process is performed in the first step arbitrarily for the manufacture of the semiconductor device, first, the alignment mark 13 is formed in the first process, and the second process is aligned through the alignment mark 13. When the alignment mark 13 is exposed in the second process, the alignment mark 13 is also aligned through the alignment mark 13 formed in the first process in the third process, and the planarization is performed in the third process.

상기한 바와같은 본 발명에 의한 반도체 웨이퍼의 정렬마크 형성방법은 종래에 비해 표면으로부터 정렬마크까지의 단차가 현저하게 증가하여 정렬마크에 대한 대조(contrast)가 증가하며, 후속 제3적층막의 평탄화공정이 진행되더라도 충분한 과도연마 여유도를 확보하여 정렬마크의 열화를 방지할 수 있게 됨에 따라 정렬정확도를 향상시킬 수 있는 효과가 있다.As described above, in the method of forming the alignment mark of the semiconductor wafer according to the present invention, the level difference from the surface to the alignment mark is significantly increased compared to the conventional method, and the contrast to the alignment mark is increased, and the subsequent planarization process of the third laminated film is performed. Even if this progresses, sufficient overpolishing margin can be secured to prevent deterioration of the alignment mark, thereby improving the alignment accuracy.

Claims (1)

반도체기판의 상부에 제1적층막을 형성하는 공정과; 상기 제1적층막의 일부를 일정한 거리 이격되도록 식각한 다음 정렬마크 물질을 채워서 다수의 정렬마크를 형성하는 공정과; 상기 정렬마크가 형성된 제1적층막의 상부전면에 제2적층막을 형성한 다음 상기 정렬마크가 노출되도록 식각하는 공정과; 상기 정렬마크가 노출된 구조물의 상부전면에 제3적층막을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 하는 반도체 웨이퍼의 정렬마크 형성방법.Forming a first laminated film on the semiconductor substrate; Etching a portion of the first laminated film to be spaced at a predetermined distance, and then filling the alignment mark material to form a plurality of alignment marks; Forming a second laminated film on an upper surface of the first laminated film on which the alignment mark is formed, and then etching the exposed alignment mark; And forming a third laminated film on the upper surface of the structure in which the alignment mark is exposed.
KR1019990046335A 1999-10-25 1999-10-25 Method for forming align mark of semiconductor wafer KR100587035B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313909B1 (en) * 2010-12-13 2013-10-01 에베 그룹 에. 탈너 게엠베하 Apparatus, device and method for determining alignment errors

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US7550379B2 (en) * 2006-10-10 2009-06-23 Asml Netherlands B.V. Alignment mark, use of a hard mask material, and method

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JPH01152723A (en) * 1987-12-10 1989-06-15 Seiko Epson Corp Manufacture of semiconductor device
JP3402874B2 (en) * 1995-09-28 2003-05-06 シャープ株式会社 Semiconductor device
KR0165353B1 (en) * 1995-12-14 1999-02-01 김광호 Forming alignment key pattern in semiconductor apparatus
KR19990006078A (en) * 1997-06-30 1999-01-25 김영환 Method of forming overlay measurement mark of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313909B1 (en) * 2010-12-13 2013-10-01 에베 그룹 에. 탈너 게엠베하 Apparatus, device and method for determining alignment errors

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