KR970011587B1 - Circuit for detecting the frame sync. of multiplexed analog component system - Google Patents

Abstract

The frame synchronization detecting circuit in a MAC(Multiplexed Analog Component) system comprises a first frame synchronization detector(10) connected to a MAC signal inputting terminal(MACI), for detecting a line synchronization of a MAC signal and also a frame synchronization; a second frame synchronization detector(20) connected to the MAC signal inputting terminal and detecting the frame synchronization by using the frame synchronization of the inputted MAC signal; and a frame synchronization discriminator(30) connected with the first and second frame synchronization detectors(10)(20) and discriminating the signal inputted from the MAC signal inputting terminal(AMCI) as the frame synchronization in detecting the frame synchronization in the first and second frame synchronization detectors(10)(20), whereby resulting in more efficient detection of the frame synchronization by detecting a line synchronization word in case the frame synchronization word is not detected.

Description

Frame Sync Detection Circuit of MAC System

1 is a frame sync detection circuit diagram of a conventional MAC system.

2 is a circuit diagram showing one embodiment of a frame sync detection circuit of a MAC system according to the present invention;

3 is a detailed circuit diagram of the pulse number detector of FIG.

* Explanation of symbols for main parts of the drawings

1, 11: W1 detector 12: W2 detector

2, 13, 14: 1H delay 3, 5: error detector

4, 15, 16: 12H delay 10, 20: 1st, 2nd frame sync detector

21: virtual frame sync generating unit 22: frame sync word error detection unit

23: number of pulse detector 24: pulse generator

30: frame sync determination unit 31: delay unit

SPC1: Serial parallel converter INV1, INV2: Inverter

AND1 to AND7: AND gate OR1, OR2: OA gate

EX-OR1: Exclusive Oagate

The present invention relates to the detection of frame sync in a multiplexed analog component (MAC) system. More particularly, the present invention relates to detecting a frame sync word or a line sync word in a MAC signal. When the frame sync information is displayed, the frame sync detection circuit of the MAC system detects the frame sync.

In general, in MAC systems, sinks are transmitted in digital form, frame sinks are transmitted in 64 bits, and line sinks are 6 bits, which is 001011's Even Line Sync word (hereinafter referred to as "W2") and 110100. Is composed of an odd-numbered line sink word (hereinafter referred to as " W1 "). A line sink of W1W1W2W2 is transmitted in the odd field, and a line sink of W2W2W1W1 is transmitted in the even field, and one frame is completed by the odd field and the even field. At the end of this frame, a frame sync is sent to indicate whether a frame is over. Therefore, there is a need for a frame sync detection circuit that indicates whether the frame is over.

FIG. 1 illustrates a frame sync detection circuit in a conventional MAC system, wherein a MAC signal inputted serially from a MAC signal input terminal (MACI) is connected to a W1 detector through a serial parallel converter (SPC1) converting serial data into parallel data. 1) W1 of the 110100, which is the odd line sync word, is detected, and the MAC signal through the W1 detector 1 is input to the AND gate AND1 through the 1H delay 2, and on the other hand, the W1 detector The MAC signal through (1) is input to the AND gate AND1 through the inverter INV1 and is ANDed. This AND signal is input to the error detection unit 3 and is recognized as a line sink when the output of the AND gate AND1 falls within a certain error margin. In other words, if the signal detected by the error detection unit 3 falls within a certain error margin, it is determined that the line sink is detected.

Meanwhile, the MAC signal through the W1 detector 1 is input to the AND gate AND2 and ended with the signal through the 1H delay 2, and then the AND gate AND3 through the inverter INV2 and the 2H delay 4. Is inputted to the end).

This ANDed signal is input to the error detector 5 so that the output of the AND gate AND3 falls within an error margin to be regarded as a frame sync. That is, since the frame sync in the MAC system is 64 bits, the error detection unit 5 for detecting the frame sync is regarded as a frame sync when the frame sync is different from the frame sync word sent from the transmitter by 3 error ranges. Frame sync is detected.

As described above, the conventional frame sync detection circuit that detects the line sync and the frame sync is not able to accurately detect the frame sync because the frame sync is detected using only the odd line sync word W1.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to detect a frame sync word or a line sync word and to display information on the frame sync transmitted from the transmitting side even if only one of the frame sync words or line sync words is present. It is an object of the present invention to provide a frame sync detection circuit of a MAC system that can detect frame sync more efficiently by acknowledging that a sync is detected.

A feature of the present invention for achieving this object is a first frame sync detector for detecting a frame sync by detecting a line sync of the MAC signal input connected to the MAC signal input terminal, and a MAC signal connected to the MAC signal input terminal for input; A second frame sync detector for detecting frame sync using a frame sync of the first frame sync; and the MAC signal when the frame sync is detected by the first frame sync detector or the second frame sync detector, connected to the first and second frame sync detectors. The frame sync detection circuit of the MAC system is provided with a frame sync discrimination unit for discriminating a signal input from an input terminal as a frame sync.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates an embodiment of a frame sync detection circuit of a MAC system according to the present invention, and includes first and second frame sync detectors 10 and 20 and a frame sync determiner 30.

The first frame sync detector 10 is connected to a MAC signal input terminal (MACI) to detect the line sync of the input MAC signal to detect the frame sync, the second frame sync detector 20 is also the MAC signal input terminal ( The frame sync is detected by using the frame sync of the MAC signal connected to the MACI input terminal (MACI). The frame sync determiner 30 is connected to the first and second frame sync detectors 10 and 20 to detect the frame sync by the first and second frame sync detectors 10 and 20. In this case, the signal input from the MAC signal input terminal (MACI) is determined as a frame sync.

On the other hand, the first frame sync detector 10 is connected to the MAC signal input terminal (MACI) W1, W2 detector for detecting W1 of the odd line sync word 001011 and W2 of the even line sync word 110100 from the MAC signal input 1H delays 13, 14 and one input terminal of the AND gate AND4 and AND5 are connected to (11) and (12), respectively. The other input terminal of the AND gates AND4 and AND5 is connected to the 1H delays 13 and 14, and the AND gates AND4 and AND5 sense W1W1 or W2W2.

In addition, one input terminal of the AND gates AND7 and AND6 is connected to the output terminals of the AND gates AND4 and AND5, and the other input terminal of the AND gates AND7 and AND6 is the AND gate AND4. 2H delays (16) and (15) connected to (AND5) detect W2W2W1W1 or W1W1W2W2. An OR gate OR1 is connected to the AND gates AND6 and AND7 to logically sum the outputs of the AND gates AND6 and AND7 to detect W1W1W2W2 or W2W2W1W1.

On the other hand, the second frame sync detector 20 is configured to generate an exclusive oragate to the virtual frame sync generator 21 and the MAC signal input terminal (MACI) when generating the same frame sync as the frame sync word transmitted from the transmitter. The frame sync word error detection unit 22 connected to the EX-OR1 is connected to the signal from the MAC signal input terminal MACI and the virtual frame sync generation unit 21 to detect the error of the frame sync word. . In addition, a pulse count detector 23 is connected to the frame sync word error detector 22 to detect a high output of the frame sync word error detector 22, and a pulse count detector 23 is connected to the pulse count detector 23. When detecting three or less high pulses, a pulse generator 24 for generating a pulse is connected.

The frame sync determiner 30 is connected to the first frame sync detector 10 to match the output of the first frame sync detector 10 with the output of the second frame sync detector 20. A delay unit 31 for delaying the output of the 1 frame sync detector 10 and the pulse generator 24 and the delay unit 31 are connected to the output of the pulse generator 24 and the delay unit 31. It consists of an OR gate OR2 that OR's the output to determine the frame sync. 3 is a circuit diagram showing an embodiment of the pulse number generator 23, in which four D flip-flops DFF1 to DFF4 are connected in series so that an output becomes high when four pulses are input. .

When the frame sync word is not detected, the present invention configured as described above can detect a frame sync word by detecting a line sync word. A MAC signal from a tuner (not shown) converts a Duo binary signal into a binary signal. A MAC signal is input to a MAC signal input terminal (MACI) through a duo binary converter (not shown) to be converted, and the MAC signal is input to the first and second frame sync detectors 10 and 20.

The MAC signal input to the first frame sync detector 10 detects a line sync word in the W1 detector 11 and the W2 detector 12. That is, the W1 detector 11 detects the odd line sync word of 001011, and the W2 detector 12 detects the even line sync word of 110100. In the MAC system, since the line sync word is transmitted W2W2W1W1 (excellent field) or W1W1W2W2 (odd field) before the frame is changed, frame sync can be obtained by detecting this word.

Accordingly, when W1 and W2 are detected by the W1 detector 11 and the W2 detector 12, the signal is input to one input terminal of the AND gates AND4 and AND5, and the AND gates AND4 and AND5. Signals through the W1 and W2 detectors 11 and 12 are input to the other input terminal via 1H delays 13 and 14. That is, W1W1 or W2W2 is sensed in these AND gates AND4 and AND5.

When the W1W1 or W2W2 is detected by the AND gates AND4 and AND5, the detected signals are divided into 2H delayed signals and 2H delayed signals through 2H delays 15 and 16, respectively. AND6), and AND7, which means that W1W1 is detected at the AND gate AND4 and then W2W2 is detected at the AND gate AND6, or W2W2 is detected at the AND gate AND5. Then, the AND gate AND7 detects whether W1W1 has been detected. When W1W1W2W2 or W2W2W1W1 is detected through the AND gates AND6 and AND7, the signal is input to the ORG OR1 and the ORGATE (OR1). Make the output of OR1) high.

On the other hand, the second frame sync detection unit 20 inputs the MAC signal input from the MAC signal input terminal (MACI) to the exclusive oragate (EX-OR1) to receive the same frame sync word as the frame sync word sent by the transmitter. When the frame sync word inputted from the virtual frame sink generating unit 21 to generate and the exclusive oar result in this exclusive oar result fall within the three error range, it is regarded as a frame sink.

Since the output of the exclusive oragate EX-OR1 becomes high when the signal input from the MAC signal input terminal MACI and the signal input from the virtual frame sync generator 21 are different, the high pulse is generated. The number of times is detected by the pulse number detector 23, and when the detected signal is three or less, the pulse generator 24 generates a pulse. That is, since the frame sync is 64 bits, when the output of the exclusive oragate EX-OR1 falls within the 3 error range, the frame sync is regarded as the frame sync. Therefore, the output of the exclusive oragate EX-OR1 is high pulse. If it is 4 or more, it cannot be regarded as a frame sync. As a result, when three or less pulses are generated, the output is in a low state, and at this time, the pulse generator 24 generates pulses.

On the other hand, the frame sync word of the MAC signal input from the MAC signal input terminal (MACI) and the frame sync word from the virtual frame sink generator 21 in which the output of the exclusive ogate EX-OR1 falls within the three error range. This means that up to three bits of D are different. In the present invention, when the output of the exclusive OR gate EX-OR1 is within 3 error ranges, it is regarded as a frame sync.

When the output of the OR gate OR1 becomes high between any one of the signal delayed through the delay unit 31 and the signal from the pulse generator 23, the output of the OR gate OR2 becomes high, and thus the current MAC signal input terminal. The MAC signal input from the (MACI) is regarded as a frame sync.

On the other hand, the pulse number detection unit 23 detects the number of pulses in the following form.

In FIG. 3, the output is high when there are four or more input pulses, and when the input pulses are not four, the low is displayed. Since the frame sink comes after the line sink, a clear is performed every line sink. In other words, if the frame sync word detects two errors earlier, the output is high even if only two frame sync words are detected as errors.

If the output of the pulse number detector 23 is not high but is low, the output signal of the pulse number detector 23 is within 3 error ranges, so the input signal is regarded as a frame sync. That is, when the line sync is detected and the frame is finished, the frame sync is raised, so that the output of the pulse number detector 22 goes low, so that the frame is finished, that is, the position is the frame sync. However, when the detection output of the pulse number detection unit 23 becomes high, it is detected that the frame is not finished. That is, only after the frame sync is detected, the output of the pulse number detection unit 23 is low. Otherwise it goes high. As a result, even when the output of the pulse number detector 23 becomes low during frame sync, and the pulse generator 24 does not generate a pulse, the ORA is regarded as a frame sync because the output becomes high, so only one line sync is used. If detected, the frame sync will be detected.

As described above, the present invention detects a frame sync coming from 64-bit in a MAC system and recognizes it as a frame sync. Also, when a frame is changed, a line sync word is arranged in a predetermined form. If only one is detected, it is recognized as a frame sync. In other words, even if the frame sync word is not read, the frame sync word can be detected by reading the line sync word.

As described above, when the frame sync word or the line sync word array indicates information of the frame sync transmitted from the transmitting side when the frame sync is detected in the MAC system, the frame sync word is detected as a frame sync. Since the frame sync is detected by detecting the line sync word, the frame sync is detected more efficiently.

Claims (5)

A first frame sync detector 10 detecting frame sync by detecting line sync of an input MAC signal connected to a MAC signal input terminal (MACI) and a frame of a MAC signal connected to the MAC signal input terminal (MACI) A second frame sync detector 20 that detects frame sync using a sync; and a first frame sync detector 10 or a second unit connected to the first and second frame sync detectors 10 and 20 Frame sync detection circuit of the MAC system provided with a frame sync determiner (30) for determining the frame sync signal received from the MAC signal input terminal (MACI) when the frame sync detection in the frame sync detection unit (20). The W1 and W2 detectors of claim 1, wherein the first frame sync detector 10 detects the odd-line sync word and even-line sync word from a MAC signal input and connected to a MAC signal input terminal (MACI). And an AND gate connected to the W1 and W2 detectors 11 and 12 to logically multiply the output of the W1 and W2 detectors 11 and 12 and the output signal by the 1H delayed signal. An AND gate AND6 connected to the AND4 and AND5 and the AND gate AND4 and AND5 to logically multiply the output of the AND gate AND4 and the output of the 2H delayed signal. And (AND7) and an OR gate (OR1) connected to the AND gates (AND6) and (AND7) and configured to OR the outputs of the AND gates (AND6) and (AND7). 2. The second frame sync detection unit (20) according to claim 1, wherein the second frame sync detector (20) includes a virtual frame sync generator (21) for generating the same frame sync word as the frame sync word transmitted from the transmitter, and the MAC signal input terminal (MACI). And a frame sync word error detector 22 connected to the virtual frame sync generator 21 to compare the signals input from the MAC signal input terminal MACI and the virtual frame sync generator 21 to detect an error of a frame sync word. ), A pulse number detector 23 connected to the frame sync word error detector 22 to detect a high output of the frame sync error detector 22, and a pulse number detector connected to the pulse number detector 23. 23. A frame sync detection circuit of a MAC system comprising a pulse generator (24) for generating pulses when four or more high pulses are detected in (23). 4. The frame sync word error detector 22 is connected to the MAC signal input terminal (MACI) and the virtual frame sync generator 21, and the MAC signal input terminal (MACI) and the virtual frame sync generator 21 are generated. A frame sync detection circuit of an MAC system, comprising an exclusive oragate (EX-OR1) for exclusively ORing a signal from the < RTI ID = 0.0 > The frame sync determiner 30 is connected to the first frame sync detector 10 to output the first frame sync detector 10 and the output of the second frame sync detector 20. A delay unit 31 for delaying an output of the first frame sync detector 10, a pulse generator 24, and a delay unit 31 to match the output of the pulse generator 24. A frame sync detection circuit of a MAC system, comprising an OR gate (OR2) for ORing the output of the delay unit (31) to determine frame sync.