KR970008484A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR970008484A
KR970008484A KR1019950023185A KR19950023185A KR970008484A KR 970008484 A KR970008484 A KR 970008484A KR 1019950023185 A KR1019950023185 A KR 1019950023185A KR 19950023185 A KR19950023185 A KR 19950023185A KR 970008484 A KR970008484 A KR 970008484A
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KR
South Korea
Prior art keywords
semiconductor device
device isolation
separation method
isolation method
etching process
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Application number
KR1019950023185A
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Korean (ko)
Inventor
장규환
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950023185A priority Critical patent/KR970008484A/en
Publication of KR970008484A publication Critical patent/KR970008484A/en

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Abstract

반도체 장치의 소자분리 방법에 관하여 기재되어 있다. 식각 선택비를 가진 두 물질층을 패턴 사이에 적층시킨 후, 평탄화 공정과 식각 공정을 이용하여 두개의 트랜치를 형성하는 반도체 장치의 소자분리 방법을 제공한다. 다결정실리콘과 산화물로 만들 수 있는 가장 얇은 두께의 폭을 가진 트랜치를 형성하면, 고집적의 메모리 소자에서도 효과적인 소자 분리가 가능하다.A device isolation method of a semiconductor device is described. The present invention provides a device isolation method for a semiconductor device in which two material layers having an etch selectivity are stacked between patterns, and then two trenches are formed using a planarization process and an etching process. Forming a trench with the thinnest thickness that can be made of polycrystalline silicon and oxide enables effective device isolation even in highly integrated memory devices.

Description

반도체 장치의 소자분리 방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도 내지 제9도는 본 발명의 제1실시예에 따른 소자분리방법의 제공정을 순서대로 도시한 단면도.5 to 9 are cross-sectional views sequentially showing the provision of the device isolation method according to the first embodiment of the present invention.

Claims (4)

식각 선택비를 가진 두 물질층을 패턴 사이에 적층시킨 후, 평탄화 공정과 식각 공정을 이용하여 두개의 트랜치를 형성하는 반도체 장치의 소자분리 방법.A device isolation method of a semiconductor device in which two trenches are formed by stacking two material layers having an etch selectivity between patterns, and using a planarization process and an etching process. 제1항에 있어서, 평탄화 공정으로 CMP 기술을 이용하는 반도체 장치의 소자분리방법.The device isolation method of claim 1, wherein the CMP technique is used as a planarization process. 제1항에 있어서, 식각 공정으로 이방성 식각을 사용하는 반도체 장치의 소자분리방법.The method of claim 1, wherein the anisotropic etching is used as an etching process. 제1항에 있어서, 물질층으로 2개 또는 3개를 이용하는 반도체 장치의 소자분리방법.The method of claim 1, wherein two or three are used as the material layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950023185A 1995-07-31 1995-07-31 Device Separation Method of Semiconductor Device KR970008484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950023185A KR970008484A (en) 1995-07-31 1995-07-31 Device Separation Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950023185A KR970008484A (en) 1995-07-31 1995-07-31 Device Separation Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR970008484A true KR970008484A (en) 1997-02-24

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Application Number Title Priority Date Filing Date
KR1019950023185A KR970008484A (en) 1995-07-31 1995-07-31 Device Separation Method of Semiconductor Device

Country Status (1)

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KR (1) KR970008484A (en)

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