KR970003960A - Capacitor Pattern Formation Method of Semiconductor Device - Google Patents

Capacitor Pattern Formation Method of Semiconductor Device Download PDF

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Publication number
KR970003960A
KR970003960A KR1019950019116A KR19950019116A KR970003960A KR 970003960 A KR970003960 A KR 970003960A KR 1019950019116 A KR1019950019116 A KR 1019950019116A KR 19950019116 A KR19950019116 A KR 19950019116A KR 970003960 A KR970003960 A KR 970003960A
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KR
South Korea
Prior art keywords
etching
polysilicon
layer
capacitor
ratio
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KR1019950019116A
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Korean (ko)
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KR0172719B1 (en
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최승봉
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김주용
현대전자산업 주식회사
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Priority to KR1019950019116A priority Critical patent/KR0172719B1/en
Publication of KR970003960A publication Critical patent/KR970003960A/en
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Publication of KR0172719B1 publication Critical patent/KR0172719B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

고집적 반도체 소자 제조 방법.Highly integrated semiconductor device manufacturing method.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래에는 캐패시터의 패턴을 정의하기 위해, 도핑으로 인해 형성된 자연 산화막을 제거한다음, 포토레지스트 패턴을 형성하고, 폴리실리콘 및 ONO 막의 식각 공정을 실시하는데, 단차가 형성되어 있는 부분에는 자연 산화막이 완전히 제거되지 않아, 식각시 폴리실리콘의 잔류를 유발하는 경우가 종종 발생하고 있으며, ONO막이 완전히 제거되지 않고 잔류하고 있다가 기판과의 콘택을 형성하는 경우에 콘택의 접촉 불량을 유발하게 되는 등의 문제점이 있었음.Conventionally, in order to define a pattern of a capacitor, a natural oxide film formed by doping is removed, a photoresist pattern is formed, and a polysilicon and an ONO film are etched, and the natural oxide film is completely removed at the portion where the step is formed. In some cases, polysilicon may remain during etching, and the ONO layer may not be completely removed and remain in contact with the substrate, resulting in poor contact of the contact. Was there.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

산화막과 폴리실리콘을 동시에 선택적으로 식각하도록 식각 선택비를 조절하여 1차로 폴리실리콘의 일부를 식각하고, 다시 식각 선택비를 더 크게하고 식각 종말점을 선정하여 2차 식각을 실시한 다음, 잔존할 수도 있는 폴리실리콘과 하부의 유전층의 과도 식각을 실시하므로써, 자연 산화막 전류 및 유전막의 잔류로 인한 소자 불량을 방지할 수 있는 캐패시터 제조 방법을 제공하고자 함.The etching selectivity is adjusted to selectively etch the oxide film and the polysilicon at the same time, so that a part of the polysilicon is etched first, and then the etching selectivity is increased, the etching end point is selected, and the second etching is performed. By performing excessive etching of polysilicon and the lower dielectric layer, it is intended to provide a method for manufacturing a capacitor that can prevent device defects due to natural oxide current and residual dielectric film.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 소자의 캐패시터 제조에 이용됨.Used to manufacture capacitors in semiconductor devices.

Description

반도체 소자의 캐패시터 패턴 형성 방법Capacitor Pattern Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 캐패시터가 형성되어 있는 제조 공정도.1 is a manufacturing process diagram in which a capacitor to which the present invention is applied is formed.

Claims (4)

반도체 기판에 하부층 및 층간 절연막이 증착되고, 그 위에 두개의 상부, 하부 폴리실리콘층과 그 사이의 유전막으로 이루어진 캐패시터 구조가 형성된 상태에서 캐패시터의 패턴을 형성하는 방법에 있어서, 캐패시터 패턴을 정의하기 위한 포토레지스트 패턴을 형성하는 단계와, He과 SF6가스를 이용하여 폴리실리콘과 산화막의 식각비를 소정의 비율로 하여 상기 상부 폴리실리콘층의 일부를 식각하는 단계와, SF6, Cl2및 He 가스를 이용하여 폴리실리콘과 산화막의 식각비를 상기 상부 폴리실리콘층의 일부를 식각하는 단계에서의 비율 보다 큰 비율로 하고, 식각, 종말점을 선정하여 상기 상부 폴리실리콘층의 잔여 부분을 식각하는 단계 및, SF6, Cl2, He, HBr 및 O2가스를 이용하여 상기 유전막을 과도 식각하는 단계를 포함해서 이루어진 캐패시터 패턴 형성 방법.A method of forming a capacitor pattern in a state in which a lower layer and an interlayer insulating film are deposited on a semiconductor substrate, and a capacitor structure composed of two upper and lower polysilicon layers and a dielectric film therebetween is formed. Forming a photoresist pattern, etching a portion of the upper polysilicon layer by using a He and SF 6 gas at an etch ratio of polysilicon and an oxide film at a predetermined ratio, and SF 6 , Cl 2, and He Etching the remaining portion of the upper polysilicon layer by selecting an etching point and ending point by setting the etching ratio of the polysilicon and the oxide layer using a gas to a ratio greater than that in the step of etching the portion of the upper polysilicon layer and, SF 6, a capacitor made, including the step of using a Cl 2, He, HBr and O 2 gas etching the dielectric transient Turn-forming method. 제1항에 있어서, 상기 상부 폴리실리콘층의 일부를 식각하는 단계는 폴리실리콘과 산화막의 식각비가 약 1.5~2.5:1로 하여 수행되는 것을 특징으로 하는 캐패시터 패턴 형성 방법The method of claim 1, wherein etching the portion of the upper polysilicon layer is performed by using an etching ratio of polysilicon to an oxide layer of about 1.5 to about 2.5: 1. 제1항 또는 제2항에 있어서, 상기 상부 폴리실리콘층의 잔여 부분을 식각하는 단계는 폴리실리콘과 산화막의 식각비가 약 5~8:1로 하여 수행되는 것을 특징으로 하는 캐패시터 패턴 형성 방법.The method of claim 1, wherein the etching of the remaining portion of the upper polysilicon layer is performed by using an etching ratio of polysilicon to an oxide layer of about 5 to 8: 1. 제1항 또는 제2항에 있어서, 상기 상부 폴리실리콘층의 일부를 식각하는 단계에서 약 700Å 내지 900Å이 식각되는 것을 특징으로하는 캐패시터 패턴 형성 방법.3. The method of claim 1, wherein in the etching of a portion of the upper polysilicon layer, about 700 μs to 900 μs are etched. 4. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019116A 1995-06-30 1995-06-30 Fabricating method of semiconductor capacitor KR0172719B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019116A KR0172719B1 (en) 1995-06-30 1995-06-30 Fabricating method of semiconductor capacitor

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Application Number Priority Date Filing Date Title
KR1019950019116A KR0172719B1 (en) 1995-06-30 1995-06-30 Fabricating method of semiconductor capacitor

Publications (2)

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KR970003960A true KR970003960A (en) 1997-01-29
KR0172719B1 KR0172719B1 (en) 1999-02-01

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KR1019950019116A KR0172719B1 (en) 1995-06-30 1995-06-30 Fabricating method of semiconductor capacitor

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