KR970003687A - Low doping drain thin film transistor manufacturing method - Google Patents

Low doping drain thin film transistor manufacturing method Download PDF

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Publication number
KR970003687A
KR970003687A KR1019950016392A KR19950016392A KR970003687A KR 970003687 A KR970003687 A KR 970003687A KR 1019950016392 A KR1019950016392 A KR 1019950016392A KR 19950016392 A KR19950016392 A KR 19950016392A KR 970003687 A KR970003687 A KR 970003687A
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KR
South Korea
Prior art keywords
source
low doping
drain
ion implantation
thin film
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KR1019950016392A
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Korean (ko)
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KR100197522B1 (en
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황준
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김주용
현대전자산업 주식회사
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Priority to KR1019950016392A priority Critical patent/KR100197522B1/en
Publication of KR970003687A publication Critical patent/KR970003687A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자 제조 방법.Semiconductor device manufacturing method.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

종래의 방범에 따르면 이온주입 공정과 포토레지스터 패턴 형성 공정을 여러번 실시해야 하므로 소스/드레인 영역, 저도핑 드레인 영역, 채널 영역의 길이의 변화가 생기고 정렬이 어긋나 위치의 변화도 일어나기 쉽고 공정도 복잡하다는 문제점을 해결하고자 함.According to the conventional crime prevention, since the ion implantation process and the photoresist pattern forming process have to be performed several times, the lengths of the source / drain region, the low doping drain region, and the channel region are changed, misaligned and the position is easily changed, and the process is complicated. I want to solve the problem.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

포토레지스트 패턴 형성없이 유체 타입의 물질을 이용하여 한번의 이온주입으로 소스/드레인 영역 및 저도핑 드레인 영역을 형성하므로써, 정확하게 셀프얼라인된 저도핑 드레인 구조의 박막트렌지스터를 제고하고자 함.By forming a source / drain region and a low doping drain region with a single ion implantation using a fluid type material without forming a photoresist pattern, a thin self-aligned thin film transistor of low doping drain structure is to be improved.

4. 발명의 중요한 용도4. Important uses of the invention

저도핑 드레인 구조의 박막 트랜지스터를 제조하는데 이용됨.Used to manufacture thin film transistors with low doped drain structure.

Description

저도핑 드레인 구조의 박막 트랜지스터 제조 방법Low doping drain thin film transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 저도핑 드레인 구조의 박막 드랜지스터 제조 방법의 한 실시예에 따른 공정도.2A to 2D are process diagrams according to one embodiment of a method for fabricating a thin film transistor with a low doped drain structure of the present invention.

Claims (8)

저도핑 드레인 구조의 박막 트랜지스터를 제조하는 방법에 있어서, 반도체 기판에 하부층 산화막이 형성되고 게이트 전극이 형성된 구조상에 게이트 산화막을 증착하는 단계와, 소스/드레인용 폴리시실리콘은 증착하고 소스/드레인 영역 형성을 위한 이온주입을 실시하는 단계와, 이닐링을 실시하고 소스/드레인용 폴리실리콘의 라인을 형성하는 단계와 소정의 두께로 표면 평탄화막을 도포하는 단계와, 상기 소스/드레인 영역의 이온과 반대 타입으로, 소스/드레인용 폴리실리콘에 주입되는 이온의 양과 이온주입 에너지를 적절히 조절하여 이온주입을 실시하여 상기 도포된 표면 평탄화막의두께에 따라서 저도핑 드레인 영역과 채널영역을 형성하는 단계와, 어닐링을 실시하는 단계를 포함하여 이루어진 저도핑드레인 구조의 박막 트랜지스터 제조 방법.A method of manufacturing a thin film transistor having a low doping drain structure, the method comprising: depositing a gate oxide layer on a structure in which a lower layer oxide film is formed on a semiconductor substrate and a gate electrode is formed, depositing source / drain polysilicon and forming a source / drain region Performing ion implantation, performing annealing, forming a line of source / drain polysilicon, and applying a surface planarization film to a predetermined thickness, the type opposite to the ion of the source / drain region By performing an ion implantation by appropriately adjusting the amount of ions and ion implantation energy injected into the source / drain polysilicon to form a low doping drain region and a channel region according to the thickness of the coated surface planarization film, and annealing Fabrication of a thin film transistor having a low doping drain structure comprising the step of performing Law. 제1항에 있어서, 상기 표면 평탄화막을 포토레지스트인 것을 특징으로 하는 저도핑 드레인 구조와 박막 트랜지스터 제조 방법.The method of claim 1, wherein the surface planarization film is a photoresist. 제2항에 있어서, 상기 포토레지스트를 도포한 후 하드베이킹을 실시하는 단계를 더 포함하는 것을 특징으로 하는 저도핑 드레인 구조의 박막 트랜지스터 제조 방법.The method of claim 2, further comprising performing hard baking after applying the photoresist. 제2항에 있어서, 상기 소스/드레인 영역의 이온과 반대 타입의 이온 주입을 실시한 후 상기 포토레지스트를 제거하는 단계를 더 포함하는 것을 특징으로 하는 저도핑 드레인 구조의 박막 트랜지스터 제조 방법.3. The method of claim 2, further comprising removing the photoresist after performing ion implantation of a type opposite to that of the source / drain regions. 4. 제2항에 있어서, 상기 도포된 포토레지스트의 게이트 전극 부분 위에 두께는 약 500Å이하인 것을 특징으로 하는 저도핑 드레인 구조의 박막 트랜지스터 제조 방법.3. The method of claim 2, wherein the thickness of the coated photoresist on the gate electrode portion is about 500 GPa or less. 제3항에 있어서, 상기 하드베이킹은 약 130℃ 내지 150℃의 온도에서 1 내지 2분간 실시하는 것을 특징으로 하는 저도핑 드레인 구조의 박막 트랜지스터 제조 방법.The method of claim 3, wherein the hard baking is performed at a temperature of about 130 ° C. to 150 ° C. for 1 to 2 minutes. 제1항에 있어서, 상기 표면 평탄화막은 액상 절연막인 것을 특징으로 하는 저도핑 드레인 그조의 박막 트랜지스터 제조 방법.The method of claim 1, wherein the surface planarization film is a liquid insulating film. 제7항에 있어서, 상기 액생 절연막의 게이트 전극 부분 상의 두께는 약 200Å 이하로 유지하는 것을 특징으로 하는 저도핑 드레인 구조의 박막 트랜지스터 제조 방법.8. The method of claim 7, wherein the thickness on the gate electrode portion of the auxiliary insulating film is maintained at about 200 kPa or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950016392A 1995-06-20 1995-06-20 Method of manufacturing low-doping drain structure KR100197522B1 (en)

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KR1019950016392A KR100197522B1 (en) 1995-06-20 1995-06-20 Method of manufacturing low-doping drain structure

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KR100197522B1 KR100197522B1 (en) 1999-06-15

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