KR100197522B1 - Method of manufacturing low-doping drain structure - Google Patents
Method of manufacturing low-doping drain structure Download PDFInfo
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- KR100197522B1 KR100197522B1 KR1019950016392A KR19950016392A KR100197522B1 KR 100197522 B1 KR100197522 B1 KR 100197522B1 KR 1019950016392 A KR1019950016392 A KR 1019950016392A KR 19950016392 A KR19950016392 A KR 19950016392A KR 100197522 B1 KR100197522 B1 KR 100197522B1
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- South Korea
- Prior art keywords
- source
- drain
- ion implantation
- photoresist
- drain region
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000012530 fluid Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자 제조 방법Semiconductor device manufacturing method
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
종래의 방범에 따르면 이온주입 공정과 포토레지스터 패턴 형성 공정을 여러번 실시해야 하므로 소스/드레인 영역, 저도핑 드레인 영역, 채널 영역의 길이의 변화가 생기고 정렬이 어긋나 위치의 변화도 일어나기 쉽고 공정도 복잡하다는 문제점을 해결하고자 함.According to the conventional crime prevention, since the ion implantation process and the photoresist pattern forming process have to be performed several times, the lengths of the source / drain region, the low doping drain region, and the channel region are changed, misaligned and the position is easily changed, and the process is complicated. I want to solve the problem.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
포토레지스트 패턴 형성없이 유체 타입의 물질을 이용하여 한번의 이온주입으로 소스/드레인 영역 및 저도핑 드레인 영역을 형성하므로써, 정확하게 샐프얼라인된 저도핑 드레인 구조의 박막트렌지스터를 제고하고자 함.By forming a source / drain region and a low doping drain region by a single ion implantation using a fluid type material without forming a photoresist pattern, a thin doped transistor having a precisely doped low doping drain structure is to be improved.
4. 발명의 중요한 용도4. Important uses of the invention
저도핑 드레인 구조의 박막 트랜지스터를 제조하는데 이용됨.Used to manufacture thin film transistors with low doped drain structure.
Description
제1a도 내지 제1d도는 종래의 저도핑 드레인 구조의 박막트랜 지스터 제조 방법에 따른 공정도.1a to 1d is a process chart according to a conventional method for manufacturing a thin film transistor of a low doped drain structure.
제2a도 내지 제2d도는 본 발명의 저도핑 드레인 구조의 박막 트랜지스터 제조 방법의 한 실시예에 따른 공정도.2A to 2D are process diagrams according to an embodiment of a method for manufacturing a thin film transistor having a low doped drain structure according to the present invention.
제2c'도는 본 발명의 다른 실시예에 따른 저도핑 드레인 구조의 박막 트랜지스터의 단면도.2c 'is a cross-sectional view of a thin-film transistor of low doping drain structure according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 11 : 반도체 기판 2, 12 : 하부층 산화막1, 11: semiconductor substrate 2, 12: lower layer oxide film
3, 13 : 게이트 전극 4, 14 : 게이트 산화막3, 13: gate electrode 4, 14: gate oxide film
5, 15 : 소스/드레인용 폴리실리콘 16 : 포토레지스트5, 15 polysilicon for source / drain 16: photoresist
17 : 액상 절연막(Liquid Phass Dielectric)17: Liquid Phass Dielectric
본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서 특히, 포토레지스트 패턴의 형성없이 저도핑 드레인 영역과 소스/드레인 영역을 간단하고 정확하게 형성할 수 있는 저도핑 드레인 구조의 박막 트랜지스터를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a low doping drain structure thin film transistor capable of simply and accurately forming a low doping drain region and a source / drain region without forming a photoresist pattern. will be.
SRAM의 고부하저항(High Load Resistor)으로 사용되는 박막 트랜지스터 제조 방법에 있어서, 우선 종래의 저도핑 드레인 구조의 박막 트랜지스터 제조 방법을 첨부도면을 참조하여 살펴보게 된다. 먼저 제1a도에 도시된 바와 같이 반도체 기판(1) 상에 하부층 산화막(2)이 형성되고 게이트 전극(3)이 형성된 구조 상에 게이트 산화막(4)을 증착한다. 그리고 소스/드레인용 폴리실리콘(5)을 증착하고 N-형의 이온주입을 실시하여 채널영역을 형성한다. 다음으로 제1b도에 도시된 바와 같이 상기 게이트 전극(3) 부위만 덮인 제1포토레지스트 패턴을 형성한 후 저도핑 드레인 영역 형성을 위한 P-형의 이온주입을 실시한다. 다음으로 제1c도에 도시된 바와 같이 상기 포토레지스트를 제거하고 소스/드레인 영역만 오픈된 제2포토레지스트 패턴을 형성하고 소스/드레인 영역 형성을 의한 P+형의 이온주입을 실시한다. 마지막으로 제1d도에 도시된 바와 같이 상기 포토레지스트를 제거하고 어닐링을 실시한다. 전술한 바와 같은 종래의 방법에 따르면 이온주입 공정을 3번, 포토레지스트 패턴 형성 공정을 2번이나 실시해야 하므로 소스/드레인 영역, 저도핑 드레인 영역, 채널 영역의 길이의 변화가 생기고 정렬이 어긋나 위치의 변화도 일어나기 쉽고 공정도 복잡하다는 문제점을 가지고 있었다.In the method of manufacturing a thin film transistor used as a high load resistor of an SRAM, a conventional method of manufacturing a thin film transistor having a low doped drain structure will be described with reference to the accompanying drawings. First, as shown in FIG. 1A, a gate oxide film 4 is deposited on a structure in which a lower layer oxide film 2 is formed on a semiconductor substrate 1 and a gate electrode 3 is formed. Then, the source / drain polysilicon 5 is deposited and an N-type ion implantation is performed to form a channel region. Next, as shown in FIG. 1B, a first photoresist pattern covering only the portion of the gate electrode 3 is formed, and then P-type implantation is performed to form a low doped drain region. Next, as shown in FIG. 1C, the photoresist is removed, a second photoresist pattern in which only the source / drain regions are opened is formed, and P + type implantation is performed by forming the source / drain regions. Finally, the photoresist is removed and annealed as shown in FIG. 1d. According to the conventional method as described above, the ion implantation process has to be performed three times and the photoresist pattern forming process has to be performed twice, so that the lengths of the source / drain regions, the low-doped drain regions, and the channel regions are changed, and the alignment is misaligned. The change was easy to occur and the process was complicated.
따라서, 전술한 바와 같은 문제점을 해결하기 위해 안출된 본 발명을 포토레지스트 패턴 형성없이 유체 타입의 물질을 이용하여 표면을 평탄화시키므로써, 한번 이온주입으로 소스/드레인 영역 및 저도핑 드레인 영역을 형성하여 정확하게 셀프얼라인(self-align)된저도핑 드레인 구조의 박막 트랜지스터를 제조하는 방법을 제공하는 것을 특징으로 한다.Accordingly, the present invention devised to solve the above problems is planarized by using a fluid type material without forming a photoresist pattern, thereby forming a source / drain region and a low doping drain region by ion implantation. A method of manufacturing a thin film transistor having a precisely self-aligned low doping drain structure is provided.
본 발명에 따른 저도핑 드레인 구조의 박막 트랜지스터 제조방법은, 반도체 기판에 하부층 산화막이 형성되고 게이트 전극이 형성된 구조 상에 게이트 산화막을 증착하는 단계와. 소스/드레인용 폴리실리콘은 증착하고 소스/드레인 영역 형성을 위한 이온주입을 실시하는 단계와, 어닐링을 실시하고 소스/드레인용 폴리실리콘의 라인을 형성하는 단계와, 소정의 두께로 표면 평탄화막을 도포하는 단계와, 상기 소스/드레인 영역의 이온과 반대 타입으로, 소스/드레인용 폴리실리콘에 주입되는 이온의 양과 이온주입 에너지를 적절히 조절하여 이온주입을 실시하여 상기 도포된 표면 평탄화막의 두께에 따라서 저도핑 드레인 영역과 채널영역을 형성하는 단계와, 어닐링을 실시하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a thin-film transistor having a low doped drain structure according to the present invention includes depositing a gate oxide film on a structure in which a lower layer oxide film is formed on a semiconductor substrate and a gate electrode is formed. Depositing the source / drain polysilicon and performing ion implantation to form the source / drain region, performing annealing and forming a line of the source / drain polysilicon, and applying a surface planarization film to a predetermined thickness And ion implantation by appropriately adjusting the amount of ions injected into the source / drain polysilicon and ion implantation energy in the opposite type to the ions in the source / drain region, and according to the thickness of the coated surface planarization film. And forming an ping drain region and a channel region, and performing annealing.
본 발명의 저도핑 드레인 구조의 박막 트랜지스터 제조 방법의 한 실시예에 대하여 첨부도면을 참조하여 상세하게 살펴보게 된다. 먼저 제2a도에 도시된 바와 같이 반도체 기판(11)에 하부층 산화막(12)이 형성되고 게이트 전극(13)이 형성된 구조 상에 게이트 산화막(14)을 증착한다. 다음으로 제2b도에 도시된 바와 같이 소스/드레인용 폴리실리콘(15)을 증착하고 P+형의 이온주입을 실시한 후, 어닐링을 실시하고 소스/드레인용 폴리실리콘의 라인을 형성한다. 다음으로 제2c도에 도시된 바와 같이 표면이 평탄하게 되도록 포토레지스트(16)를 도포한다. 이때 점도가 낮은 포토레지스트를 사용하여 낮은 회전 속도9Revoluition Per Minute)로 스핀 코팅을 실시하여 상기 게이트 전극(13) 부분 상에 코팅된 포토레지스트의 두께가 약 500Å이하가 되도록 한다. 그리고 약 130℃ 내지 150℃의 온도에서 1 내지 2분간 하드베이킹(Hard Baking)을 실시한 후 N+형의 이온주입을 실시한다. 이 때 이온주입 에너지, 소스(source) 가스의 양을 적절히 조절하여 상기 도포된 포토레지스트의 두께에 따라 저도핑 드레인 영역은 P-형의 이온영역이 되고 채널 영역은 N-형의 이온영역이 되도록 한다. 마지막으로 제2d도에 도시된 바와 같이 상기 포토레지스트(16)를 제거하고 어닐링을 실시한다.An embodiment of a method of manufacturing a thin film transistor having a low doped drain structure according to the present invention will be described in detail with reference to the accompanying drawings. First, as shown in FIG. 2A, the gate oxide layer 14 is deposited on the structure in which the lower layer oxide layer 12 is formed on the semiconductor substrate 11 and the gate electrode 13 is formed. Next, as shown in FIG. 2B, the source / drain polysilicon 15 is deposited and P + type ion implantation is performed, followed by annealing to form a line of the source / drain polysilicon. Next, the photoresist 16 is applied so that the surface is flat as shown in FIG. 2C. In this case, spin coating is performed using a low viscosity photoresist at a low rotational speed of 9 revolution per minute so that the thickness of the photoresist coated on the gate electrode 13 is about 500 kPa or less. Then, hard baking is performed at a temperature of about 130 ° C. to 150 ° C. for 1 to 2 minutes, followed by N + ion implantation. At this time, the amount of ion implantation energy and source gas is appropriately adjusted so that the low-doped drain region becomes a P-type ion region and the channel region becomes an N-type ion region according to the thickness of the applied photoresist. do. Finally, the photoresist 16 is removed and annealed as shown in FIG. 2d.
다음으로 저도핑 드레인 구조의 박막 트랜지스터 제조 방법의 다른 실시예에 대하여 자세하게 살펴보면, 전술한 실시예의 제2a도와 제2b도에 도시된 바와 같이 반도체 기판(11)에 하부층 산화막(12)이 형성된 구조 상에 게이트 전극(13)과 게이트 산화막(14) 및 이온주입된 소스/드레인 라인을 차례로 형성한다, 다음으로 제2c'도에 도시된 바와 같이 포토레지스트의 도포 대신 액상 절연막(Liquid Phass dielectric)(17)을 증착한다. 이 때 상기 게이트 전극(13) 부분상에 증착된 액상 절연막(17)의 두께는 약 200Å이하로 유지하게 한다 그리고 이온주입 에너지, 소스(source) 가스의 양을 적절히 조절하여 상기 액상 절연박(17)의두께에 따라 저도핑 드레인 영역은 P-형의 이온영역이 되고 채럴 영역은 N-형의 이온영역이 되도록 N+형의 이온주입을 실시한후 어닐링을 실시한다.Next, another embodiment of a method of manufacturing a thin film transistor having a low doped drain structure will be described in detail. As shown in FIGS. 2A and 2B, the lower layer oxide film 12 is formed on the semiconductor substrate 11. The gate electrode 13, the gate oxide film 14, and the ion implanted source / drain lines are formed in this order. Next, as shown in FIG. 2C ', a liquid insulating film (Liquid Phass dielectric) is used instead of the application of the photoresist. E). At this time, the thickness of the liquid insulating film 17 deposited on the gate electrode 13 is maintained at about 200 kΩ or less, and the amount of ion implantation energy and source gas is appropriately adjusted to adjust the liquid insulating foil 17. Depending on the thickness of the N-type ion implantation, the low doping drain region becomes a P-type ion region and the barrel region becomes an N-type ion region, followed by annealing.
반도체 소자 제조시, 전술한 바와 같은 본 발명에 따라 저도핑 드레인 구조의 박막 트랜지스터를 제조하므로써 포토레니지스트 패턴 형성 없이 효과적으로 셀프얼라인(self-align)되어 이온주입이 실시될 수 있어 공정이 간편해질수 있다. 또한 포토래지스트 패턴을 형성하여 이온주입하는 공정에서 발생하는 선폭의 변화나 미스얼라인(Misaling)으로 인해 반도체 소자가 불량해지는 것을 방지할 수 있다.When manufacturing a semiconductor device, according to the present invention as described above, by manufacturing a thin-film transistor having a low doping drain structure, the ion implantation can be carried out effectively by self-aligning without forming a photoresist pattern, thereby simplifying the process. have. In addition, the semiconductor device may be prevented from being deteriorated due to a change in line width or misalignment generated in the process of forming the photoresist pattern and implanting ions.
Claims (8)
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| KR1019950016392A KR100197522B1 (en) | 1995-06-20 | 1995-06-20 | Method of manufacturing low-doping drain structure |
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| KR1019950016392A KR100197522B1 (en) | 1995-06-20 | 1995-06-20 | Method of manufacturing low-doping drain structure |
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| KR100197522B1 true KR100197522B1 (en) | 1999-06-15 |
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