KR940010311A - How to improve the characteristics and uniformity of thin film transistors - Google Patents

How to improve the characteristics and uniformity of thin film transistors Download PDF

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Publication number
KR940010311A
KR940010311A KR1019920019827A KR920019827A KR940010311A KR 940010311 A KR940010311 A KR 940010311A KR 1019920019827 A KR1019920019827 A KR 1019920019827A KR 920019827 A KR920019827 A KR 920019827A KR 940010311 A KR940010311 A KR 940010311A
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South Korea
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film
thin film
oxide film
implanted
transistor
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KR1019920019827A
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Korean (ko)
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KR950011785B1 (en
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손광식
남종완
최국선
이왕주
노승정
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 박막트랜지스터의 특성 및 균일성 개선 방법에 관한 것으로, 반도체 기판에 형성된 웰(well)(1)상에 소정의 간편으로 필드 산화막(소자 분리 절연막)(2)을 형성하고 벌크 박막트랜지스터의 게이트 산화막(3)과 이온 주입된 플리실리콘막을 소정의 크기로 형성하여 벌크 트렌지스터의 게이트 전극(4)을 형성한 다음에 IPO(5)를 전면에 증착하고 폴리실리콘막(6)을 소정의 크기로 형성하는 제1단계, 상기 제1단계 후에 산화막(7)을 증착하고 불순물 주입된 산화막(또는 BPSG)(8)을 도포하여 플로우(flow) 시키고 편탄화한 후에 후속 공정의 폴리실리콘막과 절연을 위한 이온 주입되지 않은 산화막(9)를 증착하는 제2단계, 및 상기 제2단계 후에 이온 주입되는 폴리실리콘막을 증착하여 소정의 크기로 박막트랜지스터의 게이트 전극(10)을 형성하고 박막트랜지스터의 게이트 산화막(11)을 형성한 후에 이온 주입되는 폴리실리콘막으로 채널 폴리실리콘막(12)을 형성하는 제3단계를 포함하여 이루어지는 것을 특징으로 하는 박막트랜지스터의 특성 및 균일성 개선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving the characteristics and uniformity of a thin film transistor, wherein a field oxide film (element isolation insulating film) 2 is simply formed on a well 1 formed in a semiconductor substrate, and a bulk thin film transistor The gate oxide film 3 and the ion implanted polysilicon film are formed to a predetermined size to form the gate electrode 4 of the bulk transistor, and then the IPO 5 is deposited on the entire surface, and the polysilicon film 6 is formed to a predetermined size. After the first step of forming, the oxide film 7 is deposited and the impurity implanted oxide film (or BPSG) 8 is applied, flowed and knitted, and then insulated from the polysilicon film of a subsequent process. A second step of depositing an ion implanted oxide film 9 for deposition, and a polysilicon film ion-implanted after the second step to form a gate electrode 10 of the thin film transistor to a predetermined size, and a thin film transistor And a third step of forming the channel polysilicon film 12 with the polysilicon film ion-implanted after the gate oxide film 11 of the gate is formed, and a method for improving the characteristics and uniformity of the thin film transistor. will be.

Description

박막트랜지스터의 특성 및 균일성 개선 방법How to improve the characteristics and uniformity of thin film transistors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 SRAM평면도,1 is a plan view of an SRAM according to the present invention;

제2도는 제1도의 A-A′선을 따른 제조 공정 단면도.2 is a cross-sectional view of the manufacturing process along the line A-A 'of FIG.

Claims (3)

박막트랜지스터의 특성 및 균일성 개선 방법에 있어서, 반도체 기판에 형성된 웰(well)(1)상에 소정의 간격으로 필드 산화막(소자 분리 절연막)(2)을 형성하고 벌크 박막트랜지스터의 게이트 산화막(3)과 이온 주입된 폴리실리콘막을 소정의 크기로 형성하여 벌크 트랜지스터의 게이트 전극(4)을 형성한 다음 IPO(5)를 전면에 증착하고 폴리실리콘막(6)을 소정의 크기로 형성하는 제1단계, 상기 제1단계 후에 산화막(7)을 증착하고 불순물 주입된 산화막(또는 BPSG)(8)을 도포하여 플로우(flow) 시키고 평탄화한 후에 후속 공정의 폴리실리콘막과 절연을 위한 이온 3주입되지 않은 산화막(9)를 증착하는 제2단계, 및 상기 제2단계 후에 이온 주입되는 폴리실리콘막을 증착하여 소정의 크기로 박막트랜지스터의 게이트 전극(10)을 형성하고 박막트랜지스터의 게이트 산화막(11)을 형성한 후에 이온 주입되는 폴리실리콘막으로 채널 폴리실리콘막(12)을 형성하는 제3단계를 포함하여 이루어 지는 것을 특징으로 하는 박막트랜지스터의 특성 및 균일성 개선 방법.In the method for improving the characteristics and uniformity of a thin film transistor, a field oxide film (element isolation insulating film) 2 is formed at a predetermined interval on a well 1 formed in a semiconductor substrate, and a gate oxide film 3 of a bulk thin film transistor is formed. ) And an ion implanted polysilicon film to a predetermined size to form a gate electrode 4 of the bulk transistor, and then deposit the IPO 5 on the front surface and form the polysilicon film 6 to a predetermined size. After the first step, an oxide film 7 is deposited, and an impurity implanted oxide film (or BPSG) 8 is applied, flowed, and planarized before implanting three ions for insulation with the polysilicon film in a subsequent process. The second step of depositing the oxide film 9 and the polysilicon film ion-implanted after the second step are formed to form the gate electrode 10 of the thin film transistor in a predetermined size, and the gate oxidation of the thin film transistor. And a third step of forming a channel polysilicon film (12) with a polysilicon film ion-implanted after forming the film (11). 제1항에 있어서, 상기 제2단계의 평탄화는 산화막(또는 BPSG)(8)을 도포하여 플로우(flow)시킨후 에치백(etch back)하여 평탄화를 이루는 제4단계를 더 포함하는 것을 특징으로 하는 박막트랜지스터의 특성 및 균일성 개선 방법.2. The method of claim 1, wherein the planarization of the second step further comprises a fourth step of applying an oxide film (or BPSG) 8 to form a flow and then etching back to achieve planarization. Method for improving the characteristics and uniformity of the thin film transistor. 제1항에 있어서, 상기 제2단계의 평탄화는 완전 평탄화 또는 하층 단차를 부분적으로 완화 시키는 부분 평탄화인 것을 특징으로 하는 박막트랜지스터의 특성 및 균일성 개선 방법.The method of claim 1, wherein the planarization of the second step is partial planarization which partially relaxes the entire planarization or the lower layer step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920019827A 1992-10-27 1992-10-27 Improving method of characteristic and uniformity for thin film transistor KR950011785B1 (en)

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KR1019920019827A KR950011785B1 (en) 1992-10-27 1992-10-27 Improving method of characteristic and uniformity for thin film transistor

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Application Number Priority Date Filing Date Title
KR1019920019827A KR950011785B1 (en) 1992-10-27 1992-10-27 Improving method of characteristic and uniformity for thin film transistor

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KR940010311A true KR940010311A (en) 1994-05-26
KR950011785B1 KR950011785B1 (en) 1995-10-10

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