KR970054257A

KR970054257A - Low doping drain thin film transistor and its manufacturing method

Info

Publication number: KR970054257A
Application number: KR1019950047088A
Authority: KR
Inventors: 용창범; 조성갑
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-12-06
Filing date: 1995-12-06
Publication date: 1997-07-31

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자 제조 방법.Semiconductor device manufacturing method.

2. 발명이 해결하려고 하는 기술적 과제.2. The technical problem that the invention is trying to solve.

종래의 저도핑 드레인 구조의 박막 트랜지스터를 제조하는 방법은 측벽 스페이서 산화막을 형성하는 단계 및 두번의 이온주입 단계를 포함하므로 공정이 복잡하다는 단점을 보완하고자 함.The conventional method for manufacturing a thin film transistor having a low doped drain structure is intended to compensate for the disadvantage of the complicated process because it includes forming a sidewall spacer oxide film and two ion implantation steps.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

게이트 전극을 양단의 두께가 얇게 형성하므로써, 측벽 스페이서를 형성하는 공정을 수행하지 않고 한 번의 이온주입 공정으로 저도핑 드레인 구조를 형성할 수 있는 박막 트랜지스터를 제조하고자 함.By forming a gate electrode with a thin thickness at both ends, a thin film transistor capable of forming a low doped drain structure in one ion implantation process without performing a process of forming sidewall spacers is intended.

4. 발명의 중요한 용도4. Important uses of the invention

저도핑 드레인 구조의 박막 트랜지스터를 제조하는데 이용됨.Used to manufacture thin film transistors with low doped drain structure.

Description

Low doping drain thin film transistor and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 저도핑 드레인 구조의 박막 트랜지스터 제조 방법의 한 실시예에 따른 공정도.2A to 2D are process diagrams according to one embodiment of a method for manufacturing a thin film transistor having a low doped drain structure according to the present invention.

Claims

A method of manufacturing a thin film transistor having a low doped drain structure, the method comprising: forming a gate oxide layer on a semiconductor substrate and depositing polysilicon for the gate electrode; and a first photoresist pattern having an open doped drain region and a source / drain region. Forming a portion of the polysilicon using the first photoresist pattern as an etch barrier, removing the remaining photoresist, and forming a second photoresist pattern for forming a gate electrode; Using a photoresist pattern as an etch barrier to etch the polysilicon and gate oxide layer for the gate electrode, and to perform ion implantation to remove residual photoresist and form source / drain regions. A method of manufacturing a thin film transistor having a drain structure.

A thin-film transistor having a low doped drain structure, comprising: a gate electrode having a step thickness smaller than a center thickness, a gate oxide film formed under the gate electrode, and source / drain formed on semiconductor substrates on both sides of the gate electrode; A thin film transistor having a low doped drain structure comprising a region and a low doped drain region formed under a stepped portion of both ends of the gate electrode.

※ Note: The disclosure is based on the initial application.