KR970002404B1 - Error detection of digital systems - Google Patents

Abstract

An apparatus for detecting malfunction of a digital information processing system is provided to protect damage of the system when an error is occurred in its input/output device. The apparatus comprises a processor for performing multiple programs with controlling input/output ports; a task time counter for producing a signal representing abnormal state of the processor if a task performing count time value excesses a preset level; a first storage means for storing the output data designated by a user; a second storage means for storing the input/output mode data designated by a user; a port driving means for outputting the data stored in the first storage means according to the logical value of the input/output mode data stored in the second storage means and that of the abnormal state detect signal; and an input restriction means for cutting off the input data being sent from the input/output port to the processor in response to input of the abnormal state detect signal.

Description

Abnormal state detection device of digital system

1 is a circuit diagram of an abnormal state detection apparatus of a digital system according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: timer 12, 14: first and second flip flop

16: NOR gate 18: 3 state inverter

20: OR gates 22 to 26: first to third registers

28: multiplexer 30: input / output port

32: buffer circuit 34: NMOS transistor

36: PMOS transistor

The present invention relates to an abnormal state detection apparatus of a digital system that can prevent damage to a system by controlling an input / output device when an abnormal state occurs in a processor included in the digital information processing system.

A typical digital system includes at least one input means for inputting digital information, at least one output device for outputting processed information, and a processor for processing the input digital information. The processor calculates and processes the digital information input by the user and controls the system. When the abnormal state occurs in the system, the processor controls the input / output device to solve the abnormal state of the system.

The abnormal state detection device counts the period of the event signal from the processor to detect the congestion of the program of the processor. The abnormal state detection device generates the interrupt signal of the specific logic and supplies the generated interrupt signal when the width of the event signal indicating that the processor is processing digital information exceeds a predetermined period. Then, the processor processes the abnormal state of the system according to the interrupt program instead of the normal program currently being executed. The congestion of the program of the processor is generated because the input / output device is not normally driven by the noise signal from the power supply device or the noise signal from the outside.

However, the processor cannot handle the abnormal state of the system when the abnormal state of the system is due to the abnormal state of the input / output device to be driven for the processing of the abnormal state. In addition, the processor causes the digital system to be burned or damaged due to the failure of the system.

As a result, the conventional abnormal state detection apparatus of the digital system can detect the congestion of the program of the processor and notify the processor of the detected abnormal state, but the problem of damaging the system because it cannot control the input / output device to be driven. Was hugging.

Accordingly, an object of the present invention is to provide an abnormal state detection apparatus of a digital system that can prevent damage to a system by controlling an input / output device when an abnormal state occurs in a processor included in the digital system.

In order to achieve the above object, the digital system fault condition detecting apparatus of the present invention counts the time for which the processor performs a task according to a program and counts the work time for generating the fault condition detection signal when the counted value exceeds the limit time. Means, first storage means for storing user-specified output data, second storage means for storing user-specified input / output mode data, the abnormal state detection signal and the input / output mode stored in the second storage means. Input / output driving means for outputting the data stored in the first storage means to the input / output device according to the logic value of the data, and an input limit for cutting off the input data to be transmitted from the input / output device to the processor by the abnormal state detection signal; It is characterized by having a means.

Hereinafter, an apparatus for detecting an abnormal state of a digital system according to an embodiment of the present invention will be described in detail with reference to FIG.

Referring to FIG. 1, a timer 10 for inputting a click pulse string from a first control line 11 and a first reset signal from a second control line 13, a second control line 13, and a third control signal may be used. An abnormal state detection apparatus of a digital system according to an embodiment of the present invention having an OR gate 20 for inputting a first reset signal and a second reset signal from the control line 15 is described. The first reset signal is generated as a result of OR operation of a master reset signal generated when the power is turned on and an event reset signal generated each time a processor (not shown) starts a new task. The second reset signal is a reset signal generated by the processor when an interrupt signal indicating an abnormal state is generated. The timer 10 has a high logic logic signal at its output terminal Q by a high logic first reset signal from the second control line 13 applied to its proset terminal PR. Occurs. The timer 10 generates a low logic overflow signal when the number of clock pulses input from the first control line 11 to its clock terminal CK exceeds a predetermined number. In addition, the timer 10 supplies the low logic overflow signal to the clock terminals CK of the first flip-flop 12 and the second flip-flop 14. The OR gate 20 ORs the first and second reset signals from the second and third control lines 13 and 15 and ORs the ORed reset signals to the first and second flips. The reset terminal R of the flops 12 and 14 is supplied. The first flip-flop 12 and the second flip-flop 14 are initialized by the OR-operated reset signal having high logic from the OR gate 20. Then, the first flip-flop 12 is a high logic logic signal supplied from the first power supply (Vcc) to its input terminal (D) at the falling edge of the overflow signal from the timer (10). The output terminal Q is transmitted to the input terminal D of the second flip-flop 14. Further, the second flip-flop 14 receives a high logic logic signal from the output terminal Q of the first flip-flop 12 at the rising edge of the overflow signal from the timer 10. It transmits to the line 19 via its output terminal Q. The line 19 is connected to an interrupt terminal of a processor (not shown) and transmits a high logic logic signal from the output terminal Q of the second flip-flop 14 to the processor.

The abnormal state detection device of the digital system includes the first to third registers 22, 24, and 26 connected to the data bus 17, and the line from the output terminal Q of the second flip-flop 14. A NOR gate 16 for inputting a logic signal via (19) is further provided. The first to third registers 22 to 26 are read control terminals RE for inputting a read enable signal, a write enable signal and data from the data bus 17, a write control terminal WE, And an input terminal D, respectively. The first register 22 has its input port D from the data bus 17 by a write enable signal of a predetermined logic value (for example, high or low logic) to the write control terminal WE. 2bit output level mode data is stored in itself. The first register 22 supplies the 2-bit output level mode data stored therein to the first input port DP1 of the multiplexer 28. Further, when the read enable signal of a predetermined logic value is applied from the data bus 17, the first register 22 stores the 2-bit output level mode data stored in the data bus 17. Output to When the write enable signal of a predetermined logic value is applied from the data bus 17, the second register 24 has a one-bit supply from the data bus 17 to its input terminal D. The input / output mode selection data is stored in itself, and the stored input / output mode selection data is supplied to the first selection terminal S1 of the multiplexer 28 via its non-inverting output terminal Q. When the read enable signal of a predetermined logic value is applied, the second register 24 outputs the input / output mode selection data stored therein to the data bus 17. The third register 26 has a two-bit supply to its input port D from the data bus 17 by a write enable signal of a predetermined logic value supplied to its write control terminal WE. The output level mode data is stored in itself, and the two-bit output level mode data stored therein is supplied to the second input port DP2 of the multiplexer 28. The third register 26, when a read enable signal of a predetermined logic value is applied from the data bus 17, transfers the 2-bit output level mode data stored therein to the data bus 17. Output The 2-bit output level mode data stored in the first register 22 is data to be output to the congestion and input / output ports of the program, and its logical value is specified by the user. The output level mode data stored in the third register 16 is output data processed by a processor that operates normally.

The multiplexer 28 supplies input / output mode selection data from the non-inverting output terminal Q of the second register 24 and a logic value of a logic signal from the output terminal Q of the second flip-flop 14. Therefore, the output level mode data supplied to both input ports DP1 and DP2 is selectively outputted or cut off. When the input / output mode selection data has a logic value of 0, the multiplexer 28 is connected to its output terminals Q1 and Q2 independently of the output level mode data supplied to the input ports DP1 and DP2. A high impedance signal is output to the gates of the connected NMOS and PMOS transistors 34 and 36. In contrast, when the input / output mode selection data has a logic value of 1, the multiplexer 28 selects the first signal according to the logic state of the logic signal applied from the line 19 to its second selection terminal S2. The 2-bit output level mode data from the first or third registers 22 or 26 is applied to the gates of the NMOS and PMOS transistors 34 and 36. In detail, when the logic signal from the line 19 has a logic value of 1, the multiplexer 28 outputs the 2-bit output level mode data from the first register 22 to the NMOS and PMOS. Transfers to the gates of transistors 34 and 36. On the contrary, when the logic signal from the line 19 has a logic value of 0, the multiplexer 28 outputs the 2-bit output level mode data from the third register 26 to the NMOS and PMOS transistors. 34, 36 to the gate side. The NMOS and PMOS transistors 34 and 36 are configured such that the input / output port 30 maintains a high impedance state when a high impedance signal from both output terminals Q1 and Q2 of the multiplexer 28 is input. Thus, the input / output port 30 functions as an input port. On the contrary, when 10 or 1 output level mode data from both output terminals Q1 and Q2 of the multiplexer 28 is input, the NMOS and PMOS transistors 34 and 36 enter the input / output port 30. Allows you to function as an output port for sending high or low output data. The buffer circuit 32 including the NMOS and PMOS transistors 34 and 36 connected in series between a first power source Vcc and a second power source Vss includes the input / output port 30 and the multiplexer 28. ) Function as a buffer.

In addition, the abnormal state detection device of the digital system includes a NOR gate 16 connecting both input terminals to the input / output port 30 and the line 19, and an inverted output terminal (/ Q) of the second register 24. And a three-state inverter 18 for inputting the inverted input / output mode selection data from the side to the control terminal thereof. The NOR gate 16 inverts the input data from the input / output port 30 and transmits the inverted data to the tri-state inverter 18. In addition, when a high logic logic signal is input from the line 19, the NOR gate 16 outputs a low logic logic signal regardless of the input data from the input / output port 30 to the tri-state inverter 18. To feed. The three-state inverter 18 is driven by the inverted input / output mode selection data having high logic. The three-state inverter 18 inverts the logic signal from the NOR gate 16 and transmits the inverted logic signal to the data bus 17.

As described above, the abnormal state detection apparatus of the digital system of the present invention provides an advantage that the input / output port can be operated in a user-specified input and output mode when an abnormal state of the system is detected. Due to the above advantages, the abnormal state detection apparatus of the digital system of the present invention provides an advantage of outputting a user-specified output data via an input / output port when an abnormal state of the system is detected. In addition, the present invention provides an advantage of preventing damage to the system by controlling the input and output port.

Claims (5)

A digital system having an input / output port for inputting and outputting data, and a processor for executing a plurality of programs for processing data and controlling the input / output port, the digital system comprising: Work time counting means for generating an abnormal state detection signal when the counted value exceeds the limit time, first storage means for storing the output data specified by the user, and second input for storing the input / output mode data specified by the user Port driving means for outputting data stored in the first storage means to the input / output port according to a storage means, a logic value of the abnormal state detection signal and the input / output mode data stored in the second storage means, and the abnormal state. Input to be transmitted from the input / output port to the processor by the detection signal An abnormal state detection device comprising an input limiting means for blocking data. 2. The apparatus of claim 1, wherein the port driving means selects the output data from the first storage means and the output data from the processor toward the input / output port according to the abnormal state detection signal and the logic value of the input / output mode data. And multiplexing means for outputting the data to and outputting the output data to the input / output port. The output data stored in the first storage means and the output data from the processor have three-state logic, wherein the port driving means outputs the multiplexing means so that the input / output port outputs the output data. An abnormal state detection device, characterized in that it further comprises a buffer means to be in the same logical state as the logic value of the. The logic computing device of claim 1, wherein the input limiting means performs a logic operation on the input data from the input / output port and the abnormal state detection signal from the working time counting means, and transmits the logical operation signal to the processor. Abnormal state detection device, characterized in that provided. The control switch means according to claim 4, wherein said input limiting means is adapted to switch said logically operated signal to be supplied from said logic operation element to said processor by a logic value of input / output mode data stored in said second storage means. An abnormal state detection device, characterized in that further provided.