JP2899610B2 - Malfunction protection circuit of CPU clock selection supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU used for controlling various electronic devices such as a camera and a radio cassette.
And a circuit for protecting a CPU clock selection / supply circuit for selectively supplying a clock signal to a malfunction from malfunctioning.

[0002]

2. Description of the Related Art In order to control various electronic devices such as a camera and a radio cassette, a CPU called a microprocessor or a microcontroller is widely used.
In general, this type of CPU is often configured to be able to operate under a plurality of clock signals of different speeds. In some cases, a user operates the external microswitch or the like to select a plurality of clock signals to be supplied to the CPU, but the CPU itself receiving such a clock signal appropriately selects the clock signal according to the processing content. In some cases, the configuration can be selected.

FIG. 7 shows an example of the configuration of a clock selection / supply circuit for the CPU itself to select one of a plurality of clock signals in a case where there are two clock signals.
As shown in FIG. 2, two clock supply circuits 11 and 12 are arranged in front of the CPU 10, and the switch 13 is switched based on a command from the CPU 10 to change the clock signal CK1 or CK.
One of the two can be selectively received. In the case of a CPU that operates with a built-in battery or the like, the configuration is such that the operation of the necessary clock supply circuit can be started and the operation of the unnecessary clock supply system can be stopped at any time for the purpose of saving power consumption. CPU 10 sends on / off control signals en1 and en2 for instructing on / off control registers 14a and 14b provided corresponding to circuits 11 and 12 to start / stop the operation.
Are writable via the control bus 16.

In the clock signal selection and supply circuit shown in FIG.
A selection control register 15 is provided for the PU 10 to select a clock signal via the control bus 16, and a selection command “sel” of “1” / “0” can be written to this control register. Also, the CPU 10 determines which clock supply circuit is currently operating by the control bus 1.
6, each clock supply circuit holds an N-bit counter and a carry signal C output from the N-bit counter, so that N clocks can be detected after the operation of the clock supply circuit is started. The flag FLG1, which rises from "0" to "1" when the cycle elapses
A flip-flop that outputs FLG2 is provided.

[0005]

In the conventional clock signal selection and supply circuit shown in FIG. 7, the selection of a clock signal by switching a switch and the ON / OFF of each clock supply circuit are all performed under the control of the CPU. It has a configuration. For this reason, the output of the clock supply circuit that is not operating is erroneously selected or the operation of the clock supply circuit that is outputting the selected clock signal is stopped based on a runaway in the program of the CPU or malfunction of hardware. If the operation is stopped by mistake, the clock signal is not supplied to the CPU from that moment, which causes a problem that the CPU becomes inoperable.

Normally, an inoperable state caused by a CPU runaway or hardware malfunction is automatically detected by a watchdog timer or the like, and can be automatically recovered by an automatic reset or the like. However, if the supply of the clock signal to the CPU is erroneously stopped, the self-diagnosis and automatic recovery functions such as the watchdog timer are also stopped at the same time, so the possibility of automatic recovery is completely lost. There is a problem that the inoperable state is maintained until the user notices this and performs a manual reset or the like.

[0007]

According to the present invention, a malfunction protection circuit for a CPU clock selection supply circuit according to the present invention is designed to select a clock signal which does not have a clock selection command supplied from the CPU. An erroneous selection protection circuit that changes the selection command to select a signal and supplies the selection control register and an on / off control signal supplied from the CPU outputs a clock signal being selected as a CPU clock signal. When the operation of the clock supply circuit is to be stopped, at least one of an erroneous stop protection circuit for changing the on / off control signal and supplying the same to the on / off control register so as to continue the operation is provided. ing.

[0008]

The erroneous selection protection circuit recognizes an existing clock signal by monitoring a flag indicating the presence or absence of a clock signal output from each clock supply circuit, and the CPU erroneously outputs another clock signal for some reason. When the user wants to make a selection, the selection command is changed so as to select an existing clock signal, and is supplied to the selection control register. Further, the false stop protection circuit identifies the currently selected clock supply circuit by monitoring the clock signal selection command being output from the selection control register, and
If the user wants to stop the operation of the clock supply circuit being selected by mistake for some reason, the on / off command is changed and supplied to the on / off control register so that the operation is continued.

By providing at least one of the above-mentioned erroneous selection protection circuit and the erroneous stop protection circuit, preferably both, the CP
A situation in which the CPU clock signal is cut off due to a malfunction of U is effectively avoided.

[0010]

FIG. 1 shows a configuration of a malfunction protection circuit of a clock signal selection / supply circuit according to an embodiment of the present invention. The clock signal selection / supply circuit to be protected and a CPU clock signal received from the clock selection / supply circuit. 10 is a block diagram shown together with a CPU, 10 is a CPU, 11 and 12 are clock supply circuits, 13 is a switch, and 14a and 14b are ON / OFF.
An OFF control register, 15 is a selection control register, and 20 is a malfunction protection circuit. The malfunction protection circuit 20 includes a malfunction selection protection circuit 21 and a malfunction stop protection circuit 22.

The clock supply circuit 11 includes an AND gate 1
1a, an inverter 11b, an N-bit counter 11c, and a flip-flop 11d, receives a clock signal ck1 'supplied from an external crystal oscillator or the like to an external clock input terminal 17, and receives an on / off command EN.
The clock signal CK1 to the CPU 10 is supplied to one input terminal of the switch 13 by passing through the AND gate 11a and the inverter 11b which are selectively opened by 1. The N-bit counter 11c counts the clock signal CK1 output from the inverter 11b, and upon counting 2 ^N clock signals, overflows and outputs the carry signal C. Flip-flop 1
In 1d, the flag FLG1, which indicates the presence or absence of the clock signal CK1, rises from "0" to "1" by holding the carry signal. The flag FLG1 is set to "0" when the on / off command EN1 falls to "0".
Initially set to

The clock supply circuit 12 has the same configuration as the above-described clock supply circuit 11, and receives a clock signal ck2 'supplied to an external clock input terminal 18, although not shown in the figure to avoid complication. The clock signal CK2 to the CPU 10 is supplied to the other input terminal of the switch 13 by passing through a built-in AND gate selectively opened by the on / off command EN2 and an inverter. A flag FLG2 indicating the presence / absence of the clock signal CK2 is provided by a built-in N-bit counter for counting the clock signal CK2 and a flip-flop for holding the carry signal C generated by the overflow.
Rises from “0” to “1”. This flag F
LG2 is initialized to "0" when the on / off command EN2 falls to "0". The clock signals CK1 and CK2 may have different normal periods.

When the ON / OFF command EN1 held in the ON / OFF control register 14a becomes "1", the clock supply circuit 11 turns on the built-in AND gate 11a to start the operation of supplying a clock signal. OFF command EN1
Becomes "0", the built-in AND gate 11a is closed to stop the clock supply operation. At the same time, the N-bit counter 11c and the flip-flop 11d are cleared. Similarly, when the on / off command EN2 held in the on / off control register 14b becomes “1”, the clock supply circuit 12 turns on the built-in AND gate to start the clock signal supply operation and turn on / off. When the command EN2 becomes "0", the built-in AND gate is closed to stop the clock supply operation, and the flip-flop receiving the built-in N-bit count and its carry signal is cleared. The N-bit counters in the clock supply circuits 11 and 12 output an unstable clock signal immediately after the start of the clock supply.
0, the presence of the corresponding clock signals CK1 and CK2 is determined by the flag FLG after the elapse of N cycles.
1, for displaying by the rising of FLG2 from "0" to "1".

The CPU 10 includes clock supply circuits 11, 1
By reading the flags FLG1 and FLG2 output from the control bus 16 via the control bus 16, it is possible to recognize which clock signal is present, and the control bus 16 and the erroneous selection protection circuit 2
The switch 13 is switched by writing a 1-bit selection command (sel) to the selection control register 15 via 1 to select one of the clock signals CK1 and CK2 as the CPU clock signal. Further, the CPU 10 reads the clock selection command SEL via the control bus 16 to recognize which of the outputs of the clock supply circuits 11 and 12 is being selected as the CPU clock signal. By writing 1-bit ON / OFF commands (en1, en2) to the ON / OFF control registers 14a, 14b via the circuit 22, the operation of the necessary clock supply circuit is started or continued, or unnecessary clock supply is performed. Stop the operation of the circuit.

False selection protection circuit 2 in malfunction protection circuit 20
Reference numeral 1 denotes a circuit for protecting the output of the clock supply circuit whose operation is stopped due to a program runaway of the CPU 10 or a malfunction of hardware from being erroneously selected as a CPU clock signal. As shown in FIG. 2, the erroneous selection protection circuit 21 includes an AND gate 31,
32, 33, an OR gate 34, and an inverter 35. The presence / absence of the clock signal CK1 is indicated by “1” / “0” of the flag FLG1, and
The presence / absence of the clock signal CK2 is indicated by “1” / “0” of the flag FLG2. In addition, the selection of the clock signal CK1 by the CPU 10 is instructed by the selection command sel “0”, and the selection command sel “1” causes CP
The selection of the clock signal CK2 by U10 is instructed.
The signal SEL is a protected selection command output from the erroneous selection protection circuit 21. Selection of the clock signal CK1 is commanded by "0", and selection of the clock signal CK2 is commanded by "1". Is done.

FIG. 3 shows the relationship between input and output signals realized by the erroneous selection protection circuit 21 of FIG. Referring to FIG. 3, when the flag FLG1 is "1" and the flag FLG2 is "0", that is, when the clock signal CK1
When only the command exists, the selection command s from the CPU 10
The selection command SEL ′ becomes “0” irrespective of the content of the signal “el”, and this is held in the selection control register 15 as the selection command SEL.
1 is instructed. Conversely, the flag FLG1
Is “0” and the flag FLG2 is “1”, that is, when only the clock signal CK2 exists, the CPU
The selection command SEL 'becomes "1" irrespective of the content of the selection command sel from the selector control register sel.
Is held as the selection command SEL, the selection of the only existing clock signal CK2 is commanded. When both the flag FLG1 and the flag FLG2 are “1”, that is, when both the clock signals CK1 and CK2 are present, the selection command SEL ′ according to the content of the selection command sel from the CPU 10 is output, and this is output. The selection control register 15 holds the selection command SEL.

As described above, the clock signal CK1 or CK
If only one of the clock signals exists, a selection command se from the CPU 10 selects the only clock signal that exists.
Since 1 is changed, it is effectively prevented that the selection command from the CPU 10 erroneously selects a non-existent clock signal due to a program runaway or hardware malfunction.

Erroneous stop protection circuit 2 in malfunction protection circuit 20
Reference numeral 2 denotes a circuit for protecting the operation of the clock supply circuit which is supplying the CPU clock signal from being erroneously stopped due to a program runaway of the CPU 10 or a malfunction of hardware. This false stop protection circuit 2
2 includes OR gates 41 and 42 and an inverter 43, as shown in FIG. “1” for en1 /
The start / stop of the operation of the clock supply circuit 11 is instructed by the CPU 10 by “0”, and “1” /
The CPU 10 instructs start / stop of the operation of the clock supply circuit 12 by “0”.

FIG. 5 shows the relationship between input and output signals realized by the false stop protection circuit 22 of FIG. Referring to FIG. 5, when the selection command SEL is “0”, that is, when the clock signal CK1 is being selected as the CPU clock signal, the on / off command en from the CPU 10 is provided.
The ON / OFF command EN1 'is "1" regardless of the contents of l.
The ON / OFF command EN1 to the clock supply circuit 11 becomes "1" by being held in the ON / OFF control register 14a. Further, the on / off command EN2 ′ (and thus EN2) for the clock supply circuit 12 that does not supply the CPU clock signal is changed according to the on / off control command from the CPU 10.

Conversely, when the selection command SEL is "1", that is, when the clock signal CK2 is being selected as the CPU clock signal, the on / off command e from the CPU 10 is output.
The on / off command EN2 'becomes "1" irrespective of the content of n2, and is held in the on / off control register 15a, so that the on / off command EN2 for the clock supply circuit 12 becomes "1". The on / off command EN1 for the clock supply circuit 11 to which the CPU clock signal is not supplied is changed according to the on / off control command from the CPU 10.

As described above, the ON / OFF command from the CPU 10 to the clock supply circuit supplying the CPU clock signal is changed by the erroneous stop protection circuit 22 so that the clock supply circuit can continue to supply the CPU clock signal. You. As a result, an unexpected situation in which the on / off command from the CPU 10 erroneously stops the operation of the clock supply circuit during the supply of the CPU clock signal due to a program runaway or a hardware malfunction may be effectively prevented. .

FIG. 6 is a circuit diagram showing an example of the configuration of the abnormal operation detection circuit added to the circuit of FIG. The abnormal operation detecting circuit includes exclusive OR gates 51, 52, 53
, An OR gate 54, a flip-flop 55, and an AND gate 56. The exclusive OR gate 51 determines that a mismatch has occurred between the selection command sel issued by the CPU 10 and the selection command actually output from the erroneous selection protection circuit 21, that is, that the selection protection circuit 21 has functioned due to some abnormality. Upon detection, the output rises from "0" to "1". The exclusive OR gate 52 is provided with an on / off command enl issued by the CPU 10.
When it is detected that a mismatch has occurred with the ON / OFF command EN1 actually output from the erroneous stop protection circuit 22, the output is raised from "0" to "1". Further, the exclusive OR gate 53 is provided with an on / off command en issued by the CPU 10.
2 is detected, the output is raised from “0” to “1” when a mismatch between the ON / OFF command EN2 actually output from the false stop protection circuit 22 is detected.

The mismatch detection signal "1" output from one of the exclusive OR gates 51, 52, 53 is supplied to a flip-flop 55 through an OR gate 54, and is supplied to the CPU.
10 is held in the flip-flop 55 by a write command W issued via the control bus 16, and is supplied to the control bus 1 as a signal ER indicating occurrence of abnormal operation due to some cause.
6 is output. This signal ER is generated by an interrupt enable signal IN output on the control bus 16 each time the CPU 10 issues a selection command sel or on / off commands en1 and en2.
Through AND gate 56 opened by TEN, C
An interrupt request INT to the PU 10 is generated. The CPU 10 that has received the interrupt request INT executes an appropriate self-diagnosis routine to determine the cause of the abnormal operation in which the mismatch has occurred, and changes internal data and the like as necessary. Thus, by adding the circuit of FIG. 6, the fact that the malfunction protection circuit 20 has functioned can be determined by the CPU.
10 and the opportunity to make the necessary diagnosis
PU10.

In the above, the configuration in which both the erroneous selection protection circuit 21 and the erroneous stop protection circuit 22 are preferably provided has been exemplified. However, by providing only one of the above protection circuits for the purpose of reducing the circuit scale, etc., the probability of occurrence of a malfunction can be reduced as compared with the conventional circuit.

Although the present invention has been described with respect to the case where there are two clock supply circuits, the present invention can be generally applied to a case where there are three or more clock supply circuits.

[0026]

Since the malfunction protection circuit of the CPU clock selection supply circuit according to the present invention has the above-described configuration, the CPU clock signal is cut off due to a runaway in the CPU program or malfunction of the hardware circuit. The situation is effectively avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a malfunction protection circuit according to an embodiment of the present invention, together with a clock selection supply circuit to be protected and a CPU receiving a clock signal from the selection supply circuit;

FIG. 2 is a circuit diagram showing an example of a configuration of an erroneous selection protection circuit 21 of FIG.

FIG. 3 is a conceptual diagram showing a logical relationship of the logic circuit diagram of FIG. 2;

FIG. 4 is a circuit diagram showing an example of a configuration of an erroneous stop protection circuit 22 of FIG. 1;

FIG. 5 is a conceptual diagram showing a logical relationship of the logic circuit of FIG.

FIG. 6 is a circuit diagram showing an example of a configuration of an abnormal operation occurrence detection circuit added to FIG. 1;

FIG. 7 is a block diagram showing a configuration of a conventional clock selection supply circuit together with a CPU.

[Explanation of symbols]

 10 CPU 11,12 Clock supply circuit 14a, 14b ON / OFF control register 15 Selection control register 16 Control bus 20 Malfunction protection circuit 21 False selection protection circuit 22 False stop protection circuit

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 1/04-1/14

Claims (2)

(57) [Claims] 1. A CPU, a plurality of clock supply circuits each having an output terminal for a clock signal to be supplied to the CPU, and a clock signal supplied from the CPU to instruct each of the clock supply circuits to start / stop operation. An on / off control register for holding an on / off command, a clock presence / absence detection means for detecting the presence / absence of a clock signal at an output terminal of each clock supply circuit, and holding as a flag indicating the presence / absence of the clock signal, Switch means for selecting one of the output terminals and connecting to the clock signal input terminal of the CPU, and a selection control register for holding a selection command supplied from the CPU for instructing the switch means for the selection operation. A circuit for protecting the CPU clock selection supply circuit from malfunctioning, comprising: A clock signal that is provided at the previous stage and exists when there is an attempt to select a clock signal for which there is no selection command supplied from the CPU based on a combination of flags indicating the presence / absence of a clock signal held by the clock presence / absence detection means. An erroneous selection protection circuit that changes this selection command so as to select a clock signal and supplies it to the selection control register; and a selection command provided before the on / off control register and held in the selection control register. Based on the CPU
In order to stop the operation of the clock supply circuit that is outputting the clock signal selected by the on / off command supplied from the CPU, the on / off command is changed so that the operation is continued. A malfunction protection circuit for a CPU clock selection / supply circuit, comprising: one or both of a malfunction stop protection circuit supplied to the on / off control register. 2. The CPU according to claim 1, wherein at least one of the presence or absence of the change in the selection command supplied from the CPU and the presence or absence of the change in the on / off command supplied from the CPU is detected. CPU provided with means for notifying to CPU
Malfunction protection circuit for clock selection supply circuit.