KR960043031A - 반도체 소자의 금속배선 형성방법 - Google Patents

반도체 소자의 금속배선 형성방법 Download PDF

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KR960043031A
KR960043031A KR1019950012710A KR19950012710A KR960043031A KR 960043031 A KR960043031 A KR 960043031A KR 1019950012710 A KR1019950012710 A KR 1019950012710A KR 19950012710 A KR19950012710 A KR 19950012710A KR 960043031 A KR960043031 A KR 960043031A
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South Korea
Prior art keywords
aluminum alloy
metal wiring
temperature
silicon
semiconductor device
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KR1019950012710A
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English (en)
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KR0168162B1 (ko
Inventor
신찬수
곽노정
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김주용
현대전자산업 주식회사
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Priority to KR1019950012710A priority Critical patent/KR0168162B1/ko
Publication of KR960043031A publication Critical patent/KR960043031A/ko
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Publication of KR0168162B1 publication Critical patent/KR0168162B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53219—Aluminium alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법이 개시된다.
본 발명은 확산방지층 표면에 SiH4가스의 고온에서의 환원반응을 이용하여 실리콘 핵을 형성한 후, 실리콘 핵상에 실리콘 이온이 포함되지 않은 알루미늄 합금을 증착하여 금속배선을 형성한다.
따라서, 본 발명은 실리콘 핵과 알루미늄 이온이 고온에서 상호 격렬하게 확산되는 특성으로 콘택홀의 매립을 용이하게 하여 금속배선의 끊어짐 현상을 예방할 수 있어 반도체 소자의 신뢰성을 향상시킬 수 있다.

Description

반도체 소자의 금속배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a 내지 1e도는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위해 도시한 소자의 단면도.

Claims (8)

  1. 반도체 소자의 금속배선 형성방법에 있어서, 실리콘 기판상에 층간 절연막을 형성한 후, 상기 층간 절연막의 소정부분을 식각하여 접합부가 노출되는 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 상기 층간 절연막상에 확산방지층을 형성하는 단계와, 상기 확산방지층 표면에 실리콘 핵을 생성시키는 단계와, 상기 실리콘 핵상에 알루미늄 합금 중착공정을 실시하여 금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  2. 제1항에 있어서, 상기 실리콘 핵은 300내지 500℃ 온도와 200mTorr내지 5Torr반 응압력의 CVD 챔버안으로 300내지 500SCCM의 SiH4가스를 흘려주어 생성되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  3. 제1항에 있어서, 상기 알루미늄 합금은 실리콘 이온이 포함되지 않은 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  4. 제1항에 있어서, 상기 알루미늄 합금은 알루미늄에 구리가 0.5% 함유된 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  5. 제1항에 있어서, 상기 알루미늄 합금 증착공정은 상기 실리콘 핵상에 알루미늄 합금을 저온에서 원하는 두께의 일부만 증착한 후, 고온에서 나머지 두께가 되 도록 알루미늄 합금을 증착하여 금속배선을 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  6. 제5항에 있어서, 상기 알루미늄 합금의 저온증착시 온도는 50내지 100℃이고, 고온 증착시 온도는 450 내지 600℃인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  7. 제1항에 있어서, 상기 알루미늄 합금 증착공성은 실리콘 핵상에 알루미늄 합금을 저온에서 원하는 두께로 증착시킨 후, 증착된 알루미늄 합금을 고온에서 리플 로우시켜 금속배선을 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  8. 제7항에 있어서, 상기 알루미늄 합금의 저온증착시 온도는 50 내지 100℃이고, 고온리플로우시 온도는 500 내지 600℃인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950012710A 1995-05-22 1995-05-22 반도체 소자의 금속배선 형성방법 KR0168162B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950012710A KR0168162B1 (ko) 1995-05-22 1995-05-22 반도체 소자의 금속배선 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950012710A KR0168162B1 (ko) 1995-05-22 1995-05-22 반도체 소자의 금속배선 형성방법

Publications (2)

Publication Number Publication Date
KR960043031A true KR960043031A (ko) 1996-12-21
KR0168162B1 KR0168162B1 (ko) 1999-02-01

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