KR960039197A - 실리콘 산화막의 형성방법 및 반도체 장치의 제조방법 - Google Patents

실리콘 산화막의 형성방법 및 반도체 장치의 제조방법 Download PDF

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KR960039197A
KR960039197A KR1019960007624A KR19960007624A KR960039197A KR 960039197 A KR960039197 A KR 960039197A KR 1019960007624 A KR1019960007624 A KR 1019960007624A KR 19960007624 A KR19960007624 A KR 19960007624A KR 960039197 A KR960039197 A KR 960039197A
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depositing
silicon oxide
oxide film
gas
deposition
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다쓰오 스기야마
고사쿠 야노
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모리시다 요이치
마쯔시다 덴키 산교 가부시키가이샤
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Publication of KR960039197A publication Critical patent/KR960039197A/ko

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Abstract

실란가스 및 아산화잘소 가스를 주원료로 하는 감압 CVD법에 의하여 실리콘 산화막을 형성하는 방법을 제공한다. 실리콘 산화막의 퇴적조건은, 퇴적온도가 800℃ 이하, 상기 주원료 가스압력이 150Pa 이하, 상기 주원료의 가스유량이 반응용기 1리터당 25℃ 1기압의 표준조건에서 0.08리터/분 이하로 되도록 설정되어 있다.

Description

실리콘 산화막의 형성방법 및 반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 각 실시예에 관한 실리콘 산화막의 형성방법에 이용하는 감압 CVD 장치의 구성도.

Claims (12)

  1. 실란가스 및 아산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 실리콘 산화막을 산화막을 퇴적하는 실리콘 산화막 퇴적공정을 포함하고, 상기 실리콘 산화막 퇴적공정은, 퇴적온도가 800℃ 이하이면서 상기 주원료 가스유량이 반응용기 1리터당 25℃ 1기압의 표준조건에서 0.018리터/분 이하인 퇴적조건에 의하여 이루어지는 것을 특징으로 하는 실리콘 산화막의 형성방법.
  2. 제1항에 있어서, 상기 퇴적조건은, 상기 주원료의 가스압력이 170Pa 이하로 되는 조건을 더욱 포함하는 것을 특징으로 하는 실리콘 산화막의 형성방법.
  3. 제1항에 있어서, 상기 주원료의 가스압력이 125Pa 이하로 되는 조건을 더욱 포함하는 것을 특징으로 하는 실리콘 산화막의 형성방법.
  4. 실란가스 및 아산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 실리콘 산화막을 퇴적하는 실리콘산화막 퇴적공정을 포함하고, 상기 실리콘 산화막 퇴적공정은, 퇴적온도가 800℃ 이하이면서 상기 주원료 가스압력이100Pa 이상인 퇴적조건에 의하여 이루어지는 것을 특징으로 하는 실리콘 산화막의 형성방법.
  5. 제4항에 있어서, 상기 퇴적온도는 780℃ 이상이면서 800℃ 이하이고, 상기 주원료의 가스압력이 100Pa 이상인 것을 특징으로 하는 실리콘 산화막의 형성방법.
  6. 제4항에 있어서, 상기 퇴적온도는 740℃ 이상이면서 800℃ 이하이고, 상기 주원료의 가스압력은 125Pa 이상인 것을 특징으로 하는 실리콘 산화막의 형성방법.
  7. 저농도 불순물 영역이 형성된 반도체 기판 상에 게이트 전극을 형성하는 게이트 전극 형성공정과, 상기 반도체 기판 상에서의 상기 게이트 전극의 측면에 실리콘 산화막으로 이루어지는 측벽을 형성하는 측벽 형성 공정과, 상기 반도체 기판에 상기 게이트 전극 및 측벽을 마스크로 하여 불순물을 주입하여 고농도 불순물 영역을 형성하는 공정을 구비하고, 상기 측벽형성공정은, 상기 실리콘 산화막을, 실란가스 및 이산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 퇴적온도가 800℃ 이하이면서 상기 주원료 가스압력이 100Pa 이상인 퇴적조건으로 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  8. 불순물이 도프된 반도체 기판 상에 배선층을 형성하는 배선층 형성공정과, 상기 배선층 상에 실리콘 산화막으로 이루어지는 절연막을 퇴적하는 절연막 퇴적공정을 구비하고, 상기 절연막 퇴적공정은, 상기 실리콘 산화막을, 실란가스 및 아산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 퇴적온도가 800℃ 이하이면서 상기 주원료 가스압력이 100Pa 이상인 퇴적조건으로 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  9. 불순물이 도프된 반도체 기판 상에 실리콘 산화막으로 이루어지는 절연막을 퇴적하는 절연막 퇴적공정과, 상기 절연막 상에 도전성막을 퇴적하는 도전성막 퇴적공정과, 상기 도전성막에 대하여 상기 절연막을 에칭스토퍼로서 에칭하는 공정을 구비하고, 상기 절연막 퇴적공정은, 상기 실리콘 산화막을, 실란가스 및 아산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 퇴적온도가 800℃ 이하이면서 상기 주원료 가스압력이 100Pa 이상인 퇴적조건에서 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  10. 불순물이 도프된 반도체 기판 상에 플로팅 게이트가 되는 제1도 전성막을 퇴적하는 제1 도전성막 퇴적공정과, 상기 제1 도전성막 상에 실리콘 산화막으로 이루어지는 절연막을 퇴적하는 절연막 퇴적공정과, 상기 절연막 상에 콘트롤게이트가 되는 제2도전성막을 퇴적하는 제2도전성막 퇴적공정을 구비하고, 상기 절연막 퇴적공정은, 상기 실리콘 산화막을, 실란가스 및 아산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 퇴적온도가 800℃ 이하이면서 상기 주원료 가스압력이 100Pa 이상인 퇴적조건으로 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  11. 불순물이 도프된 반도체 기판 상에 플로팅 게이트가 되는 제1도전성막을 퇴적하는 제1도전성막 퇴적공정과, 상기 제1도전성막 상에 실리콘 산화막으로 이루어지는 절연막을 퇴적하는 절연막 퇴적공정과, 상기 절연막상에 콘트롤게이트가 되는 제2도전성막을 퇴적하는 제2도전성막 퇴적공정을 구비하고, 상기 절연막 퇴적공정은, 상기 실리콘 산화막을, 실란가스 및 아산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 퇴적온도 800℃이하이면서 상기 주원료 가스유량이 반응용기 1리터당 25℃ 1기압으로 표준조건에서 0.018리터/분 이하인 퇴적조건으로 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  12. ITO기판 상에 실리콘 산화막으로 이루어지는 절연막을 퇴적하는 절연막 퇴적공정과, 상기 절연막 상에소스 · 드레인 영역이 되는 도전성막을 형성하는 도전성막 형성공정을 구비하고, 상기 절연막 퇴적공정은, 상기실리콘 산화막을, 실란가스 및 아산화질소 가스를 주원료로 하는 감압 CVD법에 의하여, 퇴적온도가 800℃ 이하이면서 상기 주원료 가스압력이 100Pa 이상이 되는 퇴적조건으로 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960007624A 1995-04-12 1996-03-20 실리콘 산화막의 형성방법 및 반도체 장치의 제조방법 KR960039197A (ko)

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US6146724A (en) * 1994-06-06 2000-11-14 The University Of Tennessee Research Corporation One atmosphere uniform glow discharge plasma coating with gas barrier properties
JP2809183B2 (ja) * 1996-03-27 1998-10-08 日本電気株式会社 半導体記憶装置の製造方法
JP3818561B2 (ja) 1998-10-29 2006-09-06 エルジー フィリップス エルシーディー カンパニー リミテッド シリコン酸化膜の成膜方法および薄膜トランジスタの製造方法
EP1132959A1 (en) 2000-03-03 2001-09-12 STMicroelectronics S.r.l. A method of forming low-resistivity connections in non-volatile memories
CN103787325B (zh) * 2014-02-21 2016-08-24 中山大学 一种石墨烯器件的制备方法
CN104099581A (zh) * 2014-07-23 2014-10-15 国家纳米科学中心 一种氧化硅膜材料及其制备方法
CN115467021B (zh) * 2022-09-22 2023-12-12 粤芯半导体技术股份有限公司 低缺陷掺杂多晶硅及其制备方法

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US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4458407A (en) * 1983-04-01 1984-07-10 International Business Machines Corporation Process for fabricating semi-conductive oxide between two poly silicon gate electrodes
JPH02294040A (ja) * 1989-05-09 1990-12-05 Hitachi Ltd 半導体装置およびその製造方法
US5250468A (en) * 1990-02-05 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including interlaying insulating film
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