KR960036124A - Insulated gate semiconductor device and manufacturing method thereof - Google Patents

Insulated gate semiconductor device and manufacturing method thereof Download PDF

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KR960036124A
KR960036124A KR1019960004724A KR19960004724A KR960036124A KR 960036124 A KR960036124 A KR 960036124A KR 1019960004724 A KR1019960004724 A KR 1019960004724A KR 19960004724 A KR19960004724 A KR 19960004724A KR 960036124 A KR960036124 A KR 960036124A
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gate structure
conductor
layer
gate
dielectric material
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KR1019960004724A
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KR100368847B1 (en
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비.데이비스 로버트
수드하마 찬드라세크하라
케이.베이커 프랭크
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빈센트 비.인그라시아
모토로 라인코포레이티드
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

감소된 게이트 내 드레인 캐패시턴을 가진 절연 게이트 전계 효과 트랜지스터(10)와 그 제조방법이 제공되었다.An insulated gate field effect transistor (10) with a reduced in-gate drain capacitance and a method of manufacturing the same are provided.

도우펀트 웰(13)은 반도체 기판(11)내에 형성되고, 드레인 연장영역(25)은 도우펀트 웰(13)내에 형성된다. 산화물층(26)은 도우펀트 엘(13)상에 형성되고 400 옹스트롬 이상의 두께를 갖는다. 게이트 구조물(61)은 산호물층(26)의 얇은 부분 위의 게이트 션트부(32)와, 산화물층(26)의 얇게 되지 않은 부분 위의 전계 효과 트랜지스터(10)의 게이트 산화물을 형성하고, 얇게 되지 않는 부부은 전계 효과 트랜지스터(10)의 게이트 션트부(32)의 캐패시턴스를 낮춘다.The dopant well 13 is formed in the semiconductor substrate 11 and the drain extension region 25 is formed in the dopant well 13. The oxide layer 26 is formed on the dopant el 13 and has a thickness of 400 angstroms or more. The gate structure 61 forms a gate oxide of the field shunt portion 10 on the undifferent portion of the oxide layer 26 and the gate shunt portion 32 on the thin portion of the coral water layer 26, The capacitance of the shunt portion 32 of the field effect transistor 10 is lowered.

Description

절연 게이트 반도체 장치 및 그 제조방법Insulated gate semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명의 제1 실시예에 따른 공정 동안의 절연게이트 전계 효과 트랜지스터의 일부분의 확대 단면도.FIG. 1 is an enlarged cross-sectional view of a portion of an insulated gate field effect transistor during a process according to a first embodiment of the present invention. FIG.

Claims (3)

절연 게이트 반도체 장치의 제조 방법에 있어서, 주면(12)을 가진 제1도체형의 반도체 재료(13)를제공하는 단계와, 상기 주면(12)으로부터 상기 반도체 재료(13)내로 연장되는 제1도우펀트층(25)을 형성하는 단계와 제1 측부(36)와 제2 측부(37)를 가지며 유전재료(26)의 제1층의 제1부에 의해 주면(12)으로부터 이격된 제1게이트 구조물(61)의제1부(32)를 상기 유전 재료(26)의 상기 제1층의 제1부 상에 형성하는 단계와, 상기 제1게이트 구조물(61)의상기 제1부(32)의 상기 제1 측부(36)부근의 상기 반도체 재료(13)의 적어도 한 부분을 제1도체형의불순물로 도우핑하는 단계와. 상기 제1게이트 구조물(61)의 제1부(32)와 상기 제1주면(12) 사이에서 제1측부(36)로부터 연장되는 제1캐비티(35)를 형성하기 위해서, 유전재료(26)의 제1층의 제1부의 부분을 측방향으로 제거하는 단계와, 상기 제1게이트구조물(61)의 적어도 제1부(32)의 부근에 유전재료(26')의 제2층을 형성하는 단계와, 상기 제1캐비티(35)를 충전하는 유전재료(26')의 제2층에 의해 상기 제1게이트 구조물(61)의 제1 측부(36)로부터 이격된 제1게이트 구조물(61)의 제2부(58)를 형성하는 단계와 상기 제1게이트 구조물(61)의 제1부(32)의 제2측부(37) 부근 반도체 재료(13)의 부분(64)과, 상기 제1게이트 구조물(61)의 제2부(58)의 제2측부 부근의 반도체 재료(13)의부분 (63)을 도우핑하는 단계와, 상기 제1게이트 구조물(61)의 부분을 도우핑하는 단계를 포함하는 것을 특징으로하는 절연게이트 반도체 장치의 제조 방법A method of manufacturing an insulated gate semiconductor device comprising the steps of: providing a first conductor type semiconductor material (13) having a major surface (12); providing a first dowel extending from the main surface (12) Forming a punch layer 25 and a first side of the first gate 36 spaced from the major surface 12 by a first portion of the first layer of dielectric material 26, (32) of the structure (61) on a first portion of the first layer of the dielectric material (26), forming a first portion of the first portion (32) of the first gate structure Dipping at least a portion of the semiconductor material (13) near the first side (36) with an impurity of a first conductor type; A dielectric material 26 is deposited to form a first cavity 35 extending from the first side 36 between the first portion 32 of the first gate structure 61 and the first major surface 12. [ Lateral formation of a first layer of dielectric material 26 'in the vicinity of at least a first portion 32 of the first gate structure 61; (61) spaced from the first side (36) of the first gate structure (61) by a second layer of dielectric material (26 ') filling the first cavity (35) (64) of the semiconductor material (13) near the second side (37) of the first portion (32) of the first gate structure (61) and a second portion Doping a portion 63 of the semiconductor material 13 near the second side of the second portion 58 of the gate structure 61 and doping the portion of the first gate structure 61 And an insulated gate blanket Method of manufacturing a sieve device 절연 게이트 반도체 장치의 형성 방법에 있어서, 주면(12)을 가진 제1도체형의 반도체 재료(13)를 제공하는 단계와, 상기 주면(12)으로부터 상기 반도체 재료(13)내로 연장되는 제2도체형의 제1도우펀트층(25)을 형성하는 단계와, 상기 제1주면(12)상에 유전재료(26)의 제1층을 형성하는 단계와, 제1측부(36)와 제2측부(37)와 상면(45)을 가진 제1게이트 구조물(61)의 제1부(32)를 유전체 재료(26)의 제1층의 제1부상에 형성하는 단계와, 상기 제1게이트구조물(61)의 제1부(32)아래에서 상기 제1측부(36)로부터 연장되며 주면(12)의 일부를 노출시키느 제1캐비티(35)를 형성하는 단계와, 상기 제1게이트 구조물(61)의 제1부(32)의 제1측부(36)에 정렬된 제1도체형의 하나 이상의 강화된 도우펀트 영역(51)을 반도체 재료(13)내에 형성하는 단계와, 상기 제1게이트구조물(61)과 노출된 주면(12)의부분상에 유전재료(26')의제2층을 형성하는 단계와, 제1측부와 상기 제1게이트 구조물(61)의 제1부(32)의 제1측부(36)부근에 있는 제2측부를 가진 상기 제1게이트 구조물(61)의 제2부(58)를 유전재료(26')의 제2층상에 형성하는 단계와, 상기 제1게이트 구조물(61)의 제2부(58)의 제1측부에 정렬된 제2도체형의 제1도우펀트 영역(63)과 상기 제1게이트 구조물(61)의 제1부(32)의 제2측부(37)에 정렬된 제2도체형의 도우펀트 여역(64)을 형성하는 단계와, 상기 제1게이트 구조물(61)의 제1부(32)와 제2부(58)를 제2도체형의 불순물로 도우핑하는 단계와, 상기제1게이트 구조물(61)의 제1부(32)와 제2부(58)를 커플링하는 제1도체 스트랩(78)을 형성하는 단계를 포함하는 것을 특징으로 하는 절연 게이트 반도체 장치의 형성 방법A method of forming an insulated gate semiconductor device comprising the steps of: providing a first conductor type semiconductor material (13) having a major surface (12); providing a second conductor Forming a first layer of dielectric material 26 on the first major surface 12 and a second layer of dielectric material 26 on the first major surface 12, (32) of a first gate structure (61) having a first gate structure (37) and an upper surface (45) on a first portion of a first layer of dielectric material (26) Forming a first cavity (35) extending from the first side (36) below the first portion (32) of the first gate structure (61) and exposing a portion of the major surface (12) Forming in the semiconductor material (13) at least one enhanced dopant region (51) of a first conductor type aligned with the first side (36) of the first portion (32) of the first gate structure (61) and exposed week Forming a second layer of dielectric material 26 'on a portion of the first gate structure 12 in the vicinity of the first side 36 of the first portion 32 of the first gate structure 61; Forming a second portion (58) of the first gate structure (61) having a second side with a second side on a second layer of a dielectric material (26 '), (63) of a second conductor type aligned with the first side of the first gate structure (58) and a second dopant region (63) aligned with the second side (37) of the first portion (32) of the first gate structure Forming a dopant region 64 of a second conductor type and doping the first portion 32 and the second portion 58 of the first gate structure 61 with an impurity of a second conductor type, , And forming a first conductor strap (78) coupling the first portion (32) and the second portion (58) of the first gate structure (61) Method of forming 절연 게이트반도체 장치에 있어서, 주면(12)을 가진 제1도체형의 반도체 재료(13)와, 상기 반도체 재료(13)상의 유전재료(26)의 제1층과, 상기 주면(12)으로부터 상기 반도체 재료(13)의 제1부 내로 연장되는 제2도체형의 도우펀트층(25)과 제1측부(36)와 제2측부(37)를 가지며 유전재료(26)의 제1층의 제1부상의 제1도체부(32)와, 제1측부와 제1게이트 구조물(61)의 제1부(32)와 주면(12)의 제1부 사이의 제1게이트 구조물(61)의 제2도체부(58)의 부분과 유전재료(26')의 제2층에 의해 제1게이트 구조물(61)의 제1도체부(32)의 제1측부(36)로부터 이격된 제2측부를 가진 제2도체부(58)를 가진 제1게이트구조물(61)과, 상기 제1게이트구조물(61)의 제2도체부(58)아래의 반도체 재료(13)의 적어도 부분내에 있는 제1도체형의 하나 이상의 강화된 도우펀트 영역(51)과, 상기 제1게이트 구조물(61)의 제1부(32)의 제2측부(37)부근의 반도체 재료(13)의 부분내에 있는 제1도체형의 하나 이상의 강화된 도우펀트 영역(51)과, 상기 제1게이트 구조물(61)의 제1부(32)의 제2측부(37)부근의 반도체 재료(13)의 부분내의 제2도체형의 제1도우펀트 영역(64)과, 상기 제1게이트구조물(61)의 제2도체부(64)과, 상기 제1게이트 구조물(61)의 제2도체부(58)의 제1측부 부근의 반도체 재료(13)의 부분내의 제2도체형의 제2도우펀트 영역(63)을 포함하는 것을 특징으로 하는 절연 게이트 반도체 장치1. An insulated gate semiconductor device comprising: a first conductor type semiconductor material (13) having a main surface (12); a first layer of dielectric material (26) on the semiconductor material (13) A dopant layer 25 of the second conductor type extending into the first portion of the semiconductor material 13 and a dopant layer 25 of the first layer of dielectric material 26 having a first side 36 and a second side 37, A first conductor portion 32 on the first gate structure 61 and a first conductor portion 32 on the first gate structure 61 between the first portion 32 of the first gate structure 61 and the first portion 12 of the main surface 12. [ A second side spaced from the first side 36 of the first conductor portion 32 of the first gate structure 61 by a portion of the second conductor portion 58 and a second layer of dielectric material 26 ' A first gate structure (61) having a second conductor portion (58) with a first conductor structure (61) and a second conductor portion (58) At least one reinforced dopant region (51) of a first gate structure , One or more reinforced dopant regions (51) of a first conductor type in the portion of the semiconductor material (13) near the second side (37) of the first portion (32) of the first gate structure Of the second conductor type in the portion of the semiconductor material 13 near the second side portion 37 of the first portion 32 of the first gate structure 61 and the first dopant region 64 of the second conductor type in the portion of the semiconductor material 13 near the second side portion 37 of the first gate structure 61 And a second conductor type second dopant region 63 in the portion of the semiconductor material 13 near the first side of the second conductor portion 58 of the first gate structure 61 ), Characterized in that the insulating gate semiconductor device ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960004724A 1995-03-21 1996-02-27 Insulated gate semiconductor device and its manufacturing method KR100368847B1 (en)

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