JPH01212474A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To enable the selective diffusion into a specified region to form a enclosing layer by a method wherein an opening, where a first active layer, a second layer, and a third active layer are exposed, is formed, and ions are implanted through the opening to formed the enclosing layer. CONSTITUTION:A first active layer 13, a second active layer 41, and a third active layer 43 are previously formed in a specified profile and then an opening 49 is formed. And, the second active layer 41 is exposed as a base surface, and ions are implanted for the purpose of forming an enclosing layer 53 in such a manner that the third layer 43 is covered with a second mask layer 45-45c which are left unremoved at a boring process of an opening 49. By the above process, the opening 49 can be formed as a structural component which exposes one side of a first mask layer 37 without the strict alignment of the opening 49 of a resist pattern. By these processes, an enclosing layer 53 can be selectively diffused into a specified region.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method suitable for manufacturing a field effect transistor (hereinafter simply referred to as FET).

(Prior Art) For example, FET elements are widely used as elements for high frequency amplification and oscillation, elements for logic circuits, and semiconductor elements having other functions.

In constructing various electronic devices using these FET elements, research and development is progressing to achieve ultra-high density integrated circuits (VLSI) in response to demands for smaller size, higher speed, and lower power consumption of the devices. ing. In this FET element,
The short channel effect and source
Addresses various problems caused by the shape (profile) of the active layer (in the following explanation, the region formed by implanting impurities will be comprehensively referred to as the active layer), such as parasitic resistance in the train region. The technology to do this is essential.

The above-mentioned FET is made of gallium, which is a compound semiconductor.
Arsenic (GaAs)! GaA is used as an active layer and is constructed by a Schottky junction with a metal gate electrode.
The s-MESFET device is known, and as an example of a technique for solving the above-mentioned problems in the device, Document I: “47th
Proceedings of the Academic Conference of the Japan Society for Applied Physics J (Atsushi 627 pages,
A semiconductor device having a structure disclosed in Lecture No. 28-8-9 (September 1986) is known.

Hereinafter, the technology disclosed in the above-mentioned document I will be explained with reference to the drawings.

FIG. 2 is an explanatory diagram showing the structure of a GaAs-MESFET element through a schematic cross-section of a substrate in order to explain the technology disclosed in the above-mentioned literature. The following description will be made with reference to simple manufacturing steps within the scope disclosed in the above-mentioned documents. In addition, the moon in the figure is semi-insulating GaA
13 is a channel region formed by diffusing n-type impurities as first conductivity type impurities and corresponds to the first active layer; 15 is tungsten silicide (WSix);
gate electrodes 17a and 1 corresponding to the first electrode;
7b is an enclosing layer formed by diffusing n-type impurities as second conductivity type impurities; 19 is a first conductivity type impurity and Lt
a source region 6 formed by spreading rn'-impurities and corresponding to a third active layer; 21 a channel region corresponding to a third active layer formed by diffusing n-type impurities at the same time as the source region 19; 23 is nickel (Ni), aluminum (
/l+1) or other electrode material and corresponds to the second electrode; 25 is made of the same material as the source electrode 23 and corresponds to the third electrode; 2;
7 indicates a GaAs-MESFET element. In addition, hatching indicating a cross section is omitted in the drawing, and detailed explanations of the film thickness of each component and the like are omitted.

First, in this GaAs-MESFET element, the substrate 11
After forming a channel region 13 by diffusing n-type impurities, a gate electrode 15 is formed.

Next, as a mask for ion implantation of the gate electrode 15 described above, beryllium ions (B
g+) is implanted, and the enclosing layers 17a and +7b are formed by self-alignment.

Subsequently, a SiNx film (not shown) is deposited on the entire upper surface of the base, and Si+, which is a first conductivity type impurity, is ion-implanted through the film. In this way, source region 19 and train region 21 are simultaneously formed in self-alignment.

Next, the source electrode 23 and the train electrode 25 are placed on the above-mentioned substrate by any suitable technique such as a lift-off method.
A GaAs-MESFET element 27 is obtained.

- As can be understood from FIG. 2, in the GaAs-MESFET device 27 manufactured through such a process, by forming the enclosure layer 17a and the enclosure layer 171), the source region 19 or the train region 21 is A pn junction is formed in each case. Therefore, in a GaAs-MESFET device with a short gate length, f! It is possible to suppress the current flowing through l and reduce the so-called short channel effect.

(Problems to be Solved by the Invention) As can be understood from the above description, in the conventional technology, the first electrode is used as a mask for ion implantation, and the enclosing layer is formed by self-alignment. Therefore, this enclosing layer is simultaneously formed so as to enclose both the third active layer and the third active layer. However, when aiming to reduce the above-mentioned short channel effect, a sufficient effect can be obtained by simply disposing an enclosing layer only on at least one active layer side. In brief, for example, GaAs
- In order to increase the speed of MESFET devices, IFF is a technique that reduces the parasitic resistance (source resistance) between the gate and source electrodes compared to the resistance between the gate and train electrodes and improves the mutual conductance (for example, Reference I Kaisho 62-33
No. 476) is known. From this point of view, in the conventional technique described above, an enclosing layer is simultaneously formed on the source region side, so there is a problem in that it is difficult to provide a semiconductor element with excellent characteristics.

The present invention was made in view of the above-mentioned conventional problems, and it is possible to selectively diffuse the above-mentioned enclosure layer, which is implanted for the purpose of improving the characteristics of a semiconductor element, only in a predetermined region. It is an object of the present invention to provide a method for manufacturing a semiconductor device, and by extension, to provide a semiconductor device having excellent characteristics.

(Means for Solving the Problems) In order to achieve this object, according to the method for manufacturing a semiconductor device of the present invention, impurities of the first conductivity type are diffused into the first active layer forming region on the surface of the substrate. a step of defining an active layer; a step of forming a first electrode in a predetermined region on the above-described first active layer using the first mask layer as an etching mask; After forming a base in which a second active layer and a first active layer are defined by diffusing impurities of one conductivity type, and depositing a second mask layer for ion implantation on the upper front surface of the base, the process described above is performed. forming a resist pattern having an opening on the second active layer; using the resist pattern as a mask, etching and removing a portion of the second mask layer to form at least the surface of the substrate and the first mask; After forming an opening to expose one side of the layer and removing the above-mentioned resist pattern, ions are implanted through the above-mentioned opening to diffuse the second conductivity type impurity into the above-mentioned base. The method is characterized in that it includes a step of defining an enclosing layer.

(Function) According to the method for manufacturing a semiconductor device of the present invention, the first active layer, the second active layer, and the third active layer are formed in advance using a predetermined BOO file, and then the opening is formed. Ion implantation for the purpose of forming an enclosure layer is performed with the third active layer exposed as the base surface and covered with the second mask layer left in the step of forming the opening. It consists of a composition. In such a step, the opening in the resist pattern can be formed as a component that exposes one side surface of the first mask layer without performing strict alignment.

Therefore, it is possible to form the aforementioned enclosing layer only on one side of the gate electrode constituting the aforementioned first mask layer, for example.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. It should be noted that the drawings referred to in the following description are merely illustrative in outline to the extent that the present invention can be understood, and it should be understood that the present invention is not limited only to the illustrated examples. In addition, in the following explanation, a GaAs-MESFET element using a Schottky junction of GaAs, which is a compound semiconductor, as a gate is applied, and a channel region as a first active layer, a source region as a second active layer, and a second active layer are used. Although a case will be described in which the three active layers are treated as train regions under specific conditions, the present invention is not limited to these specific elements and conditions.

First, FIGS. 1(A) to (F) are explanatory diagrams showing each manufacturing process by a schematic cross section of a substrate, similar to FIG. 2, in order to explain an embodiment of the manufacturing method of the present invention. be. still,
Components that have the same functions as those already explained, except for those that are the characteristics of this invention, are given the same reference numerals, and some of the numerals are omitted, except for the components that are the characteristics of each step. Let me explain. Roughly speaking, in the following explanation, what will happen when forming the active layer? The explanation will be omitted with the anneal process omitted. In these figures, 29 is a gate electrode forming layer made of, for example, tungsten-aluminum (W-/IQ) alloy, tungsten silicide (WSix), or any other suitable high-melting point metal, and 31 is, for example, aluminum (AQ), nickel (Ni). ) or other suitable material; 33 is a gate electrode obtained by etching the gate electrode forming layer 29 and corresponds to the first electrode; 35 is a side etched portion formed together with the gate electrode 33; , 37 is a first mask layer composed of an electrode pattern layer 31, a gate electrode 33, and a side etching portion 35; 39 is a resist pattern for ion implantation; 41
43 is a source region defined by diffusing an n-type impurity as a first conductivity type impurity and corresponds to a second active layer; 43 is a train region defined similarly to the source region 41 and corresponds to a third active layer; 45a; ~45c is, for example, germanium (Ge)
47 is a resist pattern defining an opening 49 formed at an arbitrary position on the train region 43; 51 is an opening formed in the second mask layer; An enclosing layer 55 defined by diffusing n-type impurities corresponding to two-conductivity type impurities is a GaAs-MESFET element according to this embodiment.

First, in the same manner as described above, a channel region 13 as a first active layer is formed in a predetermined region according to a design on a substrate 11 made of semi-insulating GaAs. Subsequently, a gate electrode forming layer 29 for forming a gate electrode is deposited on the entire upper surface of the substrate 11 on which the region 13 is formed. Thereafter, an electrode pattern layer 31 is formed on a predetermined portion of the gate electrode formation layer 29 above the channel region 13 and where a gate electrode is desired to be provided, by, for example, a lift-off technique. A base in the state shown in (A) is obtained.

Subsequently, for example, reactive ion etching (Re-ac
The electrode pattern layer 31 described above is used as an etching mask to perform etching using a dry etching technique such as tive ion etching (formerly E) method. In this way, the electrode pattern layer 31, the gate electrode 33,
A first mask layer 377 consisting of side etched portions 35 (indicated by broken lines in the figure) on both sides of the electrode 33;
&Form.

Next, as in the prior art, an ion implantation resist pattern 39 is formed at a predetermined position according to the design.

Thereafter, using the resist pattern 39 and the above-described first mask layer 37 as ion implantation masks, impurity ions are implanted as shown by a series of arrows C. In this way, the source region 41 and the train region 43 are implanted. , and as shown in Figure 1 (
The state shown in 8) is obtained.

As can be understood from the above description, the source region 41 corresponding to the second active layer and the drain region 43 corresponding to the third active layer are simultaneously obtained in the self-alignment.

Here, by forming the side etching portion 35 as a component of the first mask layer 37, the so-called LDD (
Similar to the lic+htly doped drain) structure, it can be expected that the two active layers (source region and train region) described later will contribute to reducing the short channel effect caused by lateral diffusion.

Next, the above-described resist pattern 39 for ion implantation is removed, and second mask layers 45a to 45c for ion implantation are deposited on the entire upper surface of the base. With such a laminated relationship, second mask layers 45a and 45b deposited directly on substrate 11 and second mask layer 45c deposited above first mask layer 37 are formed.

Then, a resist pattern 47 having an opening 49 only at an arbitrary position M (described later) on the train region 43 is formed with a predetermined thickness on the entire upper surface of the mask layers 45a to 45c. A base in the state shown in Figure (C) is obtained.

Next, using the resist pattern 47 described above as an etching mask, only the materials constituting the second mask layers 45a to 45c are etched by RIE or other dry etching techniques using, for example, sulfur hexafluoride (SF) as an etching gas. (Fig. 1 CD)
An opening 51 as shown in FIG.

The etching process for forming the opening 51 will be described in detail. As already mentioned in the structure of the manufacturing method of the present invention, the etching process is performed by precisely aligning the opening 49 defined by the resist pattern 47. The opening 51 can be formed as a component that exposes one side surface of the first mask layer 37 without performing this step. In other words, if the conditions are such that an isotropic etching jig can perform the dry etching technique for forming the openings 51 described above, as the isotropic etching process is performed, etching is performed not only in the direction perpendicular to the surface of the substrate 11 but also in the surface. Parallel etching progresses. Therefore, no matter where the opening 49 is formed in the train electrode region 43, the end surface of the second mask layer 45c and one side surface of the gate electrode 33 will not be exposed. Become. Therefore, the above-described etching in the parallel direction is stopped when at least the side surfaces of the first mask layer 37 are exposed, and the etching of the second mask layers 45a and 45 is stopped.
b is not etched.

The resist pattern 47 having such an opening 51 formed therein is removed. After that, as shown in Figure 1 (E),
The second mask layers 45a and 45t) and the second mask layer 45C remaining from the above-mentioned etching process are used as ion implantation masks, and through the above-mentioned opening 51, a second conductive type such as beryllium ion CBe+) is implanted. A p-type impurity (indicated by a series of arrows d in the figure) as an impurity is diffused to form an enclosing layer 53.

To explain the ion implantation conditions for this enclosing layer 53, as shown by the arrow e in FIG. It is preferable to set the conditions such that the formation of the pores occurs.

Next, after removing the second mask layers 45a to 45c and the electrode pattern layer 31 described above, the source electrode 23 and the train electrode 25 are formed as in the conventional method. In this way, a GaAs-MESFET element 55 according to an embodiment of the present invention as shown in FIG. 1(F) is obtained.

Although the embodiments of the present invention have been described in detail above, it is clear that the method of manufacturing a semiconductor device of the present invention is not limited to the embodiments described above.

For example, the embodiments described above use a first mask layer that includes side etchings to reduce short channel effects. However, the method of the present invention is not limited to this, and the first mask layer may be formed with a conventionally known sidewall instead of the above-mentioned side etching portion.

In general, the manufacturing method of the present invention is not only applicable when the above-mentioned technique aimed at reducing the short channel effect is used in combination, but also sufficient effects can be obtained by simply forming an enclosing layer.

In addition, in order to ensure that only one end of the first mask layer is etched away at the opening, the height from the substrate surface to the upper side of the first mask layer is made sufficiently high to prevent the second mask layer from breaking. The cases where this occurs have been illustrated and explained. However, if the second mask layer is deposited as a continuous layer, even if etching progresses over time after the second mask layer on one side of the first mask layer is etched away, at least the first mask layer As long as the second mask layer on the other side remains, the same effect as described above can be obtained.

Roughly speaking, in the above embodiment, germanium was used as the material constituting the second mask layer, but other materials may be used as long as they meet the following conditions. .

■Materials with high ion implantation stopping power when implanting impurity ions■For example, between the material forming the deposition surface such as the substrate,
A material that does not cause negative effects such as peeling due to stress ■ A material that has a higher etching rate than the resist pattern, first mask layer, and substrate and is capable of isotropic etching As, for example, the above-mentioned germani.

Silicon nitride (SiNx) or the like can be used instead of RAM.

In addition to this, in the above-mentioned embodiment, a case was explained in which a GaAs-MESFET device was manufactured as an example of a semiconductor device, but MESFETs made of semiconductors other than G8^8
It can also be applied to the manufacture of ET devices or other semiconductor devices.

These materials, shapes, and arrangements! It will be obvious that any suitable design changes and modifications may be made to the relationships, numerical conditions and other conditions without departing from the scope of the invention.

(Effects of the Invention) As is clear from the above explanation, according to the method of manufacturing a semiconductor device of the present invention, by having the above-mentioned structure, there is no need to carry out strict alignment for forming an opening. The second mask layer is etched away, allowing ion implantation to be performed only on one side of the 1779th layer through the opening. Therefore, for example, the above-mentioned first mask layer 1! It becomes possible to form the above-mentioned enclosing layer by implanting impurities of a conductivity type different from that of the previously formed active layer only on one side of the first electrode.

Therefore, it is possible to provide a method for manufacturing a semiconductor device in which the above-mentioned enclosure layer, which is implanted for the purpose of improving the characteristics of the semiconductor device, can be selectively diffused only in a predetermined region. Accordingly, it is possible to provide a semiconductor element having characteristics such as:

[Brief explanation of the drawing]

1(A)-(F) provide a detailed explanation of this invention."
Therefore, each manufacturing process is illustrated by a schematic cross-section of the substrate. FIG. 2 is an explanatory diagram of the prior art. 11...Substrate 13...Channel region (first active layer) 15...
-Gate electrode (body electrode) 17a, 17b, 53... Enclosure layer 19.
41... Source region (third active layer) 21.43.
...Train region (third active layer) 23.33...
...Source electrode (second electrode) 25...Train electrode (third electrode) 27.55----GaAs-MESF
ET element 29... Gate electrode forming layer 31... Electrode pattern layer 35... Side etching portion, 37... First mask layer 39... Resist pattern for ion implantation 45
a to 45c...Second mask layer 47...Resist pattern, 49...Opening 51...Openings a, b, e...Predetermined portions C of enclosing layer...・・n
type impurity (M-conductivity type impurity) d...n type impurity (
second conductivity type impurity). Patent applicant: Oki Electric Industry Co., Ltd. Figure 2 Figure 1 '55: Explanation of GaA8-MESFET device example Figure 1

Claims (1)

[Claims] (1) Defining a first active layer by diffusing a first conductivity type impurity into a first active layer formation region on the substrate surface; and etching a first mask layer in a predetermined region on the first active layer. a step of forming a first electrode as a mask; and a step of diffusing a first conductivity type impurity using a self-alignment line with respect to the first mask layer to form a base on which a second active layer and a third active layer are defined. , after depositing a second mask layer for ion implantation on the upper front surface of the base, forming a resist pattern having an opening on the second active layer; and using the resist pattern as a mask, forming the second mask layer. forming an opening that exposes at least a surface of the substrate and one side of the first mask layer by etching away a portion thereof; and after removing the resist pattern, performing ion implantation through the opening; 1. A method of manufacturing a semiconductor device, comprising the step of diffusing a second conductivity type impurity into a base to define an enclosing layer.