JPH07118485B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor element, and particularly to a method suitable for manufacturing a field effect transistor (hereinafter, simply referred to as FET).

(Prior Art) For example, FET elements are widely used as high-frequency amplification / oscillation elements, logic circuit elements, and semiconductor elements having other functions.

In constructing various electronic devices with these FET elements, research and development for achieving a very high-density integrated circuit (VLSI) are being advanced in response to demands for miniaturization, high speed, and low power consumption of the devices. ing. In this FET element, the active layer such as the short channel effect due to the miniaturization of the element and the parasitic resistance of the source / drain region (in the following description, the region formed by implanting impurities is included as the active layer. A technique for coping with various problems caused by the shape (profile) is indispensable.

As the above-mentioned FET, there is known a GaAs MESFET device that is composed of a compound semiconductor, gallium-arsenic (GaAs), as an operation layer and is formed by a Schottky junction using a gate electrode as a metal, and solves the above-mentioned problems in the device. As an example of the technique, an element disclosed in JP-A-62-33476 and a method for manufacturing the element are known.

The technique disclosed in the above publication will be described below with reference to the drawings. The following description will be made according to the above-described method for manufacturing the element. Further, in the following description, constituent components in the middle of the manufacturing process are comprehensively represented as a base.

FIGS. 2A to 2D are explanatory views showing the manufacturing process of the GaAs MESFET device by a schematic substrate cross section, for explaining the technique disclosed in the above-mentioned publication. In the figure, 11 is a substrate made of semi-insulating GaAs, 13 is a channel region, 15 is a silicon dioxide (SiO ₂ ) film, 17 is a tungsten nitride (WN) film, 19 is a gate electrode, 21 is a source region, and 23 is A source electrode, 25 is a drain electrode, 27 is a GaAs MESFET element, and a is an n-type impurity ion. Further, hatching showing a cross section is partially omitted in the drawing, and detailed description of the film thickness of each component is omitted.

First, using a resist pattern (not shown) as a mask, 4 × 10 ¹² (c) of an n-type impurity such as silicon ion (Si ⁺ ) is applied to a predetermined region according to the design on the substrate 11.
After implantation with an impurity concentration of about m ^-2 ), the channel region 13 is formed by annealing at a predetermined temperature.

After that, silicon dioxide (SiO ₂ ) is formed on the entire upper surface of the above-mentioned base.
Is formed, and a SiO ₂ film 15 is formed by coating at least a predetermined portion of the substrate 11 to be a drain region by a subsequent step and patterning so that an end face is formed at a portion where a gate electrode is to be formed. .

Next, the WN film 17 is deposited on the entire upper surface of the above-mentioned base to obtain the base in the state shown in FIG. 2 (A).

Then, for example, carbon tetrafluoride (C
Anisotropic etching such as Reactive Ion Etching (RIE) using F ₄ ) as an etching gas is performed, and the above-mentioned channel region of the SiO ₂ film 15 is etched.
A gate electrode 19 is formed on the side surface above 13 to obtain a base in the state shown in FIG.

Next, the gate electrode 19 and the SiO ₂ film 15 are applied to the base described above.
Is used as a mask to form an n-type impurity (in FIG. 2C, an arrow a
Indicate. ) Is performed to form the source region 21 with an impurity concentration of about 2 × 10 ¹³ (cm ⁻² ), and the same annealing treatment as described above is performed to obtain a base in the state shown in FIG. 2 (C). .

As can be understood from the above description, according to the technique disclosed in this publication, the source region 21 is formed by self-alignment.

Then, after removing the SiO ₂ film 15 formed on the lower surface, a source electrode 23 and a drain electrode 25 are formed by a conventionally known method, and a GaAs MESFET as shown in FIG. 2 (D) is formed.
Element 27 is obtained.

In the GaAs MESFET device 27 thus obtained, the predetermined portion of the substrate 11 corresponding to the drain region is the channel region.
It has the same impurity concentration as that of 13. For this reason, the impurity concentration of the active layer corresponding to the drain region is lower than that in the case where the source region and the drain region are simultaneously formed by ion implantation, so that the short channel effect accompanying the shortening of the channel length is reduced. It is possible.

(Problems to be Solved by the Invention) However, in the above-described conventional method for manufacturing a semiconductor element, the parasitic resistance in the source region which is one of the electrode regions,
Although the short channel effect can be solved at the same time, since the drain region and the channel region have approximately the same impurity concentration, when a low impurity concentration in the channel region is desired according to the design, the parasitic resistance in the drain region is reduced. growing. For this reason, there is a problem that not only the so-called drain resistance of the semiconductor element increases, but also the resistance related to ohmic contact in the drain region increases, which makes it difficult to improve the performance of the element.

In addition, in the technique of performing ion implantation into the source region and the drain region at the same time after performing ion implantation into the channel region, the amount of each individual region (active layer) is set as a suitable amount according to the function of the electronic device mounting the semiconductor element. It is difficult to manufacture an excellent semiconductor device in that the impurity profile of 1 cannot be controlled.

The object of the present invention is made in view of the above-mentioned various problems, and ion implantation is performed with an optimum impurity concentration and implantation depth according to the function of each active layer formed in a semiconductor element. In order to improve the degree of freedom in designing a semiconductor element, a method for manufacturing a semiconductor element is provided, and further, a semiconductor element having excellent characteristics is provided.

(Means for Solving the Problems) In order to achieve this object, according to the method for manufacturing a semiconductor element of the present invention, a first mask layer for ion implantation including at least a gate electrode is formed on a substrate. When manufacturing a semiconductor device by forming a second active layer adjacent to the first active layer on a base provided with the first active layer, a second ion implantation layer is formed on the entire upper surface of the base described above. After depositing a mask layer such that a portion formed on the first mask layer and a portion formed on the substrate are cut off,
A step of providing a resist pattern having an opening on the second active layer forming region, and using the resist pattern having the above-mentioned opening as a mask,
A part of the above-mentioned second mask layer is removed by etching, and at least the above-mentioned second active layer forming region and one side surface of the above-mentioned first mask layer (surface on the opening side provided in the above-mentioned resist pattern). The method comprises the steps of forming an exposed opening, and after removing the resist pattern described above, performing ion implantation through the opening to form a second active layer on the base described above. I am trying.

(Operation) According to the method of manufacturing a semiconductor element of the present invention, the second mask layer is formed in a state where the portion on the first mask layer and the portion on the substrate are cut off, and thus the first mask layer is formed. A structure is obtained in which there is no second mask layer diagonally above the layer.
Therefore, after the predetermined step of etching the second mask layer with the resist pattern as a mask and further removing the resist pattern, the second mask layer is provided with a second active layer forming region as a second region. An opening is formed so as to be exposed to one side surface of one mask layer. Next, it becomes possible to perform ion implantation only on one side of the first mask layer through this opening. In such a process,
The opening can be formed as a constituent that exposes one side surface of the first mask layer without performing strict alignment of the opening of the resist pattern.

Therefore, for example, the respective second active layers such as the source region and the drain region can be individually formed easily and easily by self-alignment on both sides of the gate electrode forming the above-mentioned first mask layer.

(Example) Hereinafter, an example of a method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. It should be understood that the drawings referred to in the following description are merely schematic illustrations to the extent that the present invention can be understood, and the present invention is not limited to the illustrated examples. Further, in the following description, a GaAs MESFET device using a Schottky junction of a compound semiconductor, GaAs, as a gate is applied, and a specific region is used as a channel region as a first active layer and a source region as a second active layer. However, the present invention is not limited to these specific elements and conditions.

FIGS. 1 (A) to 1 (H) are manufacturing process diagrams shown in the same manner as FIGS. 2 (A) to 2 (D) for explaining an embodiment of the manufacturing method of the present invention. Further, except for the constituent components which are the features of the present invention, constituent components having the same functions as those already described are designated by the same reference numerals.
Further, in the following description, the annealing process for forming the active layer is omitted. In these figures,
29 is a gate electrode forming layer made of, for example, a tungsten-aluminum (W-Al) alloy or any other suitable refractory metal, and 31 is, for example, aluminum (Al) or nickel (N).
an electrode pattern layer made of i) or other suitable material, 3
3 is a gate electrode obtained by etching the gate electrode forming layer 29, 35 is a side etching portion formed together with the gate electrode 33, and 37 is a first electrode pattern layer 31, a gate electrode 33 and a side etching portion 35. One mask layer, 39a
39c is a second mask layer for ion implantation made of germanium (Ge), 41 is a source formation region corresponding to the second active layer formation region, and 45 is an opening formed at an arbitrary position on the source formation region 41. 43 is a resist pattern that defines 43, 47 is an opening formed in the second mask layer, 49 is a source region, and 51 is a source region.
Is a drain region, and 53 is a GaAs MESFET device manufactured by the process of this embodiment.

First of all, in the same way as described above, the semi-insulating
A channel region 13 as a first active layer is formed in a predetermined region according to the design on a substrate 11 made of GaAs. Subsequently, a gate electrode forming layer 29 for forming a gate electrode is deposited with a film thickness of about 1000 (Å) on the entire upper surface of the substrate 11 on which the region 13 is formed. Then, at a predetermined portion on the upper side of the channel region 13 and where the gate electrode is desired to be arranged, on a predetermined portion on the gate electrode forming layer 29, for example, by a lift-off technique, about 3000
The electrode pattern layer 31 is formed with a film thickness of about (Å) and a width of about 1 (μm) to obtain a base in the state shown in FIG. 1 (A).

Then, for example, reactive ion etching (Reactive Ion
Etching is performed by using the above-mentioned electrode pattern layer 31 as an etching mask by a dry etching technique such as an RIE method. In this way, the electrode pattern layer 31
And a gate electrode 33 having a width of about 0.7 (μm), and side etching portions 35 (shown by a broken line in the figure) on both side surfaces of the electrode 33. Thus, the base material in the state shown in FIG. 1 (B) is obtained.

Here, by forming the side etching portion 35 as a constituent component of the first mask layer 37, so-called LDD (Lightly D
Similar to the oped drain structure, it can be expected to contribute to the reduction of the short channel effect caused by lateral diffusion of two active layers (source region and drain region) described later.

Next, the second mask layers 39a to 39c for ion implantation are deposited on the entire upper surface of the above-described base with a film thickness of about 5000 (Å). With such a laminated relationship, the second mask layers 39a and 39b directly deposited on the substrate 11 and the first mask layer
A second mask layer 39c is deposited on top of 37.

Thereafter, a resist pattern 45 having an opening 43 is formed on the entire upper surface of the mask layers 39a to 39c with a predetermined film thickness at an arbitrary position (described later) on the source formation region 41, and FIG. A base material in the state shown in (C) is obtained.

Then, using the resist pattern 45 described above as an etching mask, for example, by the RIE method or other dry etching technique using sulfur hexafluoride (SF ₆ ) as an etching gas, only the material forming the second mask layers 37a to 37c is formed. Is selectively removed by etching to form an opening 47 as shown in FIG.

The etching process for forming the opening 47 will be described in detail. As already described as the configuration of the manufacturing method of the present invention, strict alignment is performed with respect to the opening 43 defined by the resist pattern 45. It is possible to form the opening 47 as a constituent component that exposes one side surface of the first mask layer 37 without any need. That is, if the dry etching for forming the opening 47 described above is performed under the condition that isotropic etching can be performed, as the isotropic etching process is performed, not only the direction perpendicular to the surface of the substrate 11 but also the direction parallel to the surface is increased. Etching progresses. Because of this
Even when the opening 43 is formed at any position of the source formation region 41 described above, the end surface of the second mask layer 39a and one side surface of the gate electrode 33 are exposed.
Therefore, the above-described etching in the parallel direction is stopped when at least the side surface of the first mask layer 37 is exposed, and the second mask layers 39b and 39c are not etched.

After forming such an opening 47, a resist pattern 45 is formed.
And removing the second mask layer 39 as shown in FIG. 1 (E).
By using a part of a and the second mask layers 39b and 39c as a mask, the impurity ions shown by the arrow a are implanted through the opening 47, and the source region 49 corresponding to the second active layer is obtained by self-alignment. Further, in the ion implantation in this step, it is possible to contribute to the reduction of the short channel effect by the action of the side etching portion 35 formed as the first mask layer 37.

Next, the second mask layers 39a to 39c described above are removed to obtain the state shown in FIG. As can be understood from this figure, the underlying state after the source region 49 forming step is the same as that of FIG. 1B except the existence of the region 49. Therefore, even after the active layer extending to one side of the gate electrode 33 is formed as in the prior art with reference to FIGS. 2A to 2D, the manufacturing method of the present invention can be used. For example, after the series of steps described with reference to FIGS. 1B to 1F, another active layer (drain region 51) is further provided on the other side of the gate electrode 33 as individual conditions. It can be formed (FIG. 1 (G)).

After going through such steps, the electrode pattern layer 31 is removed,
The source electrode 23 and the drain electrode 25 are formed in the same manner as in the conventional case, and the GaAs MESFET element 53 according to the embodiment of the present invention is obtained (FIG. 1 (H)).

Although the embodiments of the present invention have been described in detail above, it is apparent that the method for manufacturing a semiconductor device of the present invention is not limited to the above-mentioned embodiments.

For example, in the above-described embodiments, the case where the first mask layer including the side etching portion for reducing the short channel effect is used has been described. However, the method of the present invention is not limited to this, and the first mask layer may be formed as a structure including a conventionally known side wall instead of the side etching portion described above.

Furthermore, the manufacturing method of the present invention is not applied only when the above-mentioned technique for reducing the short channel effect is used in combination, and the width of the electrode pattern layer and the gate electrode is used as the first mask layer. It is clear that a sufficient effect can be obtained even if the process is performed in the state where

Also, in the etching step when forming the opening,
In order to surely remove only one end of the first mask layer by etching, the height from the surface of the substrate to the upper side of the first mask layer is made sufficiently high, and the case where the second mask layer is discontinued is shown in the figure. explained.

Furthermore, although the case where germanium is used as the material forming the second mask layer, which is a feature of the present invention, has been described, other materials may be used as long as they satisfy the following conditions.

A material having a high ion implantation blocking ability during the implantation of impurity ions, for example, between the material forming the deposition surface such as the substrate,
A material that does not cause adverse effects such as peeling due to stress A material that has a higher etching rate than the resist pattern, the first mask layer and the substrate, and isotropic etching is possible. It is possible to use silicon nitride (SiN _x ) or the like instead of the above-mentioned germanium.

In addition to this, in the above-mentioned embodiment, the case of manufacturing a GaAs MESFET device as an example of the semiconductor device has been described.
MESFET devices made of semiconductors other than GaAs, and MOSF
It can also be applied to ET devices and the like.

It is apparent that these materials, shapes, arrangement relationships, numerical conditions and other conditions can be changed and modified in any suitable design within the scope of the object of the present invention.

(Effects of the Invention) As is apparent from the above description, according to the method for manufacturing a semiconductor element of the present invention, by adopting the above-described configuration, it is possible to perform the second alignment without performing strict alignment for forming the opening. The mask layer can be removed by etching, and an opening can be formed in the second mask layer so that the second active layer forming region can be exposed up to one side surface of the first mask layer, and the first mask can be exposed through the opening. It is possible to perform ion implantation only on one side of the layer. Therefore, it is possible to easily and easily form the respective second active layers such as the source region and the drain region on the both sides of the gate electrode forming the first mask layer by self-alignment under the individual ion implantation conditions. it can.

Therefore, by providing a method for manufacturing a semiconductor element by performing ion implantation under optimal conditions according to the function of each active layer formed in the semiconductor element and improving the degree of freedom in designing the semiconductor element. It is possible to provide a semiconductor device having excellent characteristics.

[Brief description of drawings]

1 (A) to 1 (H) are explanatory views showing schematic cross-sections of an underlayer according to each manufacturing process for explaining the embodiment of the manufacturing method of the present invention, and FIGS. 2 (A) to 2 (D). FIG. 3 is an explanatory view showing a schematic cross-section similar to FIGS. 1 (A) to 1 (H) for explaining a conventional technique. 11 …… Substrate, 13 …… Channel region (first active layer) 15 …… Silicon dioxide (SiO ₂ ) film 17 …… Tungsten nitride (WN) film 19,33 …… Gate electrode, 21 …… Source region 23… Source electrode, 25 Drain electrode 27,53 GaAs MESFET device 29 Gate electrode forming layer, 31 Electrode pattern layer 35 Side etching part, 37 First mask layer 39a to 39c Second mask layer 41 ... Source formation region (second active layer formation region) 43 ... Opening, 45 ... Resist pattern 47 ... Opening, 49 ... Source region (second active layer) 51 ... Drain region, a: Impurity ion.

Claims (1)

[Claims] 1. A second active layer adjacent to the first active layer is provided on a base provided with a first mask layer for ion implantation including at least a gate electrode and a first active layer formed on a substrate. When forming and manufacturing a semiconductor element, a second mask layer for ion implantation is formed on the entire upper surface of the base to form a portion formed on the first mask layer and a portion formed on the substrate. A step of providing a resist pattern having an opening on the second active layer formation region after depositing so as to break, and a part of the second mask layer is removed by etching using the resist pattern as a mask, and at least the second active layer is formed. A step of forming an opening exposing a layer forming region and one side surface of the first mask layer; and after removing the resist pattern, ion implantation is performed through the opening to form a second active layer on the base. The method of manufacturing a semiconductor device characterized by comprising comprises the steps of forming.