KR950021772A - Method of manufacturing integrated circuit having at least one MOS transistor - Google Patents

Method of manufacturing integrated circuit having at least one MOS transistor Download PDF

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KR950021772A
KR950021772A KR1019940032395A KR19940032395A KR950021772A KR 950021772 A KR950021772 A KR 950021772A KR 1019940032395 A KR1019940032395 A KR 1019940032395A KR 19940032395 A KR19940032395 A KR 19940032395A KR 950021772 A KR950021772 A KR 950021772A
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doped layer
applying
doped
integrated circuit
source terminal
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KR1019940032395A
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Korean (ko)
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로타르 리쉬
토마스 포겔장
프란쯔 호프만
카를 호프만
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발도르프, 음케
지멘스 악티엔게젤샤프트
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Publication of KR950021772A publication Critical patent/KR950021772A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

절연층은 소오스 단자영역을 포함하는 기판의 기본표면상에 성장한다. 소오스 단자영역의 표면이 특히 도포되지않은 제1개구부는 절연층에 제공된다. 적어도 MOS트랜지시터에 대한 드레인영역과 채널영역을 포함하는 연속한 수직층은 도핑에서 반도체 물질의 에피텍시 성장에 의하여 제1개국부에 만들어진다. 드레인영역과 채널영역의 두께의 합과 일치하는 깊이를 가지는 제2개구부는 층 구조로 만들어지며 게이트 유전체는 그의 표면에 인가되고 게이트 전극은 상기 게이트유전체에 인가된다.The insulating layer grows on the basic surface of the substrate including the source terminal region. The first opening, to which the surface of the source terminal region is not particularly applied, is provided in the insulating layer. A continuous vertical layer comprising at least a drain region and a channel region for the MOS transistor is made in the first country portion by epitaxial growth of the semiconductor material in doping. The second opening having a depth equal to the sum of the thicknesses of the drain region and the channel region is made in a layer structure, a gate dielectric is applied to its surface, and a gate electrode is applied to the gate dielectric.

Description

적어도 하나의 모오스(MOS)트랜지시터를 구비한 집적회로의 제조방법Method of manufacturing integrated circuit having at least one MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 층구조를 나타낸 수직MOS 트랜지시터를 도시한 도면.3 shows a vertical MOS transistor showing a layer structure.

제4도는 수직MOS트랜지스터에서의 정면도.4 is a front view of a vertical MOS transistor.

제5도는 층구조에 나타낸 수직 인버터를 도시한 도면.5 shows a vertical inverter shown in a layer structure.

Claims (11)

적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법에 있어서, 기판상에 소오스 단자영역을 만드는 단계; 소오스 단자영역상에 제1절연층을 인가하는 단계; 소오스 단자영역의 표면을 노출하는 제1절연층에 제1개구부를 제공하는 단계; 소오스 단자영역의 표면상에 제1도핑층을 인가하는 단계; 제1도핑층상에 제2도핑층을 인가하는 단계; 제2도핑층상에 제3도핑층을 인가하는 단계; 제1도핑층으로 연장한 제3도핑층에 위치한 제2개구부를 제공하는 단계; 제2개구부의 표면내측에 유전체를 인가하는 단계; 게이트 전극을 형성하기 위하여 도핑된 폴리실리콘으로 제2개구부를 충전하는 단계; 도핑된 폴리실리콘에 제2절연층을 인가하는 단계; 전기접속을 제3도핑층에 제공하는 단계; 전기접속을 게이트전극에 제공하는 단계; 전기접속을 소오스 단자영역에 제공하는 단계를 포함하는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.CLAIMS 1. A method for manufacturing an integrated circuit having at least one MOS transistor, the method comprising: forming a source terminal region on a substrate; Applying a first insulating layer on the source terminal region; Providing a first opening in a first insulating layer exposing a surface of a source terminal region; Applying a first doped layer on the surface of the source terminal region; Applying a second doped layer on the first doped layer; Applying a third doped layer on the second doped layer; Providing a second opening located in the third doped layer extending to the first doped layer; Applying a dielectric inside the surface of the second opening; Filling a second opening with doped polysilicon to form a gate electrode; Applying a second insulating layer to the doped polysilicon; Providing an electrical connection to the third doped layer; Providing an electrical connection to the gate electrode; A method for manufacturing an integrated circuit having at least one MOS transistor, the method comprising providing an electrical connection to a source terminal region. 제1항에 있어서, 제3도핑층을 인가하는 단계는, 제3도핑층의 상부표면이 제1절연층의 표면에서 평평하게 되도록 더 높은 부분에 제3도핑층을 인가하는 단계를 포함하는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.The method of claim 1, wherein applying the third doped layer comprises applying the third doped layer to a higher portion such that the top surface of the third doped layer is flat at the surface of the first insulating layer. A method for manufacturing an integrated circuit having at least one MOS transistor. 제1항에 있어서, 소오스 단자영역을 만드는 단계는 도핑된 웰의 형상을 포함하는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.The method of claim 1, wherein the step of making the source terminal region comprises a shape of a doped well. 제3항에 있어서, 소오스 단자영역을 만드는 단계는 연속한 도핑층의 형상을 포함하는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.4. The method of claim 3 wherein the step of making the source terminal region comprises a shape of a continuous doped layer. 제1항에 있어서, 제1, 제2 및 제3도핑층을 인가하는 단계는 분자 빔 에피텍시를 통하여 도핑된 층을 인가하는 단계를 포함하는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.The method of claim 1, wherein applying the first, second, and third doped layers comprises applying a doped layer through molecular beam epitaxy. Method of manufacturing an integrated circuit provided. 제5항에 있어서, 제1, 제2 및 제3도핑층을 인가하는 단계는 선택적 에피텍시를 통하여 도핑된 층을 인가하는 단계를 포함하는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.6. The method of claim 5, wherein applying the first, second, and third doped layers comprises applying a doped layer through selective epitaxy. Method of manufacturing an integrated circuit. 제5항에 있어서, 분자 빔 에피텍시를 통하여 도핑층을 인가하는 단계는 400에서 700℃의 온도범위와 0.1에서 10mbar의 입력범위에서 실행되는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.6. The method of claim 5, wherein applying the doped layer through molecular beam epitaxy is performed at a temperature range of 400 to 700 ° C and an input range of 0.1 to 10 mbar. Method of manufacturing an integrated circuit. 제6항에 있어서, 선택적 에피텍시를 통하여 도핑층을 인가하는 단계는 SiH2Cl2에 대한 RTP-CVD에 의하여 실행되는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.7. The fabrication of an integrated circuit with at least one MOS transistor as claimed in claim 6, wherein the step of applying the doped layer via selective epitaxy is carried out by RTP-CVD on SiH 2 Cl 2 . Way. 제6항에 있어서, 선택적 에피텍시를 통하여 도핑층을 인가하는 단계는 SiH2에 대한 RTP-CVD에 의하여 실행되는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.7. The method of claim 6 wherein the step of applying the doped layer via selective epitaxy is performed by RTP-CVD on SiH 2 . 제1항에 있어서, 제1도핑층은 제2도핑층의 극성과는 반대 극성을 가지는 것을 특징으로 하는 적어도 하나의 모오스 트랜지시터를 구비한 집적회로의 제조방법.The method of claim 1, wherein the first doped layer has a polarity opposite to that of the second doped layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032395A 1993-12-01 1994-12-01 Method of manufacturing integrated circuit having at least one MOS transistor KR950021772A (en)

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DE4340967A DE4340967C1 (en) 1993-12-01 1993-12-01 Method for producing an integrated circuit arrangement having at least one MOS transistor
DEP4340967.9 1993-12-01

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EP (1) EP0656647B1 (en)
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2154357C (en) * 1993-02-04 2004-03-02 Kevin A. Shaw Microstructures and single-mask, single-crystal process for fabrication thereof
DE4417150C2 (en) * 1994-05-17 1996-03-14 Siemens Ag Method for producing an arrangement with self-reinforcing dynamic MOS transistor memory cells
US5872374A (en) * 1996-03-29 1999-02-16 Motorola, Inc. Vertical semiconductor device
US5929476A (en) 1996-06-21 1999-07-27 Prall; Kirk Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors
DE19653107C2 (en) * 1996-12-19 1998-10-08 Siemens Ag Method for producing a memory cell arrangement
DE19711482C2 (en) * 1997-03-19 1999-01-07 Siemens Ag Method of manufacturing a vertical MOS transistor
US5864158A (en) * 1997-04-04 1999-01-26 Advanced Micro Devices, Inc. Trench-gated vertical CMOS device
US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US5907170A (en) 1997-10-06 1999-05-25 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US6528837B2 (en) * 1997-10-06 2003-03-04 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US6069390A (en) 1998-01-15 2000-05-30 International Business Machines Corporation Semiconductor integrated circuits with mesas
US6177299B1 (en) 1998-01-15 2001-01-23 International Business Machines Corporation Transistor having substantially isolated body and method of making the same
US6025225A (en) 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
US6242775B1 (en) * 1998-02-24 2001-06-05 Micron Technology, Inc. Circuits and methods using vertical complementary transistors
US6304483B1 (en) 1998-02-24 2001-10-16 Micron Technology, Inc. Circuits and methods for a static random access memory using vertical transistors
US6097242A (en) 1998-02-26 2000-08-01 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US6124729A (en) 1998-02-27 2000-09-26 Micron Technology, Inc. Field programmable logic arrays with vertical transistors
US5991225A (en) 1998-02-27 1999-11-23 Micron Technology, Inc. Programmable memory address decode array with vertical transistors
US6492232B1 (en) 1998-06-15 2002-12-10 Motorola, Inc. Method of manufacturing vertical semiconductor device
US6208164B1 (en) 1998-08-04 2001-03-27 Micron Technology, Inc. Programmable logic array with vertical transistors
US6134175A (en) 1998-08-04 2000-10-17 Micron Technology, Inc. Memory address decode array with vertical transistors
US6500744B2 (en) 1999-09-02 2002-12-31 Micron Technology, Inc. Methods of forming DRAM assemblies, transistor devices, and openings in substrates
KR100422412B1 (en) * 2001-12-20 2004-03-11 동부전자 주식회사 Cylindrical type transistor having vertical silicon-on-insulator structure and fabrication method thereof
US7071519B2 (en) * 2003-01-08 2006-07-04 Texas Instruments Incorporated Control of high-k gate dielectric film composition profile for property optimization
US6913959B2 (en) * 2003-06-23 2005-07-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having a MESA structure
US8618600B2 (en) * 2008-06-09 2013-12-31 Qimonda Ag Integrated circuit including a buried wiring line
CN109326595B (en) 2017-07-31 2021-03-09 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
WO2023173679A1 (en) * 2022-03-18 2023-09-21 北京超弦存储器研究院 Transistor and manufacturing method therefor, memory, and electronic device
CN116230763B (en) * 2022-03-18 2024-03-15 北京超弦存储器研究院 MOS tube, memory and manufacturing method thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412868A (en) * 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
EP0098111B1 (en) * 1982-06-24 1989-08-09 Harris Semiconductor Patents, Inc. Vertical igfet device and method for fabricating same
US4740826A (en) * 1985-09-25 1988-04-26 Texas Instruments Incorporated Vertical inverter
US4788158A (en) * 1985-09-25 1988-11-29 Texas Instruments Incorporated Method of making vertical inverter
US4824797A (en) * 1985-10-31 1989-04-25 International Business Machines Corporation Self-aligned channel stop
US5072276A (en) * 1986-10-08 1991-12-10 Texas Instruments Incorporated Elevated CMOS
US5164325A (en) * 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
US4992838A (en) * 1988-02-29 1991-02-12 Texas Instruments Incorporated Vertical MOS transistor with threshold voltage adjustment
US4942445A (en) * 1988-07-05 1990-07-17 General Electric Company Lateral depletion mode tyristor
US4951102A (en) * 1988-08-24 1990-08-21 Harris Corporation Trench gate VCMOS
JPH0266969A (en) * 1988-08-31 1990-03-07 Nec Corp Semiconductor integrated circuit device
US4994871A (en) * 1988-12-02 1991-02-19 General Electric Company Insulated gate bipolar transistor with improved latch-up current level and safe operating area
MY107475A (en) * 1990-05-31 1995-12-30 Canon Kk Semiconductor device and method for producing the same.
US5240865A (en) * 1990-07-30 1993-08-31 Texas Instruments Incorporated Method of forming a thyristor on an SOI substrate

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DE4340967C1 (en) 1994-10-27
JPH07202216A (en) 1995-08-04
EP0656647A1 (en) 1995-06-07
TW274635B (en) 1996-04-21
EP0656647B1 (en) 1999-01-20
JP3851360B2 (en) 2006-11-29
DE59407691D1 (en) 1999-03-04
US5443992A (en) 1995-08-22

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