KR900015311A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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KR900015311A
KR900015311A KR1019900003459A KR900003459A KR900015311A KR 900015311 A KR900015311 A KR 900015311A KR 1019900003459 A KR1019900003459 A KR 1019900003459A KR 900003459 A KR900003459 A KR 900003459A KR 900015311 A KR900015311 A KR 900015311A
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polycrystalline silicon
silicon layer
conductive
semiconductor device
gate electrode
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KR1019900003459A
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Korean (ko)
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마사다까 미나미
가즈시게 사또오
아쯔오 와따나베
쇼욱지 슈꾸리
다가시 니시다
다까히로 나가노
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미다 가쓰시게
가부시기가이샤 히다찌세이사구쇼
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Publication of KR900015311A publication Critical patent/KR900015311A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/15Static random access memory [SRAM] devices comprising a resistor load element
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903FET configuration adapted for use as static memory cell

Abstract

내용 없음.No content.

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 반도체장치의 일실시예를 나타낸 단면구성도,1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention;

제2도는 상기 반도체장치에 조립되는 MOS트랜지스터로 이루어진 회로의 일실시예.2 is an embodiment of a circuit consisting of a MOS transistor assembled to the semiconductor device.

Claims (10)

적어도 동일채널형이고 게이트전극을 불순물을 함유시킨 다결정 실리콘층으로 구성한 2개 이상의 MOS트랜지스터와, 베이스전극을 불순물을 함유시킨 다결정 실리콘층으로 구성한 바이폴라 트랜지스터를 구비하는 반도체장치에 있어서 한쪽의 MOS트랜지스터의 게이트진극을 제1도전형 다결정 실리콘층으로 형성하는 공정과, 이 제l도전형 다결정 실리콘층의 측면을 절연막으로 피복하는 공정과, 다음쪽의 MOS트랜지스터의 게이트전극을 상기 제1도전형 다결정 실리콘층과는 다른 도전형의 다결정 실리콘층으로 형성하는 공정을 가지고 상기 바이폴라 트랜지스터의 베이스전극은 상기 제1도전형 다결정 실리콘층을 형성하는 상기 공정 및 상기 제1도전형 다결정 실리콘층과는 따른 도전형의 다결정 실리콘을 형성하는 상기 공정중 어느한쪽의 공정과 동시에 형성하도록 한 것을 특징으로 하는 반도체장치의 제조방법.A semiconductor device comprising at least two MOS transistors composed of a polycrystalline silicon layer containing at least the same channel type and containing a gate electrode, and a bipolar transistor composed of a polycrystalline silicon layer containing impurities with a base electrode. Forming a gate electrode into a first conductive polycrystalline silicon layer, covering a side surface of the first conductive polycrystalline silicon layer with an insulating film, and a gate electrode of a next MOS transistor; And a base electrode of the bipolar transistor, wherein the base electrode of the bipolar transistor forms a first conductive polycrystalline silicon layer and a conductive type according to the first conductive polycrystalline silicon layer. Same as any of the above processes for forming polycrystalline silicon of A method of manufacturing a semiconductor device, characterized in that to form the. 제1항에 있어서, 제1도전형 다결정 실리콘층과 다든 도전형의 다결청 실리콘의 측면을 절연막으로 피복하는 공정을 구비하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, further comprising a step of covering the side surfaces of the first conductive polycrystalline silicon layer and all conductive polycrystalline silicon with an insulating film. 제1항에 있어서, 바이폴라 트랜지스터의 이미터 전극도 불순물을 함유시킨 다결정 실리콘층으로 구성하도록 하고 이 다 결정 실리콘층을 상기 제1도전형 다결청 실리콘층을 형성하는 상기 공정 및 상기 제1도전형 다결정 실리콘층과는 다음 도전형의 다결정 실리콘을 형성하는 상기 공정중, 바이폴라 트랜지스터의 베이스 전극과 동시에 형성한 공정이외의 공정과 동시에 형성하도록 한 것을 특징으로 하는 반도체장치의 제조방법.The process of claim 1, wherein the emitter electrode of the bipolar transistor is also composed of a polycrystalline silicon layer containing impurities, and the polycrystalline silicon layer is formed of the first conductive polycrystalline silicon layer and the first conductive type. A method of manufacturing a semiconductor device, characterized in that the polycrystalline silicon layer is formed simultaneously with a process other than a process simultaneously formed with a base electrode of a bipolar transistor in the process of forming polycrystalline silicon of a next conductivity type. 제1항에 있어서, 각 MOS트랜지스터중 채널형과 다음 불순물을 함유하는 다결정 실리콘층을 형성하는 MOS트랜지스터에 있어서는 그 드레인층과 소오스층과의 사이의 채널영역에 상기드레인층과 소오스층과를 접속하는 동형의 반도체층을 형성하는 공정을 부가한 것을 특징으로 하는 반도체장치의 제조방법.2. The MOS transistor according to claim 1, wherein the drain layer and the source layer are connected to a channel region between the drain layer and the source layer in the MOS transistor which forms a polycrystalline silicon layer containing a channel type and the next impurity in each MOS transistor. A method of manufacturing a semiconductor device, comprising adding a step of forming a semiconductor layer of the same type. 상이한 채널형이고 게이트전극을 불순물을 함유시킨 다결정 실리콘층으로 구성한 2개이상의 MOS 트랜지스터와, 베이스전극을 불순물을 함유시킨 다결정 실리콘층으로 구성한 바이폴라 트랜지스터를 구비하는 반도체장지에 있어서, 한쪽의 MOS트랜지스터의 게이트 전극을 제1도전형 다결정 실리콘층으로 형성하는 공정과, 이 제1도전형 다결정 실리콘층과는 측면을 절연막으로 피복하는 공정과, 다음쪽의 MOS트랜지스터의 게이트전극을 상기 제1도전형 다결정 실리콘층과는 다른 도전형의 다결정 실리콘층으로 형성하는 공정을 가지고 상기 바이폴라 트랜지스터의 베이스전극은 상기 제1도전형 다결정 실리콘층을 형성하는 상기 공정 및 상기 제1도전형 다결정 실리콘층과는 따른 도전형의 다결정 실리콘을 형성하는 상기 공정의 어느한쪽의 공정과 동시에 형성하도록 한 것을 특징으로 하는 반도체장치의 제조방법.A semiconductor device comprising two or more MOS transistors each having a different channel type and comprising a polycrystalline silicon layer containing impurity gate electrodes, and a bipolar transistor composed of a polycrystalline silicon layer containing impurity base electrodes. Forming a gate electrode from a first conductive polycrystalline silicon layer, coating a side surface of the first conductive polycrystalline silicon layer with an insulating film, and a gate electrode of a next MOS transistor. A process of forming a polycrystalline silicon layer of a conductivity type different from that of the silicon layer, and the base electrode of the bipolar transistor has a conductivity according to the process of forming the first conductive polycrystalline silicon layer and the first conductive polycrystalline silicon layer. Simultaneous with any of the above processes for forming a polycrystalline silicon of a type The semiconductor device manufacturing method characterized in that it is formed in. 적어도 동일 채널형이고 게이트 전극을 뷸순물을 함유시킨 다결정 실리콘층으로 구성한 2개이상의 MOS트랜지스터를 구비하는 반도체장치에 있어서 한쪽의 MOS트랜지스터의 게이트전극을 제1도전형 다결정 실리콘층으로 형성하는 공정과, 이 제l도전형 다결정 실리콘층의 측면을 절연막으로 피복하는 공정과, 다른쪽의 MOS트랜지스터의 게이트 전극을 상기 제1도전형다결정 실리콘층과는 다른 도전형의 다결정 실리콘층으로 형성하는 공정으로 이루어지는 것을 특징으로하는 반도체장치의 제조방법.A semiconductor device comprising at least two MOS transistors having at least the same channel type and comprising a polycrystalline silicon layer containing a gate electrode, wherein the gate electrode of one MOS transistor is formed of a first conductive polycrystalline silicon layer; And a step of covering the side surface of the first conductive polycrystalline silicon layer with an insulating film and forming a gate electrode of the other MOS transistor from a polycrystalline silicon layer of a conductive type different from the first conductive polycrystalline silicon layer. A method for manufacturing a semiconductor device, characterized by the above-mentioned. 적어도 동일채널형이고, 게이트전극을 불순물을 함유시킨 다결정 실리콘층으로 구성한 2개이상의 MOS트랜지스터와, 베이스 전극을 불순물을 함유시킨 다결정 실리콘층으로 구성한 바이폴라 트랜지스터를 구비하는 반도체장치에 있어서 한쪽의 트랜지스터는 제1도전형 다결정 실리콘층으로 형성되고, 또 측면이 절연막으로 피복된 게이트전극을 다음쪽의 트랜지스터는 상기 제13도전형 다결정 실리콘층과 다른 도전형의 다결정 실리콘층으로 형성된 게이트전극을 가지고 상기 바이폴라 트랜지스터는 불순물을 함유시킨 다결정 실리콘층으로 형성된 베이스 전극을 가지는 것을 특징으로 하는 반도체장치.In a semiconductor device comprising at least two MOS transistors of at least the same channel type and comprising a polycrystalline silicon layer containing impurity gate electrodes, and a bipolar transistor comprising a polycrystalline silicon layer containing impurity base electrodes, one transistor comprises: The bipolar transistor has a gate electrode formed of a first conductive polycrystalline silicon layer and covered with an insulating film on its side, and the next transistor has a gate electrode formed of a conductive polycrystalline silicon layer different from the thirteenth conductive polycrystalline silicon layer. And the transistor has a base electrode formed of a polycrystalline silicon layer containing impurities. 제7항에 있어서, 제1도전형 다결정 실리콘층과 다른 도전현의 다결정 실리콘층의 측면은 절연막으로 피복되어있는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 7, wherein the side surfaces of the first conductive polycrystalline silicon layer and the polycrystalline silicon layer of the conductive string different from each other are covered with an insulating film. 제7항에 있어서, 바이폴라 트랜지스터는 다결정 실리콘층으로 형성된 이미터 전극을 가지는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 7, wherein the bipolar transistor has an emitter electrode formed of a polycrystalline silicon layer. 제9항에 있어서, 각 MOS트랜지스터중 채널형과 다음 불순물을 함유하는 다결정 실리콘층을 형성하는 MOS트랜지스터에 있어서는 그 드레인층과 소오스층과의 사이의 채널영역에 상기 드래인층과 소오스층을 접속하는 동형의 반도체층이 형성되어 있는 것을 특징으로 하는 반도체장치.10. The MOS transistor according to claim 9, wherein the drain layer and the source layer are connected to a channel region between the drain layer and the source layer in the MOS transistor which forms a polycrystalline silicon layer containing the channel type and the next impurity in each MOS transistor. A semiconductor device comprising the same type of semiconductor layer. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application.
KR1019900003459A 1989-03-20 1990-03-15 Semiconductor device and manufacturing method KR900015311A (en)

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JP89-67985 1989-03-20
JP1067985A JPH02246264A (en) 1989-03-20 1989-03-20 Semiconductor device and manufacture thereof

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US5134082A (en) * 1991-06-10 1992-07-28 Motorola, Inc. Method of fabricating a semiconductor structure having MOS and bipolar devices
KR930008018B1 (en) * 1991-06-27 1993-08-25 삼성전자 주식회사 Bicmos device and manufacturing method of the same
US5422499A (en) * 1993-02-22 1995-06-06 Micron Semiconductor, Inc. Sixteen megabit static random access memory (SRAM) cell
US5453636A (en) * 1994-08-16 1995-09-26 Waferscale Integration, Inc. MOS SRAM cell with open base bipolar loads
US5536962A (en) * 1994-11-07 1996-07-16 Motorola, Inc. Semiconductor device having a buried channel transistor
US5942786A (en) * 1996-02-01 1999-08-24 United Microelectronics Corp. Variable work function transistor high density mask ROM
US5896313A (en) * 1997-06-02 1999-04-20 Micron Technology, Inc. Vertical bipolar SRAM cell, array and system, and a method of making the cell and the array
US6100568A (en) * 1997-11-06 2000-08-08 Motorola, Inc. Semiconductor device including a memory cell and peripheral portion and method for forming same
TW521226B (en) * 2000-03-27 2003-02-21 Semiconductor Energy Lab Electro-optical device

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JPS60254653A (en) * 1984-05-30 1985-12-16 Fujitsu Ltd Semiconductor memory device
JPS63174354A (en) * 1987-01-14 1988-07-18 Hitachi Ltd Semiconductor storage device
EP0281711B1 (en) * 1987-01-28 1992-04-22 Advanced Micro Devices, Inc. Four-transistor (4t) static ram cells

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