KR920015565A - Method of manufacturing gate of semiconductor cell - Google Patents

Method of manufacturing gate of semiconductor cell Download PDF

Info

Publication number
KR920015565A
KR920015565A KR1019910000286A KR910000286A KR920015565A KR 920015565 A KR920015565 A KR 920015565A KR 1019910000286 A KR1019910000286 A KR 1019910000286A KR 910000286 A KR910000286 A KR 910000286A KR 920015565 A KR920015565 A KR 920015565A
Authority
KR
South Korea
Prior art keywords
gate
forming
oxide film
polysilicon
implanting
Prior art date
Application number
KR1019910000286A
Other languages
Korean (ko)
Other versions
KR0186020B1 (en
Inventor
박래학
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000286A priority Critical patent/KR0186020B1/en
Publication of KR920015565A publication Critical patent/KR920015565A/en
Application granted granted Critical
Publication of KR0186020B1 publication Critical patent/KR0186020B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

반도체 셀의 게이트 제조방법Method of manufacturing gate of semiconductor cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명이 공정 단면도.2 is a cross-sectional view of the present invention.

Claims (1)

CVD 산화막을 이용하여 실리콘 기판에 단차를 갖게 에치하는 공정과, 불순물을 주입하여 채널 스톱 영역을 형성하고 필드 산화막을 성장시키는 공정과, 게이트 산화막, 게이트 폴리실리콘, 캡 게이트 HTO를 형성하여 패터닝함으로 게이트를 형성한 후 저농도 이온을 주입하고 측벽 형성 후 고농도 이온을 주입하는 공정과, HTO를 형성하고 매몰 콘택 오픈 후 스토리지 노드 폴리실리콘, 고유전 물질, 플레이트 폴리실리콘을 형성하여 패터닝함으로 커패시터를 형성하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 반도체 셀의 게이트 제조방법.Using a CVD oxide film to etch a silicon substrate with a step, implanting impurities to form a channel stop region, growing a field oxide film, and forming and patterning a gate oxide film, a gate polysilicon, and a cap gate HTO. Forming a capacitor by implanting low-concentration ions after gate formation and implanting high-concentration ions after sidewall formation, and forming and patterning storage node polysilicon, high dielectric material, and plate polysilicon after forming HTO and opening a buried contact. A method of manufacturing a gate of a semiconductor cell, characterized in that the step is carried out sequentially. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910000286A 1991-01-10 1991-01-10 Method of manufacturing gate of semiconductor cell KR0186020B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000286A KR0186020B1 (en) 1991-01-10 1991-01-10 Method of manufacturing gate of semiconductor cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000286A KR0186020B1 (en) 1991-01-10 1991-01-10 Method of manufacturing gate of semiconductor cell

Publications (2)

Publication Number Publication Date
KR920015565A true KR920015565A (en) 1992-08-27
KR0186020B1 KR0186020B1 (en) 1999-03-20

Family

ID=19309613

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000286A KR0186020B1 (en) 1991-01-10 1991-01-10 Method of manufacturing gate of semiconductor cell

Country Status (1)

Country Link
KR (1) KR0186020B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100677770B1 (en) * 2005-01-14 2007-02-02 주식회사 하이닉스반도체 Semiconductor device with stack active region and method for manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618709B1 (en) * 2005-03-15 2006-09-06 주식회사 하이닉스반도체 Method for forming gate in semiconductor device
KR100721580B1 (en) * 2005-06-30 2007-05-23 주식회사 하이닉스반도체 Semiconductor device with step gated asymmetry recess and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100677770B1 (en) * 2005-01-14 2007-02-02 주식회사 하이닉스반도체 Semiconductor device with stack active region and method for manufacturing the same

Also Published As

Publication number Publication date
KR0186020B1 (en) 1999-03-20

Similar Documents

Publication Publication Date Title
KR930005257A (en) Thin film field effect element and its manufacturing method
KR950021772A (en) Method of manufacturing integrated circuit having at least one MOS transistor
KR920015565A (en) Method of manufacturing gate of semiconductor cell
KR920007143A (en) Fin-Stack Cell Manufacturing Method
KR980005882A (en) MOS transistor and its manufacturing method
KR940001460A (en) LDD manufacturing method of semiconductor device
KR910017635A (en) Memory Cell Capacitor Manufacturing Method
KR910020933A (en) CMOS transistor manufacturing method
KR910003657A (en) Manufacturing method of DRAM
KR910013550A (en) High capacity stack cell manufacturing method
KR920015566A (en) Memory Cell Manufacturing Method
KR920020595A (en) Manufacturing Method of Semiconductor Device
KR920010914A (en) Trench Capacitor Cell Manufacturing Method
KR920005389A (en) Manufacturing method of disposable gate sidewall capacitor cell
KR920015596A (en) Stack Capacitor Manufacturing Method
KR910001930A (en) Self-aligned Low Doped Junction Formation Method
KR920003458A (en) Semiconductor device manufacturing method
KR920015545A (en) Stack Capacitor Cell Manufacturing Method
KR940010382A (en) Transistor Manufacturing Method
KR920015632A (en) SOMOS device manufacturing method
KR900017148A (en) Manufacturing method of highly integrated trench type DRAM cell
KR920015442A (en) Method of manufacturing semiconductor memory device
KR920015532A (en) DRAM cell manufacturing method
KR900004034A (en) Fabrication Process of Transistor with Rightly Doped Drain Structure
KR930022476A (en) Method of manufacturing via hole in doped region

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091126

Year of fee payment: 12

EXPY Expiration of term