WO2023173679A1

WO2023173679A1 - Transistor and manufacturing method therefor, memory, and electronic device

Info

Publication number: WO2023173679A1
Application number: PCT/CN2022/113571
Authority: WO
Inventors: 戴瑾
Original assignee: 北京超弦存储器研究院
Priority date: 2022-03-18
Filing date: 2022-08-19
Publication date: 2023-09-21

Abstract

Embodiments of the present disclosure provide a transistor and a manufacturing method therefor, a memory, and an electronic device. The transistor comprises: a source layer; a semiconductor layer; a drain layer, wherein the source layer, the semiconductor layer and the drain layer are sequentially stacked on a substrate, the stacked drain layer and semiconductor layer are provided with a hole that opens from the upper surface of the drain layer and extends to the semiconductor layer, or the stacked drain layer and semiconductor layer are provided with a gap from the upper surface of the drain layer to the semiconductor layer; a gate, located in the hole or the gap of the semiconductor layer, a side surface of the gate being completely or partially surrounded by the semiconductor layer; and a gate insulating layer, located between the gate and the semiconductor layer and between the gate and the drain layer. The embodiments of the present disclosure can effectively reduce the area of a storage unit, increase the density, thus improve the device performance, and reduce the cost.

Description

Transistor and manufacturing method thereof, memory, electronic equipment

Related cross-references

This disclosure claims priority to the Chinese patent application with application number 202210278990.X filed with the State Intellectual Property Office on March 18, 2022, and claims priority with the application number 202210273227.8, the entire contents of these two priority applications are incorporated herein by reference.

Technical field

The present disclosure relates to the field of storage technology. Specifically, the present disclosure relates to a transistor and a manufacturing method thereof, a memory, and an electronic device.

Background technique

Memory is the main medium for data storage in electronic products. The rapid development of the electronics industry and the increasing volume of data have put forward technical requirements for memory to be miniaturized and to increase storage capacity.

However, the memory cell area of existing memories needs to be further shrunk and the density increased to improve device performance and reduce costs.

Contents of the invention

In view of the shortcomings of the existing methods, this disclosure proposes a transistor, a manufacturing method thereof, a memory, and an electronic device to solve the problem in the existing technology that the memory unit area needs to be further reduced and the density increased to improve device performance and reduce costs. question.

In a first aspect, an embodiment of the present disclosure provides a transistor, including:

source layer;

semiconductor layer;

Drain layer; wherein, the source layer, semiconductor layer, and drain layer are stacked on the substrate in sequence;

Wherein, the stacked drain layer and the semiconductor layer have a hole opening from the upper surface of the drain layer and extending to the semiconductor layer, or the stacked drain layer and the semiconductor layer have a hole from the upper surface of the drain layer to the semiconductor layer. Gaps, holes or gaps are located in the drain layer and the semiconductor layer;

The gate is located in a hole or gap in the semiconductor layer, and the side surface of the gate is fully or partially surrounded by the semiconductor layer;

A gate insulating layer is located between the gate electrode and the semiconductor layer, and between the gate electrode and the drain layer.

In some embodiments, the drain layer is not in contact with the side surface of the semiconductor layer, and the projections of the drain layer and the semiconductor layer on the substrate overlap.

In some embodiments, the hole in the semiconductor layer is a through hole, or the depth of the hole in the semiconductor layer is lower than the thickness of the semiconductor layer to form a non-through hole.

In some embodiments, the semiconductor layer is a metal oxide semiconductor layer.

In some embodiments, at least one of the source layer and the drain layer is a metal layer or an alloy layer.

In a second aspect, an embodiment of the present disclosure provides a memory, including a transistor, a word line, and a bit line. The transistor includes:

source layer;

semiconductor layer;

In some embodiments, the memory further includes an insulating layer located on the drain layer, the insulating layer has a through hole, the through hole is connected to the through hole on the drain layer, and a contact is provided in the insulating layer and the through hole in the drain layer. Electrode, one end of the contact electrode is connected to the gate located in the semiconductor layer, and the other end is connected to the word line.

In some embodiments, the source layer further includes a bit line disposed on the same layer as the source layer and extending away from the source layer.

In a third aspect, embodiments of the present disclosure provide a memory including a read transistor and a write transistor. The read transistor includes:

first source layer;

first semiconductor layer;

a first drain layer; wherein the first source layer, the first semiconductor layer, and the first drain layer are stacked on the substrate in sequence;

wherein the stacked first drain layer and the first semiconductor layer have holes opening from the upper surface of the first drain layer and extending to the first semiconductor layer, or the stacked first drain layer and the first semiconductor layer Having a gap from the upper surface of the first drain layer to the first semiconductor layer, the hole or gap being located in the first drain layer and the first semiconductor layer;

The first gate is located in the hole or gap in the first semiconductor layer, and the side surface of the first gate is fully or partially surrounded by the first semiconductor layer;

The first gate insulating layer is located between the first gate electrode and the first semiconductor layer, and between the first gate electrode and the first drain layer.

In some embodiments, the write transistor is located above the read transistor.

In some embodiments, the write transistor includes:

second drain layer;

second semiconductor layer;

a second source layer, wherein the second drain layer, the second semiconductor layer and the second source layer are stacked in sequence from close to the substrate to away from the substrate;

The second drain layer is columnar, and one end is connected to the second semiconductor layer, and the other end extends to the hole or gap of the first drain electrode and is connected to the first gate;

The second gate electrode surrounds the sidewall of the second semiconductor layer and is insulated from the second gate electrode.

In some embodiments, the second gate is annular and surrounds the sidewalls of the second semiconductor layer.

In some embodiments, the second gate has a gap as a sidewall, the second semiconductor layer is located in the gap and part of the sidewall is surrounded by the second gate.

In some embodiments, projections of the first gate and the second gate on the substrate overlap.

In some embodiments, the second semiconductor layer overlaps a projection of the first gate or the second gate on the substrate.

In some embodiments, the memory further includes a first word line, a first bit line, a second word line and a second bit line, the first word line is connected to the first gate, and the first bit line is connected to the first source. , the second word line is connected to the sidewall of the second gate, the second bit line is connected to the second source layer, the second word line, the first bit line and the second bit line are all located in a plane parallel to the substrate , the first word line is perpendicular to the substrate.

In some embodiments, the projections of the second word line and the second bit line on the substrate are perpendicular to each other, the second word line and the first bit line extend in the same direction, and the projections of the second word line and the first bit line on the substrate at least partially overlap.

In a fourth aspect, embodiments of the present disclosure provide an electronic device, including: a memory as provided in the second aspect, or a memory as provided in the third aspect.

In a fifth aspect, embodiments of the present disclosure provide a method for manufacturing a transistor, including:

provide a base;

Form a first conductive layer, a semiconductor material layer, and a second conductive layer respectively on the substrate;

The second conductive layer and the semiconductor material layer are patterned to form a hole opening from the upper surface of the second conductive layer and extending to the semiconductor material layer, or a gap or hole from the upper surface of the second conductive layer to the semiconductor material layer. Or the gap is located in the second conductive layer and the semiconductor material layer; the patterned second conductive layer is the drain, the first conductive layer is the source, and the semiconductor material layer is the semiconductor layer;

A gate insulating layer and a gate electrode are sequentially formed in the hole or gap in the semiconductor layer, so that the gate electrode fills the hole or gap in the semiconductor layer and is isolated from the semiconductor layer by the gate insulating layer.

Beneficial technical effects brought by the technical solutions provided by the embodiments of the present disclosure include: in the provided transistor, the source layer, the semiconductor layer and the drain layer are sequentially stacked on the substrate, that is, the source and drain are respectively connected with the semiconductor. Compared with the transistor structure in which the source and drain electrodes respectively surround the side walls of the semiconductor layer in the related art, the transistor structure arranged in stacked layers can effectively reduce the occupied area of the transistor, achieve further shrinkage of the transistor, and enable the application of the method provided by the present disclosure. The transistor memory can obtain a more compact structural layout, which is more conducive to device integration, that is, it is conducive to achieving both miniaturization of memory size and large-scale storage capacity. Additional aspects and advantages of the disclosure will be set forth in part in the description which follows, and will be obvious from the description, or may be learned by practice of the disclosure.

Description of the drawings

The above and/or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic three-dimensional structural diagram of a transistor provided by an embodiment of the present disclosure;

Figure 2 is a schematic cross-sectional structural diagram of a film layer of a transistor according to an embodiment of the present disclosure;

Figure 3 is a schematic cross-sectional structural diagram of the A-A plane in Figure 2;

Figure 4 is a schematic cross-sectional structural diagram of a film layer of a transistor according to an embodiment of the present disclosure;

Figure 5 is a schematic cross-sectional structural diagram of plane B-B in Figure 2;

Figure 6 is a schematic structural diagram of a transistor connected to a bit line according to an embodiment of the present disclosure;

Figure 7 is a schematic three-dimensional structural diagram of a memory provided by an embodiment of the present disclosure;

FIG. 8 is a schematic flowchart of a method of manufacturing a transistor according to an embodiment of the present disclosure.

In the picture:

100-transistor;

110-gate; 120-gate insulating layer; 130-semiconductor layer; 140-source layer; 150-drain layer; 160-contact electrode; 4-bit line;

1-Substrate; 2-Read transistor; 3-Write transistor;

21-first gate; 22-first gate insulating layer; 23-first semiconductor layer; 24-first drain layer; 25-first source layer; 26-first bit line;

31-second drain layer; 32-second source layer; 33-second semiconductor layer; 34-second gate insulating layer; 35-second gate; 36-second word line; 37-second bit line.

Detailed ways

The embodiments of the present disclosure are described below with reference to the drawings in the present disclosure. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present disclosure, and do not limit the technical solutions of the embodiments of the present disclosure.

Those skilled in the art will understand that, unless expressly stated otherwise, the singular forms "a", "an", "the" and "the" used herein may also include the plural form. It should be further understood that the word "comprising" used in the description of the present disclosure refers to the presence of the stated features, integers, steps, operations, elements and/or components, but does not exclude the implementation of other features, information supported by the technical field. , data, steps, operations, elements, components and/or their combinations, etc. It should be understood that when we refer to an element being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or one element and the other element may be connected to the other element through intervening elements. Establish connections. Additionally, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and/or" used herein refers to at least one of the items defined by the term. For example, "A and/or B" can be realized as "A", or as "B", or as "A and B" ".

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in further detail below in conjunction with the accompanying drawings.

Generally, the storage unit in the memory is mainly composed of transistors, and the size of the area occupied by the transistor will affect the degree of shrinkage of the storage unit.

An embodiment of a new structure transistor provided by the present disclosure will be described in detail as follows.

An embodiment of the present disclosure provides a transistor 100, as shown in FIGS. 1-5 , including: a source layer 140, a semiconductor layer 130, a drain layer 150, a gate 110 and a gate insulating layer 120.

Among them, the source layer 140, the semiconductor layer 130, and the drain layer 150 are stacked on the substrate in sequence.

The stacked drain layer 150 and the semiconductor layer 130 have holes opening from the upper surface of the drain layer 150 and extending to the semiconductor layer 130 , or the stacked drain layer 150 and the semiconductor layer 130 have holes extending from the upper surface of the drain layer 150 . Surface to semiconductor layer 130 gaps, holes or gaps are located in drain layer 150 and semiconductor layer 130 .

The gate electrode 110 is located in a hole or a gap in the semiconductor layer 130 , and the side surface of the gate electrode 110 is fully or partially surrounded by the semiconductor layer 130 .

The gate insulating layer 120 is located between the gate electrode 110 and the semiconductor layer 130 and between the gate electrode 110 and the drain layer 150 . It can be understood that the gate insulating layer 120 will also form a hole or gap that can accommodate the upper level.

In this embodiment, the source layer 140, the semiconductor layer 130 and the drain layer 150 in the transistor 100 are stacked on the substrate in sequence, that is, the transistor 100 structure is adopted in which the source and drain are stacked with the semiconductor layer 130 respectively. , compared with the structure of the transistor 100 in the related art in which the source and drain respectively surround the sidewalls of the semiconductor layer 130, the occupied area of the transistor 100 can be effectively reduced, further miniaturization of the transistor 100 can be achieved, and the transistor provided by the present disclosure can be applied. 100 memory can achieve a more compact structural layout, which is more conducive to device integration, that is, it is conducive to achieving both miniaturization of memory size and large storage capacity.

In the transistor 100 provided in this embodiment, when the gate 110 is not subject to an external voltage, the free electrons or holes in the semiconductor layer 130 are in a state that does not need to move, and the conductivity of the semiconductor layer 130 is extremely low or in an insulating state, that is, Transistor 100 is in an off state. When an external voltage is applied to the gate 110, the gate 110 and the semiconductor layer 130 are insulated by the gate insulating layer 120 and cannot be turned on. The potential difference formed between the gate 110 and the semiconductor layer 130 will activate, The conductivity of the semiconductor layer 130 is increased, and the source layer 140 and the drain layer 150 respectively in contact with the semiconductor layer 130 are turned on, that is, the transistor 100 is in a conductive state.

Referring to FIGS. 1 and 2 , a gate insulating layer 120 is separated between the hole walls of the hole formed on the gate electrode 110 and the drain layer 150 and the semiconductor layer 130 , that is, between the gate electrode 110 and the drain layer 150 , and The gate electrode 110 and the semiconductor layer 130 are insulated by the gate insulating layer 120 .

The gate 110 can be formed by opening a hole or a gap in the drain layer 150 and then filling the hole or gap with metal, which is beneficial to further reducing the occupied area of the transistor 100 and making the structure of the transistor 100 more compact. It is also easy to implement technically.

In some examples, the gate 110 may be located in a region near the middle of the drain layer 150. Correspondingly, a hole may be opened in or near the center of the drain layer 150. As shown in FIGS. 2 and 3, the drain The layer 150 may completely surround the gate electrode 110. Of course, the drain layer 150 is separated from the gate electrode 110 by the gate insulating layer 120.

In some examples, the gate 110 may be located in the edge region of the drain layer 150. Correspondingly, a gap may be opened in the edge region of the drain layer 150. As shown in FIGS. 4 and 5, the drain layer 150 partially surrounds the gate. According to the different axial cross-sectional shapes of the gate electrode 110, the drain layer 150 has a structure such as a U-shape or a C-shape that does not completely surround the gate electrode 110. Similarly, the drain layer 150 and the gate electrode 110 are separated by a gate insulating layer 120 .

In some embodiments, the drain layer 150 is not in contact with the side surface of the semiconductor layer 130, and the projections of the drain layer 150 and the semiconductor layer 130 on the substrate overlap. This is beneficial to realizing a stacked three-dimensional structure between the gate electrode 110 and the drain layer 150 and the semiconductor layer 130 and the source layer 140 respectively, thereby reducing the area occupied by the transistor 100.

Exemplarily, the drain layer 150 only contacts the upper surface of the semiconductor layer 130, and the projections of the drain layer 150 and the semiconductor layer 130 on the substrate overlap.

In some examples, the semiconductor layer 130 is located between the source layer 140 and the drain layer 150 . The orthographic projection of the source layer 140 on the plane of the substrate and the orthographic projection of the drain layer 150 on the plane of the substrate are respectively different from the semiconductor layer 130 . Orthographic projections of the layers 130 on the plane of the substrate at least partially overlap.

In some embodiments, the holes in semiconductor layer 130 are vias. That is, the gate electrode 110 may penetrate the semiconductor layer 130 , and the semiconductor layer 130 may surround part of the sidewalls of the gate electrode 110 . Of course, the gate insulating layer 120 located between the semiconductor layer 130 and the gate electrode 110 also surrounds part of the sidewalls of the gate electrode 110 to ensure the insulation between the gate electrode 110 and the semiconductor layer 130 .

In some examples, the gate 110 adopts a columnar structure, which can effectively reduce the area occupied by the gate 110 and thereby reduce the area occupied by the transistor 100 .

In some embodiments, the depth of the hole in the semiconductor layer 130 is lower than the thickness of the semiconductor layer 130 to form a non-through hole. That is, the holes in the semiconductor layer 130 do not penetrate through the thickness direction of the semiconductor layer 130 , such as countersunk holes. In this way, the gate electrode 110 can extend into the semiconductor layer 130 but not penetrate the semiconductor layer 130. The semiconductor layer 130 can surround the bottom and part of the sidewalls of the gate electrode 110. Similarly, the gate insulating layer 120 located between the semiconductor layer 130 and the gate electrode 110 also surrounds the bottom and part of the sidewalls of the gate electrode 110 to ensure the insulation between the gate electrode 110 and the semiconductor layer 130 .

In some embodiments, edges of source layer 140 are at least partially aligned with edges of semiconductor layer 130 . This is beneficial to making the orthographic projection of the source layer 140 on the plane of the substrate and the orthographic projection of the semiconductor layer 130 on the plane of the substrate overlap more, which can further reduce the occupied area of the transistor 100 .

In some embodiments, edges of drain layer 150 are at least partially aligned with edges of semiconductor layer 130 . This is beneficial to making the orthographic projection of the drain layer 150 on the plane of the substrate and the orthographic projection of the semiconductor layer 130 on the plane of the substrate overlap more, which can further reduce the occupied area of the transistor 100 .

In some embodiments, the edge of the source layer 140 is at least partially aligned with the edge of the semiconductor layer 130, and the edge of the drain layer 150 is also at least partially aligned with the edge of the semiconductor layer 130. This is beneficial to making the orthographic projection of the source layer 140 on the plane of the substrate, the orthographic projection of the drain layer 150 on the plane of the substrate, and the orthographic projection of the semiconductor layer 130 on the plane of the substrate, so that the overlapping area of the three is larger. The occupied area of the transistor 100 can be further reduced.

In some embodiments, semiconductor layer 130 is a metal oxide semiconductor layer. The semiconductor layer 130 is made of metal oxide semiconductor material, which enables the transistor 100 to have the advantages of high carrier mobility and low light sensitivity.

In some examples, the semiconductor layer 130 may be a single layer or multiple layers, and the materials of each layer may be the same or different. The material of the semiconductor layer 130 includes an oxide of at least one of in, Ga, Zn, Sn, rare earth elements, heavy metal elements, and the like. For example, the material of the semiconductor layer 130 may be a metal oxide including ITO (Indium tin oxide), IWO (Indium Tungsten oxide) or IGZO (Indium Gallium Zinc Oxide). things. The material of the semiconductor layer 130 may also include, for example, ZnO _x , InO _x , In ₂ O ₃ , InWO, SnO ₂ , TiO _x , InSnO _x , Zn _x O _y N z , Mg _x Zn _y _{O z} _, In _x Zn _y O _z , In _x Ga _y Zn _z O _a , Zr _x In _y Zn _z O _a , Hf _x In _y Zn _z O _a , Sn _x In y Zn z O _a , Al _x _ZnO , _{Al x} _Sn _y In _z Zn _a O _d , Si _x In _y Zn _z O _a , Zn _x Sn _y O _z , Al _x Zn _y Sn _z O _a , Ga _x Zn _y Sn _z O _a , Zr _x Zn _y Sn _z O _a , InGaSiO and other materials .

The above-mentioned materials only represent combinations of types of elements, and are not limited to their atomic number ratio or crystallographic state.

In some embodiments, at least one of the source layer 140 and the drain layer 150 is a metal layer or alloy layer. For example, at least one material of the source layer 140 and the drain layer 150 is tungsten or copper.

In some embodiments, the cross-sectional shape of the source layer 140 and the drain layer 150 may be rectangular, circular, etc., and when the first gate 110 is annular, the cross-sectional shape may be rectangular, circular, etc., specifically, Make adjustments according to actual conditions. Wherein, the aforementioned cross-section is a cross-section taken in a direction parallel to the substrate.

Based on the same inventive concept, an embodiment of the present disclosure provides a memory, which includes a transistor 100 , a word line, and a bit line 4 . As shown in FIG. 6 , the transistor 100 includes: a source layer 140 , a semiconductor layer 130 , a drain layer 150 , a gate 110 and a gate insulating layer 120 .

Among them, the source layer 140, the semiconductor layer 130, and the drain layer 150 are stacked on the substrate 1 in sequence.

The gate insulating layer 120 is located between the gate electrode 110 and the semiconductor layer 130 and between the gate electrode 110 and the drain layer 150 .

In this embodiment, since the memory includes any of the transistors 100 provided in the previous embodiments, the implementation principles and beneficial effects are similar and will not be described again here.

The word line and bit line 4 may be connected to the gate 110 and the source layer 140 respectively to help the transistor 100 achieve read or write control.

In some embodiments, the memory further includes an insulating layer located on the drain layer 150 , the insulating layer having a through hole in communication with the through hole on the drain layer 150 , the insulating layer and the through hole in the drain layer 150 A contact electrode 160 is provided therein. One end of the contact electrode 160 is connected to the gate 110 located in the semiconductor layer 130 and the other end is connected to the word line.

In this embodiment, the insulating layer is located above the drain layer 150 , that is, on the side of the drain layer 150 away from the source layer 140 . This is beneficial to separating and insulating the word line from the drain layer 150 and contacting the electrode 160 . The overlap between gate 110 and word line in transistor 100.

In some embodiments, the source layer 140 further includes a bit line 4 disposed on the same layer as the source layer 140 and extending in a direction away from the source layer 140 . That is, the bit line 4 and the source layer 140 can be integrally formed. During the manufacturing process, the bit line 4 and the source layer 140 are formed through the same patterning process, thereby simplifying the manufacturing process of the memory and reducing the manufacturing cost.

In some embodiments, the memory includes a plurality of memory cells arranged in an array, and each memory cell includes any type of transistor 100 provided by the embodiments of the present disclosure.

In some examples, when the line width of the signal line (such as word line or bit line, etc.) is the feature size (Feature Size, F), multiple memory cells form an array, so that the same layer of two adjacent memory cells The signal line spacing is also 1F, so the minimum area of the memory cell is 4F ² . This reduces the area of a single storage unit and increases the density of storage units in the memory, which is conducive to the miniaturization, thinness, and integration of the memory.

In some embodiments, the transistor may be used as a read transistor or a write transistor, which may be determined based on the actual situation.

Based on the same inventive concept, an embodiment of the present disclosure provides a memory. As shown in FIG. 7 , the memory includes a read transistor 2 and a write transistor 3 .

The read transistor 2 includes: a first source layer 25 , a first semiconductor layer 23 , a first drain layer 24 , a first gate 21 and a first gate insulating layer 22 .

The first source layer 25 , the first semiconductor layer 23 , and the first drain layer 24 are stacked on the substrate 1 in sequence.

The stacked first drain layer 24 and the first semiconductor layer 23 have holes opening from the upper surface of the first drain layer 24 and extending to the first semiconductor layer 23, or the stacked first drain layer 24 and the first semiconductor layer 23 have holes. A semiconductor layer 23 has a gap from the upper surface of the first drain layer 24 to the first semiconductor layer 23 , and holes or gaps are located in the first drain layer 24 and the first semiconductor layer 23 .

The first gate 21 is located in the hole or gap of the first semiconductor layer 23 , and the side surface of the first gate 21 is fully or partially surrounded by the first semiconductor layer 23 .

The first gate insulating layer 22 is located between the first gate electrode 21 and the first semiconductor layer 23 , and between the first gate electrode 21 and the first drain layer 24 .

The write transistor 3 includes: a second drain layer 31, a second semiconductor layer 33, a second source layer 32, and a second gate insulating layer 34.

Among them, the second drain layer 31 , the second semiconductor layer 33 and the second source layer 32 are stacked in sequence from the direction close to the substrate 1 to away from the substrate 1 .

The second drain layer 31 is columnar, with one end connected to the second semiconductor layer 33 , and the other end extending to the hole or notch of the first drain and connected to the first gate 21 .

The second gate electrode 35 surrounds the sidewall of the second semiconductor layer 33 and is insulated from the second gate electrode 35 . The second gate insulating layer 34 is located between the second gate 35 and the second semiconductor layer 33 .

In this embodiment, the read transistor 2 adopts any of the transistor structures provided in the previous embodiments, that is, the first source layer 25, the first semiconductor layer 23 and the first drain layer 24 in the read transistor 2 are stacked in sequence. On the substrate 1, a read transistor 2 structure is adopted in which the first source electrode and the first drain electrode are respectively stacked with the first semiconductor layer 23. Compared with the related art in which the source electrode and the drain electrode respectively surround the side walls of the semiconductor layer, In terms of the transistor structure, it can effectively reduce the area occupied by the read transistor 2, realize further shrinkage of the read transistor 2, and enable the memory using the read transistor 2 to obtain a more compact structural layout, which is more conducive to device integration, that is, it is conducive to both Achieve miniaturization of memory size and enlargement of storage capacity.

The second source layer 32, the second semiconductor layer 33 and the second drain layer 31 in the write transistor 3 adopt a stacked structure, so that the second source layer 32, the second semiconductor layer 33 and the second drain layer 31 are included. The overall structure is conducive to forming a structure that is vertical or substantially vertical to the substrate 1, which can effectively reduce the area occupied by the write transistor 3, thereby helping the memory using the write transistor 3 to obtain a more compact structural layout, which is more conducive to device integration.

Between the read transistor 2 and the write transistor 3 in the memory cell, the second drain in the write transistor 3 is connected to the first gate 21 in the read transistor 2, which is beneficial to realizing the connection between the read transistor 2 and the write transistor 3 on the substrate. Forming a stacked structure on 1 helps to reduce the overall occupied area including the read transistor 2 and the write transistor 3.

In some embodiments, the orthographic projection of the second source layer 32 on the plane of the substrate 1 , the orthographic projection of the second drain on the plane of the substrate 1 and the orthographic projection of the second semiconductor layer 33 on the plane of the substrate 1 At least partially overlap.

In some embodiments, write transistor 3 is located above read transistor 2 . It is beneficial to realize the stacking structure between the read and write transistors 3, thereby increasing the device density of the memory.

In some embodiments, the second gate 35 in the write transistor 3 is annular and surrounds the sidewalls of the second semiconductor layer 33 .

In some embodiments, the second gate 35 in the write transistor 3 has a gap for the sidewall, the second semiconductor layer 33 is located in the gap and part of the sidewall is surrounded by the second gate 35 .

In some embodiments, the projections of the first gate 21 and the second gate 35 on the substrate 1 overlap. It is beneficial to align the stacked structure composed of the read transistor 2 and the write transistor 3 up and down, reduce the occupied area, and increase the device density of the memory.

In some embodiments, the second semiconductor layer 33 overlaps with the projection of the first gate electrode 21 or the second gate electrode 35 on the substrate 1 . It can also help align the top and bottom of the stacked structure composed of the read transistor 2 and the write transistor 3, reduce the occupied area, and increase the device density of the memory.

In some embodiments, the memory further includes a first word line, a first bit line 26, a second word line 36, and a second bit line 37. The first word line is connected to the first gate 21, and the first bit line 26 is connected to the first gate 21. The first source is connected, the second word line 36 is connected to the sidewall of the second gate 35, the second bit line 37 is connected to the second source layer 32, the second word line 36, the first bit line 26 and the second The bit lines 37 are all located in a plane parallel to the substrate 1 , and the first word line is perpendicular to the substrate 1 .

In this embodiment, the first word line and the first bit line 26 respectively connected to the read transistor 2 can help the read transistor 2 realize reading control. Similarly, the second word line 36 and the second bit line 37 respectively connected to the write transistor 3 can help the write transistor 3 realize writing control.

In some embodiments, the projections of the second word line 36 and the second bit line 37 on the substrate 1 are perpendicular to each other, the second word line 36 and the first bit line 26 extend in the same direction, and the projections of the second word line 36 and the first bit line 26 on the substrate 1 at least partially overlap.

Based on the same inventive concept, embodiments of the present disclosure provide an electronic device. The electronic device includes any of the memories provided in the above embodiments.

In this embodiment, since the electronic device includes any of the memories provided in the previous embodiments, the implementation principles and beneficial effects are similar and will not be described again here.

Optionally, the electronic device in the embodiment of the present disclosure may include: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device or a mobile power supply, etc.

Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing a transistor. The schematic flow chart of the manufacturing method is shown in Figure 8 and includes the following steps S101-S104:

S101: Provide a base.

In some examples, the substrate provided in step S101 may be a substrate specially provided for manufacturing transistors, such as a glass substrate; it may also be the substrate 1 in a memory where the transistor is applied.

S102: Form a first conductive layer, a semiconductor material layer, and a second conductive layer respectively on the substrate.

In some examples, step S102 may use a material deposition process to form the first conductive layer, the semiconductor material layer, and the second conductive layer layer by layer, so that the first conductive layer contacts the side of the semiconductor material layer close to the substrate, and the second conductive layer contacts the side of the semiconductor material layer close to the substrate. The conductive layer is in contact with a side of the semiconductor material layer away from the substrate.

S103: Pattern the second conductive layer and the semiconductor material layer to form a hole opening from the upper surface of the second conductive layer and extending to the semiconductor material layer, or a gap from the upper surface of the second conductive layer to the semiconductor material layer. , the holes or gaps are located in the second conductive layer and the semiconductor material layer; the patterned second conductive layer is the drain, the first conductive layer is the source, and the semiconductor material layer is the semiconductor layer.

In some examples, step S103 may pattern the second conductive layer and the semiconductor material layer through a photolithography process, or may pattern the second conductive layer and the semiconductor material layer through chemical etching.

S104: Sequentially fabricate a gate insulating layer and a gate electrode in the hole or gap in the semiconductor layer, so that the gate electrode fills the hole or gap in the semiconductor layer and is isolated from the semiconductor layer by the gate insulating layer.

In some examples, step S104 may fill the hole or gap in the semiconductor layer 130 with a gate insulating material, and then etching the gate insulating material to obtain the inner wall of the hole or gap surrounding the semiconductor layer 130 and the gate at the bottom. The gate insulating layer 120 is formed, and then the gate 110 is formed by filling the holes of the gate insulating layer 120 with metal material.

In the transistor 100 obtained through the preparation method including the above steps S101-S104, the source layer 140, the semiconductor layer 130 and the drain layer 150 are sequentially stacked on the substrate 1, that is, the source and drain are stacked with the semiconductor layer respectively. Compared with the transistor structure in the related art in which the source and drain respectively surround the sidewalls of the semiconductor layer, the transistor structure can effectively reduce the occupied area of the transistor, realize further shrinkage of the transistor, and enable the application of the transistor provided by the present disclosure. The memory can obtain a more compact structural layout, which is more conducive to device integration, that is, it is conducive to achieving both miniaturization of memory size and large-scale storage capacity.

By applying the embodiments of the present disclosure, at least the following beneficial effects can be achieved:

1. The source layer, semiconductor layer and drain layer in the transistor are stacked on the substrate in sequence, that is, a transistor structure in which the source and drain are stacked with the semiconductor layer is used. Compared with the source and drain in related technologies, For a transistor structure that surrounds the sidewalls of the semiconductor layer, it can effectively reduce the area occupied by the transistor and achieve further shrinkage of the transistor, so that the memory using the transistor provided by the present disclosure can obtain a more compact structural layout, which is more conducive to the device Integration is conducive to achieving both miniaturization of memory size and enlargement of storage capacity.

2. The drain layer is only in contact with the upper surface of the semiconductor layer, and the projections of the holes or gaps on the drain layer and the semiconductor layer on the substrate overlap. This is conducive to realizing a stacked three-dimensional structure between the gate and drain layers, the semiconductor layer, and the source layer respectively, thereby reducing the area occupied by the transistor.

3. The holes in the semiconductor layer are through holes. That is, the gate electrode may penetrate the semiconductor layer, and the semiconductor layer may surround part of the sidewalls of the gate electrode. Of course, the gate insulating layer located between the semiconductor layer and the gate electrode also surrounds part of the sidewalls of the gate electrode to ensure insulation between the gate electrode and the semiconductor layer.

4. The depth of the hole in the semiconductor layer is lower than the thickness of the semiconductor layer. That is, the gate may extend into the semiconductor layer, but not through the semiconductor layer, and the semiconductor layer may surround the bottom and part of the sidewalls of the gate. Similarly, the gate insulating layer located between the semiconductor layer and the gate electrode also surrounds the bottom and part of the sidewall of the gate electrode to ensure the insulation between the gate electrode and the semiconductor layer.

5. The semiconductor layer uses metal oxide semiconductor materials, which allows the transistor to have the advantages of high carrier mobility and low light sensitivity.

Those skilled in the art can understand that the steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this disclosure can be alternated, changed, combined, or deleted. Further, other steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this disclosure may also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, the steps, measures, and solutions in the various operations, methods, and processes disclosed in the present disclosure in the prior art can also be replaced, changed, rearranged, decomposed, combined, or deleted.

In the description of the present disclosure, the words "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", " The directions or positional relationships indicated by "bottom", "inner", "outside", etc. are based on the exemplary directions or positional relationships shown in the drawings, and are for convenience of describing or simplifying the description of the embodiments of the present disclosure, rather than indicating or It is implied that the device or component referred to must have a particular orientation, be constructed and operate in a particular orientation and therefore is not to be construed as a limitation on the disclosure.

The terms “first” and “second” are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present disclosure, "plurality" means two or more unless otherwise specified.

In the description of the present disclosure, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood on a case-by-case basis.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that although various steps in the flowchart of the accompanying drawings are shown in sequence as indicated by arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of the embodiments of the present disclosure, the steps in each process may be executed in other orders according to requirements. Furthermore, some or all of the steps in each flowchart are based on actual implementation scenarios and may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, or can be executed at different times. In scenarios with different execution times, the execution order of these sub-steps or stages can be flexibly configured according to needs. Implementation of this disclosure There is no limit to this.

The above are only some embodiments of the present disclosure. It should be noted that for those of ordinary skill in the art, other similar implementation means based on the technical ideas of the present disclosure may be adopted without departing from the technical concepts of the present disclosure. , also belongs to the protection scope of the embodiments of the present disclosure.

Claims

A transistor consisting of:

source layer;

semiconductor layer;

Drain layer; wherein, the source layer, the semiconductor layer and the drain layer are stacked on the substrate in sequence;

Wherein, the stacked drain layer and the semiconductor layer have holes opening from the upper surface of the drain layer and extending to the semiconductor layer, or the stacked drain layer and the semiconductor layer Having a gap from the upper surface of the drain layer to the semiconductor layer, the hole or the gap being located in the drain layer and the semiconductor layer;

A gate electrode located in the hole or the gap in the semiconductor layer, the side surface of the gate electrode being fully or partially surrounded by the semiconductor layer;

A gate insulating layer is located between the gate electrode and the semiconductor layer, and between the gate electrode and the drain layer.
The transistor of claim 1, wherein the drain layer is not in contact with a side surface of the semiconductor layer, and projections of the drain layer and the semiconductor layer on the substrate overlap.
The transistor according to claim 1, wherein the hole in the semiconductor layer is a through hole, or a depth of the hole in the semiconductor layer is lower than a thickness of the semiconductor layer to form a non-through hole.
The transistor of claim 1, wherein the semiconductor layer is a metal oxide semiconductor layer.
The transistor of claim 1, wherein at least one of the source layer and the drain layer is a metal layer or an alloy layer.
A memory includes a transistor, a word line and a bit line, the transistor includes:

source layer;

semiconductor layer;

Drain layer; wherein, the source layer, the semiconductor layer and the drain layer are stacked on the substrate in sequence;

Wherein, the stacked drain layer and the semiconductor layer have holes opening from the upper surface of the drain layer and extending to the semiconductor layer, or the stacked drain layer and the semiconductor layer Having a gap from the upper surface of the drain layer to the semiconductor layer, the hole or the gap being located in the drain layer and the semiconductor layer;

A gate electrode located in the hole or the gap in the semiconductor layer, the side surface of the gate electrode being fully or partially surrounded by the semiconductor layer;

A gate insulating layer is located between the gate electrode and the semiconductor layer, and between the gate electrode and the drain layer.
The memory of claim 6, wherein the memory further comprises an insulating layer located on the drain layer, the insulating layer having a through hole, the through hole being connected to the through hole on the drain layer , a contact electrode is provided in the through hole in the insulation layer and the drain layer, one end of the contact electrode is connected to the gate located in the semiconductor layer, and the other end is connected to the word line.
The memory of claim 6, wherein the source layer further includes the bit line disposed on the same layer as the source layer and extending in a direction away from the source layer.
A memory includes a read transistor and a write transistor, and the read transistor includes:

first source layer;

first semiconductor layer;

a first drain layer; wherein the first source layer, the first semiconductor layer, and the first drain layer are stacked on the substrate in sequence;

Wherein, the stacked first drain layer and the first semiconductor layer have holes opening from the upper surface of the first drain layer and extending to the first semiconductor layer, or the stacked first The first drain layer and the first semiconductor layer have a gap from an upper surface of the first drain layer to the first semiconductor layer, and the hole or the gap is located in the first drain layer and the first semiconductor layer. in the first semiconductor layer;

A first gate electrode located in the hole or the gap of the first semiconductor layer, and the side surface of the first gate electrode is fully or partially surrounded by the semiconductor layer;

A first gate insulating layer is located between the first gate electrode and the first semiconductor layer, and between the first gate electrode and the first drain layer.
The memory of claim 9, wherein the write transistor is located above the read transistor.
The memory of claim 9, wherein the write transistor includes:

second drain layer;

second semiconductor layer;

a second source layer, wherein the second drain layer, the second semiconductor layer and the second source layer are stacked in sequence from a direction close to the substrate to a direction away from the substrate;

The second drain layer is columnar, with one end connected to the second semiconductor layer, and the other end extending to the hole or the notch of the first drain connected to the first gate;

A second gate electrode is insulated from the second gate electrode by surrounding the sidewall of the second semiconductor layer.
The memory of claim 11, wherein the second gate is annular and surrounds sidewalls of the second semiconductor layer.
The memory of claim 11 , wherein the second gate has a gap as a sidewall, the second semiconductor layer is located in the gap and part of the sidewall is surrounded by the second gate.
The memory of claim 11, wherein projections of the first gate and the second gate on the substrate overlap.
The memory of claim 11, wherein the second semiconductor layer overlaps a projection of the first gate electrode or the second gate electrode on the substrate.
The memory of claim 11, wherein the memory further includes a first word line, a first bit line, a second word line, and a second bit line, the first word line being connected to the first gate. , the first bit line is connected to the first source, the second word line is connected to the sidewall of the second gate, and the second bit line is connected to the second source layer, The second word line, the first bit line and the second bit line are all located in a plane parallel to the substrate, and the first word line is perpendicular to the substrate.
The memory of claim 16, wherein the second word line and the second bit line are perpendicular to each other when projected on the substrate, the second word line and the first bit line extend in the same direction, and the projection on the substrate is at least Partially overlapping.
An electronic device, including: the memory as described in any one of claims 6-8 or 9-17.
A method of manufacturing a transistor, including:

provide a base;

Form a first conductive layer, a semiconductor material layer, and a second conductive layer respectively on the substrate;

The second conductive layer and the semiconductor material layer are patterned to form holes opening from the upper surface of the second conductive layer and extending to the semiconductor material layer, or forming holes from the upper surface of the second conductive layer. to the gap in the semiconductor material layer, the hole or the gap is located in the second conductive layer and the semiconductor material layer; the patterned second conductive layer is a drain, and the first conductive layer is The source electrode and semiconductor material layer are semiconductor layers;

A gate insulating layer and a gate electrode are sequentially formed in the hole or gap in the semiconductor layer, so that the gate electrode is filled in the hole or gap in the semiconductor layer and communicates with the semiconductor through the gate insulating layer. layer isolation.