CN116209254A

CN116209254A - 3D memory array, preparation method thereof and electronic equipment

Info

Publication number: CN116209254A
Application number: CN202211275548.8A
Authority: CN
Inventors: 戴瑾; 余泳; 梁静
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-10-18
Filing date: 2022-10-18
Publication date: 2023-06-02
Anticipated expiration: 2042-10-18
Also published as: WO2024082403A1; CN116209254B

Abstract

3D memory array, preparation method thereof and electronic equipment, wherein the 3D memory array comprises: a multi-layered vertically stacked memory array, a plurality of vertically extending write word lines; the memory array comprises a plurality of memory cells, a plurality of read bit lines and a plurality of write bit lines which are distributed in the array, wherein the memory cells comprise: a first transistor and a second transistor of a horizontal channel, the first transistor including a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer; the second transistor comprises a third electrode, a fourth electrode, a second grid electrode extending along the direction vertical to the substrate, and a second semiconductor layer surrounding the second grid electrode, wherein the first grid electrode is connected with the second semiconductor layer; the second grid electrodes of the adjacent memory cells in different layers are connected with the same write word line; the first electrodes of the memory cells in the same layer and column are connected with the same read bit line, and the fourth electrodes are connected with the same write bit line. The scheme provided by the embodiment provides a novel storage array structural design, is favorable for realizing a 3D storage array which is simple in structure and easy to manufacture.

Description

3D memory array, preparation method thereof and electronic equipment

Technical Field

Embodiments of the present disclosure relate to, but not limited to, semiconductor technology, and in particular, to a 3D memory array, a method for manufacturing the same, and an electronic device.

Background

Currently, a common dynamic random access memory (Dynamic Random Access Memory, DRAM) cell structure is of the 1T1C type, i.e., a transistor source-to-capacitor structure. The structure stores data by using the capacitor, but the electric quantity of the capacitor is consumed during reading, and the capacitor itself is leaked, so that the electric charge in the capacitor needs to be continuously refreshed, and the power consumption is high. Meanwhile, the technology for manufacturing the capacitor occupies a large area, and the size shrinkage is also a difficult problem.

The two-transistor non-capacitive memory cell (2Transistor 0Capacitor,2T0C) uses two transistors as the cell structure, uses gate capacitance to store charge and changes the transistor transconductance to store information. However, 2t0c DRAM cells typically use 2 horizontal channel transistors connected in the same plane, which occupies a large area, has a low integration density, and is complex in the stacking process and costly.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a 3D memory array, a preparation method thereof and electronic equipment, and the 3D memory array simplifies the process and reduces the cost.

The disclosed embodiments provide a 3D memory array, including: a plurality of memory arrays stacked in a direction perpendicular to a substrate, a plurality of write word lines extending in a direction perpendicular to the substrate; the memory array includes a plurality of memory cells, a plurality of read bit lines, and a plurality of write bit lines distributed in an array, the memory cells including: a first transistor and a second transistor disposed on the substrate, wherein:

The first transistor includes a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer disposed on the substrate;

the second transistor comprises a third electrode, a fourth electrode, a second grid electrode and a second semiconductor layer, wherein the third electrode and the fourth electrode are arranged on the substrate, the second grid electrode extends along the direction perpendicular to the substrate, the second semiconductor layer surrounds the second grid electrode and is insulated from the second grid electrode, and the first grid electrode is connected with the second semiconductor layer; the second semiconductor layer comprises a second source contact area and a second drain contact area which are arranged at intervals, the third electrode is in contact with the second source contact area of the second semiconductor layer, the fourth electrode is in contact with the second drain contact area of the second semiconductor layer, and a channel between the second source contact area and the second drain contact area is a horizontal channel;

the second grid electrodes of the adjacent memory cells along the direction perpendicular to the substrate are connected with the same write word line;

the first electrodes of the memory cells of the same column of the same layer are connected with the same read bit line;

the fourth electrodes of the memory cells of the same column of the same layer are connected to the same write bit line.

In an exemplary implementation, the second gate of adjacent ones of the memory cells of different layers is part of a write word line to which the second gate is connected.

In an exemplary implementation, the first electrodes of the memory cells of the same column of the same layer are part of a read bit line to which the first electrodes are connected.

In an exemplary implementation, the fourth electrode of the memory cells of the same column of the same layer is part of the write bit line to which the fourth electrode is connected.

In an exemplary implementation, the 3D memory array further includes a plurality of read word lines extending in a direction perpendicular to the substrate, the second electrodes of adjacent memory cells in the direction perpendicular to the substrate being connected to the same read word line.

In an exemplary implementation, the second electrode of adjacent ones of the memory cells of different layers is part of a read word line to which the second electrode is connected.

In an exemplary implementation, in the same memory array, the memory cells of the first column are connected to the same read bit line as the first electrode or the fourth electrode of the memory cells of the adjacent column are connected to the same write bit line, the memory cells of the last column are connected to the same read bit line as the first electrode or the fourth electrode of the memory cells of the adjacent column are connected to the same write bit line, the memory cells of other columns except for the first column and the last column are connected to the same read bit line as the first electrode of one of the memory cells of the adjacent two columns, and the fourth electrode of the memory cell of the other column is connected to the same write bit line.

In an exemplary implementation, the first semiconductor layer includes a first source contact region and a first drain contact region, the read bit line is connected to the first source contact region of the first semiconductor layer, and the write bit line is connected to the second drain contact region of the second semiconductor layer; the read word lines are respectively connected with first drain contact regions of the first semiconductor layers of the memory cells of different layers.

In an exemplary implementation, the read word line surrounds sidewalls of each first semiconductor layer of the memory cells of different layers and is connected to a first drain contact region of the sidewalls of each first semiconductor layer.

In an exemplary implementation, the first semiconductor layer includes a sidewall, a first end connected to a second source contact region of the second semiconductor layer, and a second end connected to the read bit line.

In an exemplary implementation, the second semiconductor layers of the second transistors of adjacent ones of the memory cells of different layers are spaced apart in a direction perpendicular to the substrate.

In an exemplary implementation, an insulating layer is exposed between the second semiconductor layers disposed at intervals, and the insulating layer is a second gate insulating layer between the second gate electrode and the second semiconductor layer.

In an exemplary implementation, the second semiconductor layers of the second transistors of adjacent ones of the memory cells of different layers are connected as a unitary structure.

In an exemplary implementation, the first gate is all or a portion of the third electrode.

In an exemplary implementation, the first gate is connected with a second source contact region of the second semiconductor layer.

In an exemplary implementation, the second drain contact region of the second semiconductor layer is opposite to and spaced apart from the second source contact region of the second semiconductor layer on a sidewall of the second semiconductor layer.

In an exemplary implementation, the first semiconductor layer includes a sidewall and two ends, the first semiconductor layer includes a first source contact region and a first drain contact region, the first drain contact region is located at the sidewall of the first semiconductor layer and surrounds the first semiconductor layer, the first source contact region is located at the sidewall of the first semiconductor layer and surrounds the first semiconductor layer, or is located at an end of the two ends away from the second gate.

In an exemplary implementation, the first electrode extends in a third direction, the first gate extends in a second direction, the third electrode extends in a second direction, the fourth electrode extends in a third direction, the second direction and the third direction are parallel to and intersect the substrate.

In an exemplary implementation, the orthographic projection of the first electrode does not overlap the orthographic projection of the second electrode in a plane parallel to the substrate; the orthographic projection of the third electrode does not overlap with the orthographic projection of the fourth electrode.

In an exemplary implementation, the first electrode, the second electrode, the third electrode are located on a first side of the second gate, the fourth electrode is located on a second side of the second gate, and the first side and the second side are opposite sides in a cross section perpendicular to the substrate.

In an exemplary implementation, a surface of the first electrode on a side closer to the substrate is less distant from the substrate than a surface of the third electrode on a side closer to the substrate is distant from the substrate, and a surface of the first electrode on a side farther from the substrate is distant from the substrate than a surface of the third electrode on a side farther from the substrate is distant from the substrate.

In an exemplary implementation, the first electrode, the third electrode, and the fourth electrode are located on the same conductive film layer along a direction perpendicular to the substrate.

In an exemplary implementation, the memory array includes a plurality of rows of memory cells and a plurality of columns of memory cells, the memory structure further comprising: a gating structure, the gating structure comprising: a row word line corresponding to a memory cell row of the memory array farthest from the substrate, a column word line corresponding to a memory cell column of the memory array farthest from the substrate, and a gate transistor corresponding to a memory cell of the memory array farthest from the substrate, the gate transistor including a fifth electrode, a sixth electrode, and a third gate, the third gate of the gate transistor corresponding to a memory cell of the same memory cell row being electrically connected to the same row word line, the sixth electrode of the gate transistor corresponding to a memory cell of the same memory cell column being electrically connected to the same column word line, the fifth electrode of the gate transistor being electrically connected to the second gate of the memory cell corresponding to the gate transistor.

In an exemplary implementation, the gating transistor further includes: a third semiconductor layer disposed on a side of the fifth electrode away from the substrate, a fourth gate insulating layer disposed on a side of the third semiconductor layer away from the substrate; the third semiconductor layer extends along the direction perpendicular to the substrate, the sixth electrode surrounds the third semiconductor layer, the third semiconductor layer is provided with a containing cavity, the third grid is at least partially arranged in the containing cavity, the third grid and the third semiconductor layer are isolated through the fourth grid insulating layer, and the orthographic projection of the third semiconductor layer on the substrate is located in the orthographic projection of the fifth electrode on the substrate.

An embodiment of the present disclosure provides an electronic device, including the 3D memory array described in any one of the embodiments above.

The embodiment of the disclosure provides a preparation method of a 3D memory array, wherein the 3D memory array comprises a plurality of layers of memory arrays stacked along a direction vertical to a substrate, and a plurality of write word lines extending along the direction vertical to the substrate; the memory array includes a plurality of memory cells distributed in an array, a plurality of read bit lines and a plurality of write bit lines, the memory cells including: a first transistor and a second transistor disposed on the substrate, the first transistor including a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer, the second transistor including a second gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer, the method of manufacturing comprising:

Forming a first gate electrode of a first transistor, a first semiconductor layer, a third electrode of a second transistor, a plurality of read bit lines and a plurality of write bit lines of memory cells of the plurality of memory arrays on a substrate, wherein the first electrode of the memory cells of the same column of the same layer is a part of the same read bit line, and the fourth electrode of the memory cells of the same column of the same layer is a part of the same write bit line;

forming a second semiconductor layer of a second transistor of a memory cell of the plurality of memory arrays on the substrate, and a plurality of write word lines extending in a direction perpendicular to the substrate, the second gates of adjacent memory cells of different layers being part of the same write word line; the second grid extends along the direction perpendicular to the substrate, the second semiconductor layer surrounds the second grid, and the first grid is connected with the second semiconductor layer; the second semiconductor layer comprises a second source contact area and a second drain contact area which are arranged at intervals, the third electrode is in contact with the second source contact area of the second semiconductor layer, the fourth electrode is in contact with the second drain contact area of the second semiconductor layer, and a channel between the second source contact area and the second drain contact area is a horizontal channel;

Patterning to form a plurality of read word lines extending in a direction perpendicular to the substrate, the second electrodes of adjacent memory cells of different layers being part of the same read word line.

In an exemplary implementation, the forming the first gate of the first transistor, the first semiconductor layer, the third electrode of the second transistor, the plurality of read bit lines, and the plurality of write bit lines on the substrate of the memory cells of the plurality of memory arrays includes:

sequentially depositing a plurality of insulating films and a plurality of metal films alternately on the substrate, and patterning to form a plurality of stacked structures; each of the stacked structures includes a stack of alternating insulating layers and metal layers, the metal layers including a plurality of first sub-portions and a plurality of second sub-portions, and a plurality of read bit lines;

etching the stacked structure to form a plurality of through holes penetrating the stacked structure in a direction perpendicular to the substrate, wherein the side walls of the through holes expose one first sub-part and one second sub-part of each metal layer and the insulating layer, the plurality of first sub-parts are etched to form a plurality of first channels, and the plurality of second sub-parts are etched to form a plurality of second channels;

depositing a semiconductor film, a first gate oxide film and a metal film on the side wall of a channel formed by the first channel, the second channel and the through hole in sequence, and etching the first gate oxide film and the metal film in the through hole to form a first semiconductor layer, a third electrode, a first gate and a write bit line in the first channel;

The forming a second semiconductor layer of a second transistor of a memory cell of the plurality of memory arrays on the substrate and a plurality of write word lines extending in a direction perpendicular to the substrate includes:

after etching the first gate oxide film and the metal film in the plurality of through holes, depositing a semiconductor film on the side wall of the through holes to form a second semiconductor layer of the second transistor;

and sequentially depositing a second gate oxide film and a metal film on the side walls of the plurality of through holes, wherein the metal film fills the through holes in the second gate oxide film to form the plurality of write word lines.

depositing a semiconductor film, a first gate oxide film and a metal film on the side wall of a channel formed by the first channel, the second channel and the through hole in sequence, and etching the metal film, the first gate oxide film and the semiconductor film in the through hole to form a first semiconductor layer, a third electrode, a first gate and a write bit line in the first channel;

the forming a second semiconductor layer of a second transistor of a memory cell of the plurality of memory arrays on the substrate and a plurality of write word lines extending in a direction perpendicular to the substrate includes: after the metal film, the first gate oxide film and the semiconductor film in the through holes are removed by etching, sequentially depositing a gate oxide film and a semiconductor film on the side walls of the through holes, wherein the first gate oxide film is not deposited on the side, facing the through holes, of the third electrode and the write bit line, and removing the semiconductor film attached to the first gate oxide film in the through holes so as to form a second semiconductor layer of the second transistor; and sequentially depositing a second gate oxide film and a metal film on the side walls of the plurality of through holes, wherein the metal film fills the through holes in the second gate oxide film to form the plurality of write word lines.

etching the stacked structure to form a plurality of through holes penetrating the stacked structure in a direction perpendicular to the substrate, wherein the side walls of the through holes expose one first sub-part and one second sub-part of each metal layer and the insulating layer, the plurality of first sub-parts are etched to form a plurality of first channels, the plurality of second sub-parts are etched to form a plurality of second channels, and the size of the through holes is smaller than that of the first channels along the extending direction perpendicular to the first channels;

depositing a semiconductor film, a first grid oxide film and a metal film on the side wall of a channel formed by the first channel, the second channel and the through holes in sequence, and etching to remove the first grid oxide film and the metal film in the plurality of through holes so as to form a first semiconductor layer, a third electrode, a first grid and a write bit line in the second channel, wherein the front projection of the semiconductor film in the through holes falls into the front projection of the through holes in the metal layer on a plane parallel to a substrate, and the front projection of the semiconductor film in the through holes is etched in the direction away from the through holes in the first channel and the second channel;

after etching the first gate oxide film and the metal film in the plurality of through holes, depositing a semiconductor film on the side walls of the plurality of through holes, and etching and removing the semiconductor film on the insulating layer in the plurality of through holes along the direction perpendicular to the substrate to form a second semiconductor layer of the second transistor;

depositing a semiconductor film, a first grid oxide film and a metal film on the side wall of a channel formed by the first channel, the second channel and the through hole in sequence, and etching the metal film in the through hole to form a first semiconductor layer, a third electrode, a first grid and a write bit line in the second channel; etching in the first channel and the second channel in a direction away from the through hole so that the orthographic projection of the semiconductor film positioned in the through hole falls into the orthographic projection of the through hole positioned in the metal layer on a plane parallel to the substrate;

after etching to remove the metal films in the through holes, depositing semiconductor films on the side walls of the through holes; etching to remove the semiconductor film and the first gate oxide film which are positioned in the insulating layer in the through hole along the direction perpendicular to the substrate so as to form a second semiconductor layer of the second transistor;

The embodiment of the disclosure comprises a 3D memory array, a preparation method thereof and electronic equipment, wherein the 3D memory array comprises: a plurality of memory arrays stacked in a direction perpendicular to a substrate, a plurality of write word lines extending in a direction perpendicular to the substrate; the memory array includes a plurality of memory cells, a plurality of read bit lines, and a plurality of write bit lines distributed in an array, the memory cells including: a first transistor and a second transistor disposed on the substrate, wherein: the first transistor includes a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer disposed on the substrate; the second transistor comprises a third electrode, a fourth electrode, a second grid electrode and a second semiconductor layer, wherein the third electrode and the fourth electrode are arranged on the substrate, the second grid electrode extends along the direction perpendicular to the substrate, the second semiconductor layer surrounds the second grid electrode and is insulated from the second grid electrode, and the first grid electrode is connected with the second semiconductor layer; the second semiconductor layer comprises a second source contact area and a second drain contact area which are arranged at intervals, the third electrode is in contact with the second source contact area of the second semiconductor layer, the fourth electrode is in contact with the second drain contact area of the second semiconductor layer, and a channel between the second source contact area and the second drain contact area is a horizontal channel; the second grid electrodes of the adjacent memory cells along the direction perpendicular to the substrate are connected with the same write word line; the first electrodes of the memory cells of the same column of the same layer are connected with the same read bit line; the fourth electrodes of the memory cells of the same column of the same layer are connected to the same write bit line. According to the scheme provided by the embodiment, the grid electrode of the second transistor of the 3D memory array is of a vertical structure, the channel is of a horizontal channel and is not stacked with the first transistor, the size of memory cells in the vertical substrate direction can be reduced, and memory cells in adjacent columns can share bit lines, so that the 3D stack of the 2T0C memory array with a compact structure can be conveniently manufactured, the process is simplified, and the cost is reduced.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities particularly pointed out in the specification and the appended drawings.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, and not constitute a limitation of the technical aspects.

FIG. 1 is a schematic cross-sectional view of a 3D memory array along a direction parallel to a substrate provided by an exemplary embodiment;

FIG. 2 is a schematic cross-sectional view of a 3D memory array along a direction perpendicular to a substrate according to an exemplary embodiment;

FIG. 3 is a schematic cross-sectional view of a 3D memory array along a direction perpendicular to a substrate provided by another exemplary embodiment;

FIG. 4 is a schematic illustration of a laminated structure according to an exemplary embodiment;

FIG. 5 is a schematic diagram of patterning a metal layer according to an exemplary embodiment;

fig. 6 is a schematic diagram of a second insulating layer formed according to an exemplary embodiment;

FIG. 7 is a schematic diagram of a through hole formed according to an exemplary embodiment;

FIG. 8A is a schematic diagram of an exemplary embodiment of a first and second channel formed;

FIG. 8B is a schematic horizontal cross-sectional view of a metal layer provided in an exemplary embodiment;

fig. 9A is a schematic view of an exemplary embodiment provided after forming a first semiconductor layer and a first gate insulating layer;

FIG. 9B is a partial schematic view of FIG. 9A;

fig. 9C is a cross-sectional view along BB of fig. 9B;

FIG. 10A is a schematic illustration of an exemplary embodiment after forming a second metal layer;

FIG. 10B is a partial schematic view of FIG. 10A;

FIG. 10C is a cross-sectional view along BB of FIG. 10B;

FIG. 11A is a schematic diagram of an exemplary embodiment of a second metal layer and a first gate insulating layer in a via hole etched;

FIG. 11B is a partial schematic view of FIG. 11A;

FIG. 11C is a cross-sectional view of FIG. 11B along BB;

fig. 12A is a schematic view of a second semiconductor layer, a second gate insulating layer, and a second gate electrode after forming according to an exemplary embodiment;

FIG. 12B is a partial schematic view of FIG. 12A;

FIG. 12C is a cross-sectional view of FIG. 12B along BB;

FIG. 13 is a schematic diagram of an exemplary embodiment of a slot structure;

FIG. 14 is a schematic illustration of an exemplary embodiment after forming a fourth metal layer;

FIG. 15A is a schematic illustration of a fourth metal layer split provided by an exemplary embodiment;

FIG. 15B is a partial view of FIG. 15A;

FIG. 16 is a schematic diagram of a 3D memory array according to an exemplary embodiment;

fig. 17A is a schematic diagram of another exemplary embodiment after forming a second metal layer and a first gate insulating layer in an etched via;

fig. 17B is a sectional view of fig. 17A along the BB direction;

fig. 18A is a schematic view of a third semiconductor layer formed according to another exemplary embodiment;

FIG. 18B is a schematic view of FIG. 18A along BB;

fig. 19A is a schematic diagram of a third semiconductor layer etched according to an exemplary embodiment;

FIG. 19B is a partial schematic view of FIG. 19A;

fig. 19C is a sectional view along BB of fig. 19B;

fig. 20A is a schematic view of a second gate insulating layer and a second gate electrode formed according to another exemplary embodiment;

FIG. 20B is a schematic view of FIG. 20A along BB;

FIG. 21 is a schematic diagram of an exemplary embodiment of a slot structure;

FIG. 22 is a schematic illustration of a fourth metal layer formed in accordance with an exemplary embodiment;

FIG. 23A is a schematic illustration of a fourth metal layer split provided by an exemplary embodiment;

FIG. 23B is a partial view of FIG. 23A;

FIG. 24 is a schematic diagram of a 3D memory array provided by another exemplary embodiment;

fig. 25 is a schematic view of another exemplary embodiment provided after forming a via;

fig. 26 is a schematic view of a second metal layer formed in accordance with another exemplary embodiment;

fig. 27A is a schematic view of another exemplary embodiment of a second metal layer and a first gate insulating layer in an etched via hole;

fig. 27B is a cross-sectional view of fig. 27A along the BB direction;

fig. 28A is a schematic view of a fourth semiconductor layer formed according to another exemplary embodiment;

fig. 28B is a cross-sectional view of fig. 28A along the BB direction;

fig. 29A is a schematic view of another exemplary embodiment of a first semiconductor layer and a fourth semiconductor layer in an etched via hole;

fig. 29B is a sectional view of fig. 29A along the BB direction;

fig. 30A is a schematic view of a second gate insulating layer and a second gate electrode formed according to another exemplary embodiment;

FIG. 30B is a schematic view of FIG. 30A along BB;

FIG. 31 is a schematic diagram of an exemplary embodiment of a slot structure;

FIG. 32 is a schematic illustration of a fourth metal layer formed in accordance with an exemplary embodiment;

FIG. 33A is a schematic diagram of a 3D memory array provided by an exemplary implementation;

FIG. 33B is a partial cross-sectional view of FIG. 33A along the BB direction;

fig. 34A is a schematic view of another exemplary embodiment of a second metal layer in an etched via;

fig. 34B is a sectional view of fig. 34A along the BB direction;

fig. 35 is a schematic view of a fifth semiconductor layer formed according to another exemplary embodiment;

fig. 36 is a schematic view of another exemplary embodiment of the etched first semiconductor layer, the first gate insulating layer, and the fifth semiconductor layer in the via hole;

fig. 37 is a schematic view of a second gate insulating layer and a second gate electrode formed according to another exemplary embodiment;

FIG. 38 is a schematic diagram of a 3D memory array provided by another exemplary implementation;

FIG. 39 is a schematic diagram of a 3D memory array provided by yet another exemplary embodiment;

FIG. 40A is a schematic diagram of a gating transistor provided in an exemplary embodiment;

FIG. 40B is a partial schematic diagram of the gating transistor shown in FIG. 40A;

fig. 41 is a flowchart of a method for preparing a 3D memory array according to an exemplary embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments of the present disclosure and features in the embodiments may be arbitrarily combined with each other without collision.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

Embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, the shapes and sizes of the various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or the numerical values shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present disclosure are provided to avoid intermixing of constituent elements, and do not denote any order, quantity, or importance.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the disclosure, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In the present disclosure, in the case of using a transistor having opposite polarity, the case of changing the direction of current during circuit operation, or the like, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In this disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, for example, and thus, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, for example, and thus includes a state in which an angle is 85 ° or more and 95 ° or less.

The term "the front projection of B is within the range of the front projection of a" in this disclosure means that the boundary of the front projection of B falls within the boundary of the front projection of a, or that the boundary of the front projection of a overlaps with the boundary of the front projection of B.

The "a and B integrated structure" in the embodiments of the present disclosure may refer to a microstructure without obvious boundary interfaces such as obvious faults or gaps. Typically, the connected film layers are patterned on one film layer as one piece. For example, a and B use the same material to form a film and simultaneously form a structure with a connection relationship through the same patterning process.

The embodiment of the application provides a 3D memory array which is more favorable for high-density design in space and industrialization in process aiming at a 2T0C 3D memory array.

Fig. 1 is a schematic plan view of a 3D memory array according to an exemplary embodiment, and fig. 2 is a schematic cross-sectional view of the 3D memory array shown in fig. 1. As shown in fig. 1 and 2, the present embodiment provides a 3D memory array, which may include:

a plurality of memory arrays stacked in a direction perpendicular to the substrate 1, a plurality of write word lines 120 extending in a direction perpendicular to the substrate 1, the memory arrays may include a plurality of memory cells, a plurality of read bit lines 330, and a plurality of write bit lines 520 distributed in an array, the memory cells including: a first transistor and a second transistor provided over the substrate 1, wherein:

The first transistor may include a first gate electrode 11, a first electrode 33, a second electrode 34, and a first semiconductor layer 6 disposed on the substrate 1;

the second transistor may include a third electrode 51, a fourth electrode 52, a second gate electrode 12 extending in a first direction Z, and a second semiconductor layer 9 surrounding the second gate electrode 12 and insulated from the second gate electrode 12, the first gate electrode 11 being connected to the second semiconductor layer 9, the second semiconductor layer 9 including second source contact regions 91 (not shown in fig. 1 and 2, please refer to fig. 12C) and second drain contact regions 92 (not shown in fig. 1 and 2), which are arranged at intervals, the third electrode 51 being in contact with the second source contact regions 91 of the second semiconductor layer 9, the fourth electrode 52 being in contact with the second drain contact regions 92 of the second semiconductor layer 9, a channel between the second source contact regions 91 and the second drain contact regions 92 being a horizontal channel; the first direction Z intersects the substrate 1;

the second gates 12 of adjacent memory cells along a direction perpendicular to the substrate 1 are connected to the same write word line 120;

the first electrodes 33 of the memory cells of the same column of the same layer are connected to the same read bit line 330;

The fourth electrodes 52 of the memory cells of the same column of the same layer are connected to the same write bit line 520.

Compared with a 3D memory array adopting two transistors with horizontal channels and a 3D memory array adopting two transistors with vertical channels, the 3D memory array adopting the transistors with the sources and the drains respectively positioned on one side of the vertical channels close to the substrate and one side of the vertical channels far away from the substrate, the grid electrode of the second transistor of the 3D memory array is of a vertical structure, the horizontal channels are not stacked with the first transistor, the size of the memory cells in the vertical substrate direction can be reduced, and the memory cells in adjacent columns can share bit lines, so that the 3D stack of the 2T0C memory array with a compact structure can be conveniently manufactured, the process is simplified, and the cost is reduced.

In the solution provided in this embodiment, the second semiconductor layer of the second transistor surrounds the second gate, and the source contact region and the drain contact region on the second semiconductor layer are arranged such that the channel direction between the source and the drain extends generally along a direction parallel to the substrate, for example, in an embodiment, there is an overlap between orthographic projections of the source electrode and the drain electrode in a plane parallel to the first direction. The structure of the memory array is designed into a novel structure, so that the structure between the first transistor and the second transistor is more compact, in addition, adjacent memory cells share bit lines, the structure can be more compact, in addition, when the 3D laminated memory cells are manufactured, the grid electrodes of the second transistors of all the laminated memory cells can be shared as word lines, and the word lines extending in the vertical direction enable the process of the 2T0C memory array to be simple and save space.

The horizontal channel described in the embodiments of the present application may be understood as one of non-vertical channels, and may be an embodiment in which a length direction of the channel or a transport direction of carriers is in a plane parallel to the substrate.

In some embodiments, the horizontal channel may be a planar channel or a circular channel.

In some embodiments, the channel of the second transistor may be a horizontal channel, and the channel may be planar (planar channel) or annular.

In some embodiments, the channel of the first transistor may be a horizontal channel, and the channel may be planar (planar channel) or annular.

The second transistor is a 3D structure with the grid extending along the vertical direction and the channel being a horizontal channel, and can be conveniently manufactured to be stacked in the vertical direction. In addition, the first transistors are first transistors with the first grid electrodes along the horizontal direction and the channels along the horizontal direction, so that the first transistors are conveniently separated in the vertical direction, and the first transistors and the second transistors with compact structures are realized.

The trenches may be approximately parallel to the substrate direction and the error may be within 10 degrees, depending on the relative position between the active source and drain electrodes in practical applications, e.g., the outer contour of the upper and/or lower surfaces of the electrodes in a longitudinal cross-sectional view of the source and drain electrodes are in a plane that is approximately parallel to the major surface of the substrate.

In the present disclosure, one of the first electrode 33 and the second electrode 34 is a source electrode, and the other is a drain electrode. The identification of a source or drain electrode in a product needs to be determined according to the flow direction of current, for example, the source electrode described in the embodiments of the present application may also be interpreted as a drain electrode according to the flow direction of current. The identification of a source or drain electrode in a product needs to be determined according to the flow direction of current, for example, the source electrode described in the embodiments of the present application may also be interpreted as a drain electrode according to the flow direction of current.

The second semiconductor layer 9 may be a full-around (channel-all-around) layer that is fully around the sidewall of the second gate electrode 12. The second semiconductor layer 9 is illustratively ring-shaped, the second semiconductor layer 9 is ring-shaped in cross section at each location of the second gate electrode 12, and the ring-shape is sized to fit the second gate electrode 12. Of course, the second semiconductor layer 9 may be partially encircling.

In an exemplary embodiment, the second gate 12 of an adjacent memory cell of a different layer is part of the second gate-connected write word line 120.

In an exemplary embodiment, the first electrodes 33 of the memory cells of the same column of the same layer are part of the read bit lines 330 to which the first electrodes 33 are connected.

In an exemplary embodiment, the fourth electrode 52 of the memory cells of the same column of the same layer is part of a write bit line 520 to which the fourth electrode 34 is connected.

In an exemplary embodiment, the 3D memory array further includes a plurality of read word lines 340 extending in a direction perpendicular to the substrate 1, and the second electrodes 34 of the memory cells adjacent in the direction perpendicular to the substrate are connected to the same read word line 340.

In an exemplary embodiment, the second electrode 34 of adjacent memory cells of different layers is part of a read word line 340 to which the second electrode 34 is connected.

In an exemplary embodiment, the second transistor may further include a second gate insulating layer 10 surrounding the second gate electrode 12, and the second semiconductor layer 9 is isolated from the second gate electrode 12 by the second gate insulating layer 10. The third electrode 51 and the fourth electrode 52 are insulated from the second gate electrode 12 by the second gate insulating layer 10.

In an exemplary embodiment, in a plane perpendicular to the substrate 1, the orthographic projection of the first gate electrode 11 overlaps with the orthographic projection of the third electrode 51, the orthographic projection of the third electrode 51 overlaps with the orthographic projection of the fourth electrode 52, and the first gate electrode 11 of the first transistor is connected to the third electrode 51 of the second transistor; the first gate electrode 11 is all or a part of the third electrode 51.

In an exemplary embodiment, the first gate electrode 11 and the third electrode 51 may be integrally formed, i.e., the first gate electrode 11 and the third electrode 51 are simultaneously formed through the same manufacturing process using the same material. The embodiment of the present disclosure is not limited thereto and the first gate electrode 11 and the third electrode 51 may be non-integrally structured.

The first gate electrode 11 and the third electrode 51 are exemplified as one electrode extending in the same direction, and the electrode serves as both the first gate electrode 11 and the third electrode 51. For example, the first gate 11 extends in a direction parallel to the substrate 1 and ends to a second source contact region 91 of the second semiconductor layer, connected to said second source contact region 91.

In an exemplary embodiment, in a plane perpendicular to the substrate 1, the front projection of the first electrode 33 may overlap with the front projection of the first gate electrode 11.

In an exemplary embodiment, the second drain contact region 92 of the second semiconductor layer 9 is opposite to and spaced apart from the second source contact region 91 of the second semiconductor layer 9 on the sidewall of the second semiconductor layer 9.

In an exemplary embodiment, the first transistor may further include a first gate insulating layer 7 surrounding the first gate electrode 11, and the first semiconductor layer 6 surrounds the first gate insulating layer 7. The first electrode 33 is connected to the first semiconductor layer 6. The first semiconductor layer 6 forms a receiving cavity, the first gate electrode 11 is disposed in the receiving cavity, and the first gate insulating layer 7 isolates the first semiconductor layer 6 from the first gate electrode 11.

The accommodating cavity formed by the first semiconductor layer 6 may be a cavity having only one opening, or may be a cavity having two openings, the cavity having a circular cross section.

In an exemplary embodiment, the second electrode 34 surrounds and connects the first semiconductor layer, the cross section of the second electrode 34 has an annular opening in a plane perpendicular to the substrate 1, and the first semiconductor layer 6 is located within the opening of the second electrode 34.

In an exemplary embodiment, the first electrode 33 is disposed on a side of the second electrode 34 remote from the second gate electrode 12; and a side of the first gate 11 away from the second gate 12.

In an exemplary embodiment, the first semiconductor layer 6 may include a sidewall and two ends, the first semiconductor layer 6 may include a first source contact region 601 (refer to fig. 33B) and a first drain contact region 602 (refer to fig. 33B), the first drain contact region 602 is located at the sidewall of the first semiconductor layer 6 and surrounds the first semiconductor layer 6, and the first source contact region 601 may be located at the sidewall of the first semiconductor layer 6 and surrounds the first semiconductor layer 6, or may be located at an end of the two ends away from the second gate 12.

In an exemplary embodiment, the read bit line 330 may be connected to the first source contact region 601 of the first semiconductor layer 6, and the write bit line 520 may be connected to the second drain contact region 92 of the second semiconductor layer 9; the read word lines 340 are respectively connected to the first drain contact regions 602 of the first semiconductor layer 6 of the memory cells of different layers.

In an exemplary embodiment, the read word line 340 surrounds the sidewalls of each first semiconductor layer 6 of the memory cells of different layers and is connected with the first drain contact region 602 of the sidewalls of each first semiconductor layer 6.

In an exemplary embodiment, the first semiconductor layer 6 includes a sidewall, a first end connected to the second source contact region 91 of the second semiconductor layer 9, and a second end connected to the read bit line 330.

In an exemplary embodiment, the first electrode 33, the second electrode 34, the third electrode 51 are located on a first side of the second gate 12, the fourth electrode 52 is located on a second side of the second gate 12, and the first side and the second side are opposite sides in a cross section perpendicular to the substrate 1.

In an exemplary embodiment, the first electrode 33 may extend in the third direction Y.

In an exemplary embodiment, the length of the second electrode 34 along the third direction Y may be smaller than the length of the first electrode 33 along the third direction Y, so that the second electrodes 34 of different memory cells may be disconnected.

In an exemplary embodiment, the second electrode 34 may extend in the first direction Z.

In an exemplary embodiment, there may be overlap between the front projection of the first electrode 33 and the front projection of the first gate 11 in a plane perpendicular to the substrate 1.

In an exemplary implementation, the orthographic projection of the first electrode 33 and the orthographic projection of the second electrode 34 may not overlap on a plane parallel to the substrate 1; the orthographic projection of the third electrode 51 and the orthographic projection of the fourth electrode 52 may not overlap.

In an exemplary embodiment, a first distance from the substrate 1 on a surface of the third electrode 51 on a side close to the substrate 1 and a second distance from the substrate 1 on a surface of the fourth electrode 52 on a side close to the substrate 1 may be the same in a direction perpendicular to the substrate 1. The embodiments of the present disclosure are not limited thereto and the first distance and the second distance may be different.

In an exemplary embodiment, the surface of the third electrode 51 on the side away from the substrate 1 may be spaced from the substrate 1 by a distance equal to the distance of the surface of the fourth electrode 52 on the side away from the substrate 1. However, the embodiment of the present disclosure is not limited thereto, and the surface of the third electrode 51 on the side away from the substrate 1 may not be equal to the surface of the fourth electrode 52 on the side away from the substrate 1.

In an exemplary embodiment, the first thickness of the third electrode 51 and the second thickness of the fourth electrode 52 may be the same in a direction perpendicular to the substrate 1. Embodiments of the present disclosure are not limited thereto and the first thickness and the second thickness may be different.

In an exemplary embodiment, the first electrode 33, the third electrode 51, and the fourth electrode 52 may be located on the same conductive film layer in a direction perpendicular to the substrate 1. It is understood that the first electrode 33, the third electrode 51 and the fourth electrode 52 are located on the same metal film layer. In the laminated structure in which insulating layers and metal film layers are alternately laminated, the first electrode 33, the third electrode 51, and the fourth electrode 52 are located between two insulating layers.

In an exemplary embodiment, the orthographic projection of the second gate electrode 12 is located outside the orthographic projection of the third electrode 51 in a plane parallel to the substrate 1, and the orthographic projection of the second gate electrode 12 may be located outside the orthographic projection of the fourth electrode 52.

In an exemplary embodiment, the first direction Z may be perpendicular to the substrate 1. The embodiments of the present disclosure are not limited thereto and the first direction Z may be at other angles with the substrate 1.

In an exemplary embodiment, as shown in fig. 2, in a cross section perpendicular to the substrate 1, the third electrode 51 is located on a first side of the second gate electrode 12, the fourth electrode 52 is located on a second side of the second gate electrode 12, and the first side and the second side are opposite sides, i.e., the third electrode 51 and the fourth electrode 12 are disposed opposite to each other. The embodiments of the present disclosure are not limited thereto and the third electrode 51 and the fourth electrode 52 may be other positions.

In an exemplary embodiment, the third electrode 51 may extend in a second direction X, the fourth electrode 52 may extend in a third direction Y, the second direction X may be parallel to the substrate 1, the third direction Y may be parallel to the substrate 1, and the second direction X and the third direction Y may intersect. The embodiments of the present disclosure are not limited thereto and the third electrode 51 and the fourth electrode 52 may be other shapes.

In an exemplary embodiment, the second direction X and the third direction Y may be perpendicular, but the embodiments of the present disclosure are not limited thereto, and other angles may be between the second direction X and the third direction Y.

In an exemplary embodiment, the cross section of the first electrode 33 may be square in a direction perpendicular to the substrate 1, and the embodiment of the present disclosure is not limited thereto, and the cross section of the first electrode 33 may be other shapes, such as a circle, a hexagon, and the like.

In an exemplary embodiment, the cross sections of the third electrode 51 and the fourth electrode 52 may be square in a direction perpendicular to the substrate 1, and the embodiment of the present disclosure is not limited thereto, and the cross sections of the third electrode 51 and the fourth electrode 52 may be other shapes, such as a circle, a hexagon, and the like.

In an exemplary embodiment, the third electrode 51 and the fourth electrode 52 may be connected at other positions than the position shown in fig. 1, for example, the third electrode 51 is connected to a first side of a circular cylinder formed of a semiconductor layer, the fourth electrode 52 is connected to a second side of a circular cylinder formed of a semiconductor layer, and the first side and the second side are adjacent, and so on.

In an exemplary embodiment, the third electrode 51 and the fourth electrode 52 may be simultaneously formed through one manufacturing process, but the embodiment of the present disclosure is not limited thereto and may be separately manufactured through different processes.

In an exemplary embodiment, a surface of the first electrode 33 on a side close to the substrate 1 may be spaced apart from the substrate 1 by a distance smaller than a surface of the third electrode 51 on a side close to the substrate 1 is spaced apart from the substrate 1, and a surface of the first electrode 33 on a side far from the substrate 1 may be spaced apart from the substrate 1 by a distance greater than a surface of the third electrode 51 on a side far from the substrate 1 is spaced apart from the substrate 1. The thickness of the first electrode 33 may be greater than the thickness of the third electrode 51 in a direction perpendicular to the substrate 1.

In an exemplary embodiment, the surface of the second electrode 34 on the side away from the substrate 1 may be spaced apart from the substrate 1 by a distance consistent with the distance between the surface of the second gate 12 on the side away from the substrate 1 and the substrate 1.

In an exemplary embodiment, the length of the second semiconductor layer 9 may be equal to the length of the second gate electrode 12 in a direction perpendicular to the substrate 1. However, the embodiments of the present disclosure are not limited thereto, and in an exemplary embodiment, the length of the second semiconductor layer 9 may be equal to or less than the length of the second gate electrode 12 and equal to or less than the length of the second gate insulating layer 10, and the length of the second semiconductor layer 9 may be equal to or greater than the length of the third electrode 51, and the length of the second semiconductor layer 9 may be equal to or greater than the length of the fourth electrode 52, in a direction perpendicular to the substrate 1. The scheme provided by the embodiment can shorten the channel length and reduce the electric leakage.

In an exemplary embodiment, the length of the second semiconductor layer 9 may be equal to the length of the second gate insulating layer 10 in a direction perpendicular to the substrate 1, and the length of the second gate insulating layer 10 may be equal to the length of the second gate electrode 12.

In an exemplary embodiment, the length of the second gate insulating layer 10 may be smaller than the length of the second gate electrode 12 in a direction perpendicular to the substrate 1, and the length of the second gate insulating layer 10 may be equal to or greater than the length of the semiconductor layer 9.

In an exemplary embodiment, the materials of the first semiconductor layer 6 and the second semiconductor layer 9 may include a metal oxide semiconductor material.

In an exemplary embodiment, the metal in the metal oxide semiconductor material may include, but is not limited to: at least one of indium, tin, zinc, aluminum, gallium.

In an exemplary embodiment, the metal oxide semiconductor material may include, but is not limited to: at least one of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide.

As shown in fig. 2, the present embodiment provides a solution in which the dimensions of the channel between the third electrode 51 and the fourth electrode 52 can be controlled by the overlap length between the orthographic projection of the third electrode 51 and the orthographic projection of the fourth electrode 52 in a plane perpendicular to the substrate 1. The overlapping length between the orthographic projection of the third electrode 51 and the orthographic projection of the fourth electrode 52 is d, the channel size can be controlled by controlling the thickness of the third electrode 51 and the fourth electrode 52 along the direction perpendicular to the substrate 1, compared with a transistor with a source surrounding a gate and a drain surrounding a gate, the channel size can be controlled by changing the size of a through hole where the gate is located (a mask plate needs to be changed) or increasing the distance between the source and the drain (which can result in the increase of the volume of the transistor), the embodiment can more conveniently control the size of the channel, has small process modification and has less influence on the size of the transistor.

In an exemplary embodiment, adjacent memory cells in a direction perpendicular to the substrate 1 are respectively located in different memory arrays, i.e. adjacent memory cells of different memory arrays may share the second electrode 34.

In an exemplary embodiment, in the same memory array, the first electrode 33 of the memory cell of the first column is connected to the same read bit line 330 or the fourth electrode 52 is connected to the same write bit line 520, the first electrode 33 of the memory cell of the last column is connected to the same read bit line 330 or the fourth electrode 52 is connected to the same write bit line 520, the memory cells of other columns except for the first column and the last column are connected to the same read bit line 330, and the first electrode 33 of one of the memory cells of the two adjacent columns is connected to the same write bit line 520 as the fourth electrode 52 of the other memory cell of the two adjacent columns. As shown in fig. 1, when 4 memory cell columns are included, from the leftmost side to the rightmost side in fig. 1, the first memory cell column at the outermost side and the fourth electrode 52 of the adjacent memory cell column are connected to the same write bit line 520, the second memory cell column at the non-outermost side and the fourth electrode 52 of the first memory cell column are connected to the same write bit line 520, and the first electrode 33 of the third memory cell column is connected to the same read bit line 330; the first electrodes 33 of the third and second memory cell columns are connected to the same read bit line 330, and the fourth electrodes 52 of the third and fourth memory cell columns are connected to the same write bit line 520; the fourth electrode 52 of the outermost fourth memory cell column and the third memory cell column are connected to the same write bit line 520.

In an exemplary embodiment, as shown in fig. 2, the second semiconductor layers 9 of memory cells adjacent in a direction perpendicular to the substrate 1 are connected to each other. For example, the second semiconductor layers 9 of the second transistors of adjacent memory cells of different layers are connected as a unitary structure.

Fig. 3 is a schematic cross-sectional view of a 3D memory array along a direction perpendicular to a substrate 1 according to another exemplary embodiment. As shown in fig. 3, in the present embodiment, the second semiconductor layers 9 of the second transistors of the adjacent memory cells of different layers are arranged at intervals in a direction perpendicular to the substrate 1. That is, the second semiconductor layers 9 of memory cells adjacent in a direction perpendicular to the substrate 1 are disconnected from each other. The scheme provided by the embodiment can reduce the electric leakage among different transistors when the second semiconductor layers 9 are disconnected among different memory arrays compared with the scheme that the second semiconductor layers 9 are connected with each other.

In the above embodiments, the memory arrays each include a plurality of memory cells, but the embodiments of the present disclosure are not limited thereto, and the memory arrays may include one memory cell.

In an exemplary embodiment, the first transistor may be a read transistor, the second transistor may be a write transistor, the first electrode 33 may be connected to a read bit line, the second electrode 34 may be connected to a read word line, the second gate 12 may be connected to a write word line, and the fourth electrode 52 may be connected to a write bit line. A voltage is applied to the write word line, the channel is turned on, and communication is made between the third electrode 51 and the fourth electrode 52. The read-write process is as follows: 1) When writing "1", the write bit line applies a read voltage (i.e., applies a read voltage to the fourth electrode 52), charges are injected into the storage node (the storage node between the first gate 11 and the third electrode 51), and the first transistor is turned on; when reading "1", a read voltage is applied to the read word line in the read tube (i.e. a read voltage is applied to the second electrode 34), and since a certain charge exists in the storage node, a current passes between the first electrode 33 and the second electrode 34, and then the peripheral circuit amplifies and recognizes the current, and then the process of reading "1" is completed. (2) When writing a "0", the write bit line draws charge to a voltage below the threshold voltage (i.e., a voltage below the threshold voltage is applied to the fourth electrode 52), and the first transistor is non-conductive; when reading "0", the read word line in the read tube applies a read voltage (i.e. the second electrode 34 applies a read voltage), and no or less current passes between the first electrode 33 and the second electrode 34 due to no charge in the storage node, and the peripheral circuit performs amplification recognition to complete the process of reading "0".

The technical scheme of this embodiment is further described below through the preparation process of the 3D memory array of this embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, photoresist stripping, etc., and is a well-known preparation process in the related art. The "photolithography process" in this embodiment includes coating a film layer, mask exposure and development, and is a well-known preparation process in the related art. The deposition may be performed by known processes such as sputtering, vapor deposition, chemical vapor deposition, etc., the coating may be performed by known coating processes, and the etching may be performed by known methods, which are not particularly limited herein. In the description of the present embodiment, it is to be understood that "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process or a photolithography process throughout the fabrication process. If the "film" is also subjected to a patterning process or a photolithography process during the entire fabrication process, it is referred to as a "film" before the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

Taking a 3D memory array comprising two stacked memory arrays, each comprising 4 memory cells, as an example, embodiments of the present disclosure are not limited thereto, and a 3D memory array may comprise more memory arrays and a memory array may comprise more memory cells.

In an exemplary embodiment, as shown in fig. 4 to 16, the preparation process of the 3D memory array may include:

101 Alternately depositing a first insulating film and a first metal film in order on the substrate 1 to form a stacked structure including a plurality of first insulating layers 100 and a plurality of first metal layers 200 alternately arranged, and the topmost layer is the first insulating layer 100, as shown in fig. 4;

in an exemplary embodiment, the substrate 1 may be prepared using glass, silicon, a flexible material, or the like. The flexible material can be Polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film. In an exemplary embodiment, the substrate 1 may be a single layer structure or a multi-layered stacked structure, and the substrate of the stacked structure may include: flexible material/inorganic material/flexible material, the inorganic material may be, for example, any one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). The substrate 1 may be a semiconductor substrate; such as at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

In an exemplary embodiment, the first insulating film may be a low-K dielectric layer, i.e., a dielectric layer having a dielectric constant K < 3.9. For example, any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC) may be used.

In an exemplary embodiment, the first metal thin film may include, but is not limited to, at least one of: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).

102 Patterning the stacked structure through a patterning process to form a plurality of first slots P1 and a plurality of first openings K1 penetrating the stacked structure, and a planar pattern of the first metal layer 200 after patterning is shown in fig. 5.

In an exemplary embodiment, the first metal layer 200 may include a plurality of metal units having H-shaped cross sections (as divided by dotted lines in fig. 5) on a plane parallel to the substrate 1. The single metal unit may include a second sub-portion 32 and a first electrode 33 opposite to each other, and a first sub-portion 31 connecting the second sub-portion 32 and the first electrode 33. The sizes and shapes of the first sub-portions 31 of the different metal units may be the same or different, the sizes and shapes of the second sub-portions 32 of the different metal units may be the same or different, and the sizes and shapes of the first electrodes 33 of the different metal units may be the same or different. The plurality of first electrodes 33 form the read bit lines 330, i.e., the first metal layer 200 includes the plurality of read bit lines 330, the plurality of first sub-portions 31, and the plurality of second sub-portions 32.

In an exemplary embodiment, the size and shape of the plurality of first grooves P1 may be the same, but the embodiment of the present disclosure is not limited thereto, and the size and shape of the plurality of first grooves P1 may be different.

In an exemplary embodiment, the size and shape of the plurality of first openings K1 may be the same or different.

In an exemplary embodiment, the first sub-portion 31 may extend in the second direction X, the second sub-portion 32, and the first electrode 33 may extend in the third direction Y, and the second direction X and the third direction Y may intersect. In an exemplary embodiment, the second direction X and the third direction Y may be perpendicular.

In the present embodiment, the pattern of the first metal layer 200 is only an example, and may have other shapes.

According to the scheme provided by the embodiment, multiple layers can be etched at one time, so that the process is simplified, and the cost is reduced.

103 On the substrate 1 formed with the foregoing pattern, a second insulating film is deposited, forming a second insulating layer 5, the second insulating layer 5 filling the plurality of first grooves P1 and the plurality of first openings K1, as shown in fig. 6.

In an exemplary embodiment, the second insulating film may be a low-K dielectric layer, i.e., a dielectric layer having a dielectric constant K <3.9, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). The second insulating film and the first insulating film may be the same material or different materials. The subsequent third insulating film is similar and will not be described again.

104 On the substrate 1 formed with the foregoing pattern, a plurality of through holes 41 penetrating the stacked structure are formed, and on a plane parallel to the substrate 1, the orthographic projection of the through holes 41 may overlap with the orthographic projection of the first sub-portion 31 and may overlap with the orthographic projection of the second sub-portion 32, and the side walls of the through holes 41 expose the first and second sub-portions 31 and 32, as shown in fig. 7. The cross section of the through hole 41 in a plane parallel to the substrate 1 shown in fig. 7 is quadrangular, but the embodiment of the present disclosure is not limited thereto, and the through hole 41 may be other shapes such as a circle, a pentagon, a hexagon, and the like. The through holes 41 may be in one-to-one correspondence with the metal units.

105 The first sub-portion 31, the second sub-portion 32, and the junction of the first electrode 33 and the first sub-portion 31 are selectively etched, at this time, a first channel 42 formed by the region where the selectively etched first sub-portion 31 is located, a second channel 43 formed by the region where the second sub-portion 32 is located, and the through hole 41 are formed, the first channel 42 is communicated with the through hole 41, and the second channel 43 is communicated with the through hole 41. The first electrode 33 is provided with a second slit P2 facing the first sub-portion 31 (the first sub-portion 31 has been etched away), as shown in fig. 8A, 8B. Fig. 8A is a schematic perspective view of a 3D memory array. Fig. 8B is a cross-sectional view of the first metal layer 200 along a direction parallel to the substrate 1.

106 A first semiconductor film and a first gate oxide film are sequentially deposited on the sidewalls of the channels (i.e., the via 41, the first channel 42, and the second channel 43) formed in step 105 to form the first semiconductor layer 6 and the first gate insulating layer 7, as shown in fig. 9A, 9B, and 9C. The first semiconductor layer 6 and the first gate insulating layer 7 then act as channel walls for the channels, the first semiconductor layer 6 surrounding the first gate insulating layer 7. Fig. 9A is a perspective view of the first semiconductor layer 6 and the first gate insulating layer 7 after being formed; FIG. 9B is a partial schematic view of FIG. 9A; fig. 9C is a sectional view of fig. 9B along BB direction.

In an exemplary embodiment, the first gate oxide film may be a High-K dielectric material. The High-K dielectric material may include, but is not limited to, at least one of: silicon oxide, aluminum oxide, hafnium oxide.

In an exemplary embodiment, the first semiconductor thin film includes, but is not limited to, at least one of: IGZO, indium Tin Oxide (ITO), indium zinc Oxide (Indium Zinc Oxide, IZO). When IGZO is used as the semiconductor layer, there is an advantage of low leakage current and short refresh time. The other semiconductor films are similar and will not be described in detail.

In an exemplary embodiment, the first semiconductor thin film and the first gate oxide thin film may be deposited by an atomic layer deposition (Atomic Layer Deposition, ALD) method.

107 A second metal film is deposited in the channels (i.e., the through-holes 41, the first channels 42, and the second channels 43) to form the second metal layer 8, and the second metal layer 8 completely fills the channels, as shown in fig. 10A, 10B, and 10C. Fig. 10C is a sectional view along the BB direction of fig. 10B, and shows only the first semiconductor layer 6, the first gate insulating layer 7, and the second metal layer 8. At this time, the first gate insulating layer 7 surrounds the second metal layer 8.

In an exemplary embodiment, the second metal thin film may include, but is not limited to, at least one of: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta). The second metal film may be the same as or different from the first metal film.

108 The second metal layer 8, the first gate insulating layer 7 in the via 41, the second metal layer 8 (the second metal layer 8 in the first via 42 and the second via 43 parallel to the substrate 1) and the first gate insulating layer 7 at other positions in the remaining via, as shown in fig. 11A, 11B and 11C, fig. 11C is a sectional view of fig. 11B in the BB direction, and only the first semiconductor layer 6, the first gate insulating layer 7 and the second metal layer 8 are shown. The second metal layer 8 located in the first channel 42 serves as a third electrode 51 of the second transistor, the second metal layer 8 located in the second channel 43 serves as a fourth electrode 52 of the plurality of second transistors, and the third electrode 51 and the fourth electrode 52 are disconnected from each other. The second metal layer 8 of the second channel 43 is the write bit line 520.

109 A second semiconductor film, a second gate oxide film and a third metal film are sequentially deposited on the sidewall of the through hole etched in the step 108), so as to form a second semiconductor layer 9, a second gate insulating layer 10 and a second gate 12 of the memory cells of the plurality of memory arrays, wherein the second gate insulating layer 10 surrounds the second gate 12, the second semiconductor layer 9 surrounds the second gate insulating layer 10, and the second gate 12 completely fills the region surrounded by the second gate insulating layer 10. As shown in fig. 12A, 12B, and 12C, fig. 12C is a cross-sectional view along the BB direction of fig. 12B, and only the first semiconductor layer 6, the first gate insulating layer 7, the second semiconductor layer 9, the second gate insulating layer 10, the second metal layer 8 (the third electrode 51, the fourth electrode 52), and the second gate electrode 12 are shown. The plurality of second gates 12 form the write word line 120.

In an exemplary embodiment, the second gate oxide film may be a High-K dielectric material. The High-K dielectric material may include, but is not limited to, at least one of: silicon oxide, aluminum oxide, hafnium oxide. The materials of the second gate oxide film and the first gate oxide film may be the same or different.

In an exemplary embodiment, the second semiconductor thin film may use the same material as the first semiconductor thin film.

In an exemplary embodiment, the third metal thin film may include, but is not limited to, at least one of: tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta). The third metal film may be the same as or different from the first metal film and the second metal film. The fourth metal film is similar and will not be described again.

110 On the substrate 1 formed with the above-described pattern, the socket structure 44 as shown in fig. 13 is etched, but the first semiconductor layer 6 and the region surrounded by the first semiconductor layer 6 are not etched, the socket structure 44 penetrating through the respective film layers on the substrate 1. On a plane perpendicular to the substrate 1, the orthographic projection of the socket structure 44 is located outside the orthographic projection of the first electrode 33, outside the orthographic projection of the through hole 41, and outside the orthographic projection of the fourth electrode 52.

111 A fourth metal film is deposited within the socket structure 44 to form a fourth metal layer 300 filling the socket structure 44, as shown in fig. 14.

112 On the substrate 1 on which the above pattern is formed, a plurality of third grooves P3 and a plurality of second openings K2 penetrating the fourth metal layer 300 are formed, and after the third grooves P3 and the second openings K2 are formed, the fourth metal layer 300 is divided into 4 read word lines 340 as the second electrodes 34 of the first transistors of the plurality of memory cells (memory cells adjacent in a direction perpendicular to the substrate 1) as shown in fig. 15A. The length of the read word line 340 in the third direction Y is smaller than the length of the first electrode 33 in the third direction Y, and the read word line 340 surrounds the first semiconductor layer 6 as shown in fig. 15B.

113 On the substrate 1 on which the above pattern is formed, a fourth insulating film is deposited, and a fourth insulating layer 55 is formed, the fourth insulating layer 55 filling the third grooves P3 and the second openings K2, as shown in fig. 16.

In the 3D memory array manufactured using the above manufacturing process, the first gate insulating layer 7 surrounding the fourth electrode 52 and the first semiconductor layer 6 surrounding the first gate insulating layer 7 may be present in the second channel 43. However, the embodiment of the present disclosure is not limited thereto, and when the memory array includes only one memory cell, the first gate insulating layer 7 surrounding the fourth electrode 52 and the first semiconductor layer 6 surrounding the first gate insulating layer 7 may not be present in the second channel 43 (except for the region intersecting the via hole 41), i.e., the first gate insulating layer 7 and the first semiconductor layer 6 in the second channel 43 may be removed. The first gate insulating layer 7 and the first semiconductor layer 6 in the second channel 43 may be reserved for process convenience.

The above-described preparation process is merely an example, and the embodiments of the present disclosure are not limited thereto and may be prepared in other ways. For example, the first insulating film may be deposited after the first metal film is deposited and patterned by a patterning process to form the first metal layer pattern each time, without forming a plurality of first grooves P1 and a plurality of first openings K1 by grooves.

In another exemplary embodiment, as shown in fig. 17 to 24, the preparation process of the 3D memory array may include:

201 To 207), similar to steps 101 to 107, and will not be described again, forming the structure shown in fig. 10A, 10B and 10C;

208 The second metal layer 8, the first gate insulating layer 7, and the first semiconductor layer 6 in the positions where the through holes 41 are located are etched and etched, the second metal layer 8 (the second metal layer 8 in the first and

second channels

42 and 43 parallel to the substrate 1), the first gate insulating layer 7, and the first semiconductor layer 6 in other positions in the channels are left, as shown in fig. 17A, 17B, fig. 17A is a cross-sectional view in the BB direction, and only the first semiconductor layer 6, the first gate insulating layer 7, and the second metal layer 8 are shown. The second metal layer 8 located in the first channel 42 serves as a third electrode 51 of the second transistor, the second metal layer 8 located in the second channel 43 serves as a fourth electrode 52 of the plurality of second transistors, and the third electrode 51 and the fourth electrode 52 are disconnected from each other. The second metal layer 8 of the second channel 43 is the write bit line 520.

209 A third gate oxide film and a third semiconductor film are sequentially deposited on the sidewall of the via hole etched in step 208) above, to form a third gate insulating layer 61 and a third semiconductor layer 62, respectively. In which the third gate oxide film is selectively deposited, as shown in fig. 18A and 18B, fig. 18B is a cross-sectional view along the BB direction of fig. 18A, and only the first semiconductor layer 6, the first gate insulating layer 7, the third semiconductor layer 62, the third gate insulating layer 61, and the second metal layer 8 (the third electrode 51, the fourth electrode 52) are shown, deposited in the sidewall of the via hole 41 in the region where the second metal layer 8 is not present.

In an exemplary embodiment, the third gate oxide film may be selected from a High-K dielectric material that is not easily deposited on the metal. The High-K dielectric material may include, but is not limited to, at least one of: silicon oxide, aluminum oxide, hafnium oxide.

In an exemplary embodiment, the third semiconductor film may use the same material as the first and second semiconductor films.

210 The third semiconductor layer 62 attached on the third gate insulating layer 61 in the position where the via hole 41 is located is etched and etched, leaving the third semiconductor layer 62 attached on the other position (including the third electrode 51, the fourth electrode 52), as shown in fig. 19A, 19B, and 19C, fig. 19C is a sectional view of fig. 19B in the BB direction. It can be seen that the third gate insulating layers 61 and the third semiconductor layers 62 are alternately arranged in the through-hole 41 along the extending direction of the through-hole 41 at this time. The third semiconductor layers 62 of different memory arrays are disconnected from each other.

211 A second gate oxide film and a third metal film are sequentially deposited on the sidewalls of the via holes 41 to form the second gate insulating layer 10 and the second gate electrode 12, as shown in fig. 20A and 20B. The plurality of second gates 12 form the write word line 120.

212 On the substrate 1 formed with the above-described pattern, a socket structure 44 as shown in fig. 21 is etched, the socket structure 44 penetrating through each film layer on the substrate 1, but not etching the first semiconductor layer 6 and the region surrounded by the first semiconductor layer 6. On a plane perpendicular to the substrate 1, the orthographic projection of the socket structure 44 is located outside the orthographic projection of the first electrode 33, outside the orthographic projection of the through hole 41, and outside the orthographic projection of the fourth electrode 52.

213 A fourth metal film is deposited within the socket structure 44 to form a fourth metal layer 300 filling the socket structure 44, as shown in fig. 22.

214 On the substrate with the patterns, a plurality of third grooves P3 and a plurality of second openings K2 penetrating the fourth metal layer 300 are formed, and after forming the third grooves P3 and the second openings K2, the fourth metal layer 300 is divided into 4 read word lines 340, each read word line 340 serving as the second electrode of the first transistor of two memory cells, as shown in fig. 23A. The length of the read word line 340 in the third direction Y is smaller than the length of the first electrode 33 in the third direction Y, and the read word line 340 surrounds the first semiconductor layer 6 as shown in fig. 23B.

215 On the substrate 1 on which the above pattern is formed, a fourth insulating film is deposited, and a fourth insulating layer 55 is formed, the fourth insulating layer 55 filling the third grooves P3 and the second openings K2, as shown in fig. 24.

In another exemplary embodiment, as shown in fig. 25 to 33B, the preparation process of the 3D memory array may include:

301 To 303), similar to steps 101 to 103, and will not be described again, to form the structure shown in fig. 6;

304 On the substrate 1 formed with the foregoing pattern, a plurality of through holes 41 penetrating the stacked structure are formed, and on a plane parallel to the substrate 1, the orthographic projection of the through holes 41 may overlap with the orthographic projection of the first sub-portion 31, overlap with the orthographic projection of the second sub-portion 32, the side walls of the through holes 41 expose the first sub-portion 31 and the second sub-portion 32, and the width of the through holes 41 is smaller than the width of the first sub-portion 31 in the extending direction perpendicular to the first sub-portion 31, as shown in fig. 25.

305 307), similar to steps 105 to 107, the structure shown in fig. 26 is formed, and the right part in fig. 26 shows only a partial structure. In this embodiment, the width of the through hole 41 is smaller than the width of the first sub-portion 31 along the extending direction perpendicular to the first sub-portion 31.

308 The second metal layer 8 and the first gate insulating layer 7 in the position where the via 41 is located are etched and the etching is continued in the direction away from the via 41 in the first via 42 and the second via 42 such that the orthographic projection of the semiconductor thin film located at the via 41 (i.e., the first semiconductor layer 6 located at the via 41) falls within the orthographic projection of the via 41 located at the first metal layer 200 on the plane parallel to the substrate 1, the via 41 located at the first metal layer 200 is the via K10 in fig. 27B, as shown in fig. 27A, 27B, fig. 27B is a cross-sectional view of fig. 27A in the BB direction, and only the first semiconductor layer 6, the first gate insulating layer 7, and the second metal layer 8 are shown. The second metal layer 8 located in the first channel 42 serves as a third electrode 51 of the second transistor, the second metal layer 8 located in the second channel 43 serves as a fourth electrode 52 of the second transistor, and the third electrode 51 and the fourth electrode 52 are disconnected from each other.

309 A fourth semiconductor film is deposited on the sidewall of the through hole etched in step 308) to form the fourth semiconductor layer 64. As shown in fig. 28A, 28B, fig. 28B is a cross-sectional view along the BB direction of fig. 28A, and only the first semiconductor layer 6, the first gate insulating layer 7, the second semiconductor layer 9, the second metal layer 8 (the third electrode 51, the fourth electrode 52), and the fourth semiconductor layer 64 are shown.

In an exemplary embodiment, the fourth semiconductor film may use the same material as the first, second, and third semiconductor films.

310 The first semiconductor layer 6 and the fourth semiconductor layer 64 in the through-hole 41 are subjected to photolithography and etching, leaving the fourth semiconductor layer 64 attached at other positions (including the third electrode 51, the fourth electrode 52), as shown in fig. 29A, 29B, fig. 29B being a sectional view of fig. 29A in the BB direction. It can be seen that after this step is performed, the fourth semiconductor layer 64 is divided into a plurality of segments in a direction perpendicular to the substrate 1, and the segments serve as the second semiconductor layers 9 of the second transistors of the memory arrays of the different layers, respectively, so that the second semiconductor layers 9 of the different memory arrays can be isolated, and leakage current can be reduced.

311 A second gate oxide film and a third metal film are sequentially deposited on the sidewalls of the via holes 41 to form the second gate insulating layer 10 and the second gate electrode 12, as shown in fig. 30A and 30B.

312 On the substrate 1 formed with the above-described pattern, a socket structure 44 as shown in fig. 31 is etched, the socket structure 44 penetrating through each film layer on the substrate 1, but not etching the first semiconductor layer 6 and the region surrounded by the first semiconductor layer 6. On a plane perpendicular to the substrate 1, the orthographic projection of the socket structure 44 is located outside the orthographic projection of the first electrode 33, outside the orthographic projection of the through hole 41, and outside the orthographic projection of the fourth electrode 52.

313 A fourth metal film is deposited within the socket structure 44 to form a fourth metal layer 300 filling the socket structure 44, as shown in fig. 32.

314 315), similar to steps 214) to 215), forming a plurality of third trenches P3 and a plurality of second openings K2 penetrating the fourth metal layer 300 on the substrate 1 patterned as described above, dividing the fourth metal layer 300 into 4 read word lines 340, each read word line 340 serving as a second electrode of the first transistors of the plurality of memory cells, respectively. The length of the read word line 340 along the third direction Y is smaller than the length of the first electrode 33 along the third direction Y, and the read word line 340 surrounds the first semiconductor layer 6;

a fourth insulating film is deposited to form a fourth insulating layer 55, the fourth insulating layer 55 fills the third grooves P3 and the second openings K2, as shown in fig. 33A and 33B, fig. 33B is a cross-sectional view of fig. 33A along the BB direction, and a part of the film layer is omitted in fig. 33B.

In another exemplary embodiment, as shown in fig. 34A to 38, the preparation process of the 3D memory array may include:

401 To 407), similar to steps 301 to 307, and will not be described again, to form the structure shown in fig. 26;

in this embodiment, the size of the cross section of the through hole 41 along the direction parallel to the substrate 1 may be smaller than that of the cross section of the through hole 41 in the previous embodiment, for example, the orthographic projection of the through hole 41 on the substrate 1 in this embodiment may fall within the orthographic projection of the through hole 41 on the substrate 1 in the previous embodiment.

408 Lithography and etching of the second metal layer 8 in the via 41, and the second metal layer 8 in the first and

second channels

42 and 42 continues etching away from the via 41, such that on a plane parallel to the substrate 1, the orthographic projection of the semiconductor thin film located at the via 41 (i.e., the first semiconductor layer 6 located at the via 41) falls within the orthographic projection of the via 41 located at the first metal layer 200, the via 41 located at the first metal layer 200 being the via K11 in fig. 34B, as shown in fig. 34A, 34B, fig. 34B being a cross-sectional view of fig. 34A in the BB direction, and showing only the first semiconductor layer 6, the first gate insulating layer 7, and the second metal layer 8. The second metal layer 8 located in the first channel 42 serves as a third electrode 51 of the second transistor, the second metal layer 8 located in the second channel 43 serves as a fourth electrode 52 of the plurality of second transistors, and the third electrode 51 and the fourth electrode 52 are disconnected from each other. The second metal layer 8 of the second channel 43 is the write bit line 520.

409 A fifth semiconductor film is deposited on the sidewall of the through-hole etched in step 408) above, to form a fifth semiconductor layer 65, as shown in fig. 35.

In an exemplary embodiment, the fifth semiconductor film may use the same material as the first, second, third, and fourth semiconductor films.

410 The first semiconductor layer 6, the first gate insulating layer 7, the fifth semiconductor layer 65 in the via 41 are subjected to photolithography and etching, leaving the fifth semiconductor layer 65 attached to other positions including the third electrode 51, the fourth electrode 52, as shown in fig. 36. At this time, the fifth semiconductor layer 65 serves as a second semiconductor layer of the second transistor.

411 A second gate oxide film and a third metal film are sequentially deposited on the sidewalls of the via holes 41 to form the second gate insulating layer 10 and the second gate electrode 12, as shown in fig. 37.

412 To 415), steps 312 to 315 are similar, namely, etching the socket structure 44 on the substrate 1 formed with the aforementioned pattern, depositing a fourth metal film inside the socket structure 44, forming a fourth metal layer 300 filling the socket structure 44; a plurality of third trenches P3 and a plurality of second openings K2 are formed through the fourth metal layer 300, dividing the fourth metal layer 300 into 4 read word lines 340, each read word line 340 serving as a second electrode of the first transistors of the plurality of memory cells.

A fourth insulating film is deposited to form a fourth insulating layer 55, and the fourth insulating layer 55 fills the third grooves P3 and the second openings K2, as shown in fig. 38.

FIG. 39 is a schematic diagram of a 3D memory array according to an exemplary embodiment. As shown in fig. 39, this embodiment provides a 3D memory array, including a plurality of memory arrays stacked in any one of the above embodiments, further including: a gating structure, the gating structure comprising: a row word line XWL corresponding to a memory cell row of the memory array farthest from the substrate 1, a column word line YWL corresponding to a memory cell column of the memory array farthest from the substrate 1, and a gate transistor 70 corresponding one-to-one to the memory cells of the memory array farthest from the substrate 1, the gate transistor 70 including a fifth electrode 74, a sixth electrode 75, and a third gate 71, the third gate 71 of the gate transistor corresponding to the memory cell of the same memory cell row being electrically connected to the same row word line XWL, the sixth electrode 75 of the gate transistor corresponding to the memory cell of the same memory cell column being electrically connected to the same column word line YWL, the fifth electrode 74 of the gate transistor being electrically connected to the second gate 12 of the memory cell corresponding to the gate transistor.

According to the scheme provided by the embodiment, through the unique selection of the XWL, the YWL and the gating transistor, the corresponding writing line (the second grid) at the intersection point of the XWL and the YWL is selected, and through effective selection when information is written, the charging of a plurality of writing word lines in an array during writing operation is avoided, and a large amount of unnecessary power consumption is generated, namely, the scheme reduces a large amount of unnecessary power consumption.

In an exemplary embodiment, as shown in fig. 40A and 40B, the gate transistor 70 may further include: a third semiconductor layer 73 provided on a side of the fifth electrode 74 away from the substrate 1, a fourth gate insulating layer 72 provided on a side of the third semiconductor layer 73 away from the substrate 1; the third semiconductor layer 73 extends along the first direction Z, the sixth electrode 75 surrounds the third semiconductor layer 73, the third semiconductor layer 73 is provided with a containing cavity, the third gate 71 is at least partially disposed in the containing cavity, the third gate 71 and the third semiconductor layer 73 are isolated by the fourth gate insulating layer 72, and the orthographic projection of the third semiconductor layer 73 on the substrate 1 is located in the orthographic projection of the fifth electrode 74 on the substrate 1. The gate transistor provided in this embodiment is only an example, and the embodiments of the present disclosure are not limited thereto, and may be other structures of gate transistors. The gating transistor used in the embodiment of the disclosure can be directly prepared on a storage array, and is convenient to realize. The gating transistor provided in this embodiment may be applied to other arrays. Such as a 3D array of 1T1C, etc.

As shown in fig. 39, the row word line XWL may be located at a side of the column word line YWL away from the substrate 1. The column word line YWL may surround the sixth electrode 75.

The embodiment of the disclosure also provides a gating method applied to the 3D memory array, including:

setting all column word lines YWL to off voltage to turn off the write word lines;

all row word lines XWL are turned on (on voltage is applied), and all write word lines are precharged (precharge) to a low potential;

turning off the other row word lines XWL except the selected row word line XWL (i.e., applying a turn-off voltage to the other row word lines XWL);

the selected column word line YWL is set to the on voltage, and the selected write word line is turned on.

In an exemplary embodiment, the off voltage is, for example, low.

In an exemplary embodiment, the turn-on voltage is, for example, a high level.

By the gating method, one write word line can be gated, and unnecessary power consumption is avoided.

The embodiment of the disclosure also provides an electronic device, which comprises the 3D storage array of the embodiment. The electronic device may be: storage, smart phones, computers, tablet computers, artificial intelligence devices, wearable devices or mobile power sources, etc. The 3D memory array may include memory in a computer, etc., and is not limited herein.

As shown in fig. 41, the embodiment of the present disclosure further provides a method for manufacturing a 3D memory array, where the 3D memory array includes a plurality of memory arrays stacked in a direction perpendicular to a substrate, and a plurality of write word lines extending in the direction perpendicular to the substrate; the memory array includes a plurality of memory cells distributed in an array, a plurality of read bit lines and a plurality of write bit lines, the memory cells including: a first transistor and a second transistor disposed on the substrate, the first transistor including a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer, the second transistor including a second gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer, the method of manufacturing may include:

step 411, forming a first gate of a first transistor, a first semiconductor layer, a third electrode of a second transistor, a plurality of read bit lines and a plurality of write bit lines of memory cells of the plurality of memory arrays on a substrate, wherein a first electrode of a memory cell of a same column of a same layer is a part of a same read bit line, and a fourth electrode of a memory cell of a same column of a same layer is a part of a same write bit line;

step 412, forming a second semiconductor layer of a second transistor of a memory cell of the plurality of memory arrays on the substrate, and a plurality of write word lines extending along a direction perpendicular to the substrate, wherein the second gates of adjacent memory cells of different layers are part of the same write word line; the second grid extends along the direction perpendicular to the substrate, the second semiconductor layer surrounds the second grid, and the first grid is connected with the second semiconductor layer; the second semiconductor layer comprises a second source contact area and a second drain contact area which are arranged at intervals, the third electrode is in contact with the second source contact area of the second semiconductor layer, the fourth electrode is in contact with the second drain contact area of the second semiconductor layer, and a channel between the second source contact area and the second drain contact area is a horizontal channel;

In step 413, a plurality of read word lines extending in a direction perpendicular to the substrate are patterned, and the second electrodes of adjacent memory cells of different layers are part of the same read word line.

According to the 3D memory array prepared by the preparation method of the 3D memory array, the grid electrode of the second transistor is of a vertical structure, the channel is of a horizontal channel and is not stacked with the first transistor, the size of memory cells in the direction perpendicular to the substrate can be reduced, memory cells in adjacent columns can share bit lines, 3D stacking of the 2T0C memory array with a compact structure can be conveniently manufactured, the process is simplified, and the cost is reduced. The preparation method of the embodiment of the disclosure can be realized by using the existing mature preparation equipment, has small improvement on the existing process, can be well compatible with the existing preparation process, and has the advantages of simple process realization, easy implementation, high production efficiency, low production cost and high yield.

In an exemplary embodiment, the forming the first gate electrode of the first transistor, the first semiconductor layer, the third electrode of the second transistor, the plurality of read bit lines, and the plurality of write bit lines on the substrate of the memory cells of the plurality of memory arrays includes:

In an exemplary embodiment, the depositing the semiconductor film, the gate oxide film, and the metal film includes: the semiconductor film, the gate oxide film, and the metal film are deposited by an atomic layer deposition method.

The structure, materials, related parameters and detailed preparation process of each film layer are described in the foregoing embodiments, and are not repeated here.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.

Claims

1. A 3D memory array, comprising: a plurality of memory arrays stacked in a direction perpendicular to a substrate, a plurality of write word lines extending in a direction perpendicular to the substrate; the memory array includes a plurality of memory cells, a plurality of read bit lines, and a plurality of write bit lines distributed in an array, the memory cells including: a first transistor and a second transistor disposed on the substrate, wherein:

2. The 3D memory array of claim 1, wherein the second gates of adjacent memory cells of different layers are part of a write word line to which the second gates are connected.

3. The 3D memory array of claim 1, wherein a first electrode of a memory cell of a same column of a same layer is part of a read bit line to which the first electrode is connected.

4. The 3D memory array of claim 1, wherein a fourth electrode of a memory cell of a same column of a same layer is part of a write bit line to which the fourth electrode is connected.

5. The 3D memory array of claim 1, further comprising a plurality of read word lines extending in a direction perpendicular to the substrate, the second electrodes of adjacent memory cells being connected to the same read word line in a direction perpendicular to the substrate.

6. The 3D memory array of claim 5, wherein the second electrodes of adjacent memory cells of different layers are part of a read word line to which the second electrodes are connected.

7. The 3D memory array of claim 1, wherein in the same memory array, the memory cells of the first column are connected to the same read bit line as the first electrode of the memory cells of the adjacent column or the fourth electrode is connected to the same write bit line, the memory cells of the last column are connected to the same read bit line as the first electrode of the memory cells of the adjacent column or the fourth electrode is connected to the same write bit line, the memory cells of the other columns except for the first column and the last column are connected to the same read bit line as the first electrode of one of the memory cells of the adjacent columns, and the fourth electrode of the memory cell of the other column is connected to the same write bit line.

8. The 3D memory array of claim 5, wherein the memory array is configured to store the data,

the first semiconductor layer comprises a first source contact area and a first drain contact area, the read bit line is connected with the first source contact area of the first semiconductor layer, and the write bit line is connected with the second drain contact area of the second semiconductor layer; the read word lines are respectively connected with first drain contact regions of the first semiconductor layers of the memory cells of different layers.

9. The 3D memory array of claim 8, wherein the read word line surrounds sidewalls of each first semiconductor layer of the memory cells of different layers and is connected to a first drain contact region of the sidewalls of each first semiconductor layer.

10. The 3D memory array of claim 8, wherein the first semiconductor layer comprises a sidewall, a first end, and a second end, the first end being connected to a second source contact region of the second semiconductor layer, the read bit line being connected to the second end.

11. The 3D memory array of claim 1, wherein the second semiconductor layers of the second transistors of adjacent ones of the memory cells of different layers are spaced apart in a direction perpendicular to the substrate.

12. The 3D memory array of claim 11, wherein an insulating layer is exposed between the second semiconductor layers disposed at the intervals, the insulating layer being a second gate insulating layer between the second gate electrode and the second semiconductor layer.

13. The 3D memory array of claim 1, wherein the second semiconductor layers of the second transistors of adjacent memory cells of different layers are connected as a unitary structure.

14. The 3D memory array according to any one of claims 1 to 13, wherein the first gate is all or part of the third electrode.

15. The 3D memory array according to any one of claims 1 to 13, wherein the first gate is connected to a second source contact region of the second semiconductor layer.

16. The 3D memory array of any one of claims 1 to 13, wherein the second drain contact region of the second semiconductor layer is opposite to and spaced apart from the second source contact region of the second semiconductor layer on a sidewall of the second semiconductor layer.

17. The 3D memory array according to any one of claims 1 to 13, wherein the first semiconductor layer comprises a sidewall and two ends, the first semiconductor layer comprising a first source contact region and a first drain contact region, the first drain contact region being located at the sidewall of the first semiconductor layer and surrounding the first semiconductor layer, the first source contact region being located at the sidewall of the first semiconductor layer and surrounding the first semiconductor layer, or at an end of the two ends remote from the second gate.

18. The 3D memory array according to any one of claims 1 to 13, wherein the first electrode extends in a third direction, the first gate electrode extends in a second direction, the third electrode extends in a second direction, the fourth electrode extends in a third direction, the second direction and the third direction being parallel to the substrate and intersecting.

19. The 3D memory array according to any one of claims 1 to 13, wherein the orthographic projection of the first electrode and the orthographic projection of the second electrode do not overlap on a plane parallel to the substrate; the orthographic projection of the third electrode does not overlap with the orthographic projection of the fourth electrode.

20. The 3D memory array according to any one of claims 1 to 13, wherein in a cross section perpendicular to the substrate, the first electrode, the second electrode, the third electrode are located on a first side of the second gate, the fourth electrode is located on a second side of the second gate, and the first side and the second side are opposite sides.

21. The 3D memory array according to any one of claims 1 to 13, wherein a surface of the first electrode on a side close to the substrate is at a smaller distance from the substrate than a surface of the third electrode on a side close to the substrate, and a surface of the first electrode on a side far from the substrate is at a larger distance from the substrate than a surface of the third electrode on a side far from the substrate.

22. The 3D memory array according to any one of claims 1 to 13, wherein the first electrode, the third electrode and the fourth electrode are located in the same conductive film layer along a direction perpendicular to the substrate.

23. The 3D memory array of any one of claims 1 to 13, wherein the memory array comprises a plurality of rows of memory cells and a plurality of columns of memory cells, the memory structure further comprising: a gating structure, the gating structure comprising: a row word line corresponding to a memory cell row of the memory array farthest from the substrate, a column word line corresponding to a memory cell column of the memory array farthest from the substrate, and a gate transistor corresponding to a memory cell of the memory array farthest from the substrate, the gate transistor including a fifth electrode, a sixth electrode, and a third gate, the third gate of the gate transistor corresponding to a memory cell of the same memory cell row being electrically connected to the same row word line, the sixth electrode of the gate transistor corresponding to a memory cell of the same memory cell column being electrically connected to the same column word line, the fifth electrode of the gate transistor being electrically connected to the second gate of the memory cell corresponding to the gate transistor.

24. The 3D memory array of claim 23, wherein the gating transistor further comprises: a third semiconductor layer disposed on a side of the fifth electrode away from the substrate, a fourth gate insulating layer disposed on a side of the third semiconductor layer away from the substrate; the third semiconductor layer extends along the direction perpendicular to the substrate, the sixth electrode surrounds the third semiconductor layer, the third semiconductor layer is provided with a containing cavity, the third grid is at least partially arranged in the containing cavity, the third grid and the third semiconductor layer are isolated through the fourth grid insulating layer, and the orthographic projection of the third semiconductor layer on the substrate is located in the orthographic projection of the fifth electrode on the substrate.

25. An electronic device comprising a 3D memory array according to any of claims 1 to 24.

26. A method for manufacturing a 3D memory array, wherein the 3D memory array comprises a plurality of layers of memory arrays stacked in a direction perpendicular to a substrate, and a plurality of write word lines extending in the direction perpendicular to the substrate; the memory array includes a plurality of memory cells distributed in an array, a plurality of read bit lines and a plurality of write bit lines, the memory cells including: a first transistor and a second transistor disposed on the substrate, the first transistor including a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer, the second transistor including a second gate electrode, a third electrode, a fourth electrode, and a second semiconductor layer, the method of manufacturing comprising:

27. The method of claim 26, wherein the method further comprises the steps of,

the forming a first gate of a first transistor, a first semiconductor layer, a third electrode of the second transistor, a plurality of read bit lines, and a plurality of write bit lines of memory cells of the plurality of memory arrays on a substrate includes:

28. The method of claim 26, wherein the method further comprises the steps of,

29. The method of claim 26, wherein the method further comprises the steps of,

30. The method of claim 26, wherein the method further comprises the steps of,