CN114864583A - Capacitor-free DRAM unit structure and manufacturing method - Google Patents
Capacitor-free DRAM unit structure and manufacturing method Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
The invention relates to a capacitor-free DRAM cell structure and a manufacturing method thereof. A capacitor-less DRAM cell structure comprises sequentially stacked from bottom to top: the semiconductor device comprises a semiconductor substrate, a first isolation layer, a lower source drain layer, a lower active region, a lower gate dielectric layer, a lower gate electrode layer, a second isolation layer, an upper source drain layer, an upper active region layer, an upper gate dielectric layer and an upper gate electrode layer; the lower source drain layer comprises a lower source electrode and a lower drain electrode which are separated by a first groove, and the bottom of the first groove is in contact with the first isolation layer; the upper source drain layer comprises an upper source electrode and an upper drain electrode which are separated by a second groove, and the bottom of the second groove is in contact with the second isolation layer; the lower gate electrode layer is electrically connected with the upper source drain layer through a contact hole arranged in the second isolation layer. The upper transistor and the lower transistor in the DRAM unit structure are completely overlapped, so that the unit area is saved, the integration density is improved, the multiplexing of a gate electrode photoetching plate can be realized, and the manufacturing cost is reduced.
Description
Technical Field
The invention relates to the field of transistors, in particular to a DRAM unit structure without capacitance and a manufacturing method thereof.
Background
A conventional DRAM (Dynamic Random Access Memory) unit is composed of a transistor and a capacitor, but as the integration level increases, the capacitor structure continues to shrink, the charge storage capacity continues to decrease, the leakage current is too fast, and the DRAM is about to reach the refresh frequency limit.
Thus, a semiconductor based on two oxides, IGZO (indium gallium zinc oxide InGaZnO) has emerged 4 ) A 2T0C (2transistor 0capacitor two transistor no capacitance) DRAM cell of thin film transistors, as shown in fig. 1, in which the drain of one transistor is connected to the gate of the other transistor, using the gate capacitance to store charge and changing the transistor transconductance to store information.
In recent years, 2T0C memory with Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide-IGZO) as the channel has been popular because the off-state current of IGZO-based Thin Film Transistor (Thin Film Transistor-TFT) is extremely small, and the DRAM cell used for 2T0C can significantly reduce the leakage rate. However, the existing IGZO TFT-based 2T0C DRAM cell generally uses 2 horizontal channel TFTs connected on the same plane, which occupies a large area and has a low integration density.
The invention is therefore proposed.
Disclosure of Invention
The invention mainly aims to provide a DRAM unit structure without capacitance and a manufacturing method thereof, wherein an upper transistor and a lower transistor are completely overlapped, the unit area is saved, the integration density is improved, the multiplexing of a gate electrode photoetching plate can be realized, and the manufacturing cost is reduced.
In order to achieve the above object, the present invention provides the following technical solutions.
The invention provides a capacitor-free DRAM unit structure, which comprises the following components in sequence from bottom to top: the semiconductor device comprises a semiconductor substrate, a first isolation layer, a lower source drain layer, a lower active region, a lower gate dielectric layer, a lower gate electrode layer, a second isolation layer, an upper source drain layer, an upper active region layer, an upper gate dielectric layer and an upper gate electrode layer;
the lower source-drain layer comprises a lower source electrode and a lower drain electrode which are separated by a first groove, the bottom of the first groove is in contact with the first isolation layer, and the lower active region fills the first groove and covers at least part of the surface of the lower source electrode and/or the lower drain electrode;
the upper source drain layer comprises an upper source electrode and an upper drain electrode which are separated by a second groove, the bottom of the second groove is in contact with the second isolation layer, and the upper active region fills the second groove and covers at least part of the surface of the upper source electrode and/or the upper drain electrode; the lower gate electrode layer is electrically connected with the upper source drain layer through a contact hole formed in the second isolation layer.
A second aspect of the present invention provides a method for fabricating a capacitorless DRAM cell structure, comprising:
providing a semiconductor substrate;
forming a first isolation layer on the surface of the semiconductor substrate;
forming a lower source electrode and a lower drain electrode which are separated by a first groove on the surface of the first isolation layer to form a lower source drain layer, wherein the bottom of the first groove is in contact with the first isolation layer;
forming a lower active region to fill the first recess and cover at least a portion of a surface of the lower source and/or the lower drain;
forming a lower gate dielectric layer to cover the surface of the lower active region;
forming a lower gate electrode layer on the surface of the lower gate dielectric layer;
forming a second isolation layer to cover the surface of the lower gate electrode layer;
etching a through hole in the second isolation layer, wherein the through hole penetrates through the surface of the lower gate electrode layer;
forming an upper source electrode and an upper drain electrode which are separated by a second groove on the surface of the second isolation layer to form an upper source drain layer, wherein the through holes are synchronously filled to form contact holes, and the bottom of the second groove is in contact with the second isolation layer;
forming an upper active region to fill the second recess and cover at least a portion of a surface of the upper source and/or the upper drain;
forming an upper gate dielectric layer to cover the surface of the upper active region;
and forming an upper gate electrode layer on the surface of the upper gate dielectric layer.
Compared with the prior art, the invention achieves the following technical effects:
according to the invention, the DRAM unit is formed by vertically stacked transistors at the upper layer and the lower layer, and the internal interconnection is adopted, so that a capacitor is not needed, the unit area is greatly reduced, and the integration level is improved; and the process manufacturing cost is reduced by multiplexing the grid photoetching plate for multiple times during manufacturing.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a schematic diagram of a prior art dual transistor capacitor-less DRAM;
FIG. 2 is a schematic diagram of a capacitor-less DRAM cell structure according to the present invention;
fig. 3 to 10 are schematic structural diagrams obtained at each step in the manufacturing method provided by the present invention;
FIG. 11 is a schematic diagram illustrating a memory principle of the memory cell structure provided by the present invention;
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In the prior art, 2T0C DRAM cells are generally connected on the same plane by using 2 horizontal channel TFTs, so that the occupied area is large, and the improvement of the integration density is not facilitated.
Therefore, the invention provides a capacitor-free DRAM cell structure with completely overlapped upper and lower layers of transistors, which can be functionally divided into three regions from bottom to top: the substrate, the first layer of transistors and the second layer of transistors are separated by the first isolation layer and the second isolation layer respectively among the three functional areas, and meanwhile, the upper layer of transistors and the lower layer of transistors can be electrically connected through contact holes formed in the second isolation layer to achieve internal interconnection.
As shown in fig. 2, a capacitorless DRAM cell structure comprises, stacked in order from bottom to top: the semiconductor device comprises a semiconductor substrate 1, a first isolation layer 2, a lower source-drain layer 3, a lower active region 4, a lower gate dielectric layer 5, a lower gate electrode layer 6, a second isolation layer 7, an upper source-drain layer 9, an upper active region layer 10, an upper gate dielectric layer 11 and an upper gate electrode layer 12.
The lower source-drain layer 3 comprises a lower source electrode and a lower drain electrode which are separated by a first groove, the bottom of the first groove is in contact with the first isolation layer 2, and the lower active region 4 fills the first groove and covers at least part of the surface of the lower source electrode and/or the lower drain electrode.
The upper source-drain layer 9 comprises an upper source and an upper drain separated by a second groove, the bottom of the second groove is in contact with the second isolation layer 7, and the upper active region 10 fills the second groove and covers at least part of the surface of the upper source and/or the upper drain; the lower gate electrode layer 6 is electrically connected to the upper source/drain layer 9 through a contact hole 8a provided in the second isolation layer.
The substrate 1 may be any substrate known to those skilled in the art for supporting components of a semiconductor integrated circuit, such as a silicon-on-insulator (SOI), bulk silicon (bulk silicon), silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge), a glass substrate, a polymer substrate, or the like.
The first isolation layer 2 and the upper second isolation layer 7 are made of a material having a high dielectric property and a high k dielectric, such as silicon oxide, silicon oxynitride, hafnium oxide, or aluminum oxide, and preferably at least one of silicon oxide, hafnium oxide, and aluminum oxide, as a passivation material. The first barrier layer 2 and the second barrier layer 7 may be of the same or different materials.
The lower source-drain layer 3 is composed of a source electrode and a drain electrode, and may be made of typical conductor materials such as molybdenum, titanium nitride, tungsten, and the like, and may be doped with corresponding types of N-type or P-type doping elements. The material of the upper source drain layer 9 is the same.
The upper gate dielectric layer 11 and the lower gate dielectric layer 5 are preferably at least one of silicon oxide, hafnium oxide and aluminum oxide, respectively.
The upper gate electrode layer 12 and the lower gate electrode layer 6 may be made of the same material as the source and drain electrodes, for example, at least one of molybdenum, titanium nitride, and tungsten may be used independently of each other.
In order to increase the integration of the memory, the upper and lower transistors preferably overlap as completely as possible, and one of the purposes is to: the lower active region 4, the lower gate electrode layer 6, the upper active region layer 10, and the upper gate electrode layer 12 are conformal. Further, the projection positions of the lower active region 4, the lower gate electrode layer 6, the upper active region layer 10, and the upper gate electrode layer 12 on the semiconductor substrate may be the same.
Meanwhile, in order to reduce leakage current, improve electrical characteristics, reduce material cost, and the like, the lower active region 4 covers at least a part of the surface of the lower source or the lower drain; the upper active region 4 covers at least a part of the surface of the upper source or the upper drain. In addition, the lower active region 4 and the upper active region 10 preferably cover the same side of the lower source drain layer 3 and the upper source drain layer 9. On the basis, the projection positions of the upper source drain layer 9 and the lower source drain layer 3 on the semiconductor substrate are further made to be the same, so that the same photoetching plate or mask can be adopted for the upper source drain layer 3 and the lower source drain layer 9 during manufacturing, and the process cost is reduced.
The same or different materials, such as typical semiconductor materials of silicon, germanium, etc., may be used for the active regions (lower active region, upper active region) in the upper and lower transistors.
The capacitor-less DRAM cell structure of the present invention has the following two outstanding features:
firstly, double-deck transistor-resistor logic is perpendicular to be piled up completely, and zero electric capacity is connected, has solved the big problem of plane channel 2T0C DRAM cell area occupied, has improved the integration density.
And secondly, the upper layer transistor and the lower layer transistor are interconnected through a contact hole in the second isolation layer, so that the space of a layer of electrode is saved, and the miniaturization of an integrated circuit is facilitated.
The operation principle of the above-described DRAM cell structure of the present invention is shown in fig. 11 (the position of the transistor in the figure is only for convenience of illustrating the operation principle, and does not represent the actual position layout), the first layer transistor is used as a read tube, the second layer transistor is used as a write tube, the gate of the first layer transistor and the drain of the second layer transistor are the same electrode, the write tube changes the charge in the gate capacitance of the read tube, and further affects the resistance state between the source and the drain of the read tube, thereby realizing the distinction between "0" and "1", and the specific principle is as follows.
In the write "1" process, a positive voltage (greater than the threshold voltage Vth) is applied to the gate electrode of the read transistor (i.e., the write word line WWL) to turn on the write transistor, and a positive voltage is applied to the source of the write transistor (i.e., the write bit line WBL) to inject charge into the gate capacitance (i.e., the storage node) of the read transistor. After the charge injection, the grid electrode and the source electrode voltage of the writing tube are removed, and the '1' state is stored;
reading 1, applying reading voltage to the drain of the reading tube, obtaining larger current due to certain charge in the gate capacitor and the reading tube in lower resistance state, and completing the reading 1 after amplified and identified by the peripheral circuit;
a write "0" process, wherein a positive voltage (greater than the threshold voltage Vth) is applied to the gate electrode of the read transistor (i.e., write word line WWL) to turn on the write transistor, and a negative voltage is applied to the source of the write transistor (i.e., write bit line WBL) to pull charge out of the gate capacitance (i.e., storage node) of the read transistor. After the electric charge is extracted, the grid electrode and the source electrode voltage of the writing tube are removed, and the '0' state is stored;
reading 0, applying reading voltage to the drain of the reading tube, obtaining smaller current when the reading tube is in higher resistance state due to no charge in the gate capacitor, and completing the reading 0 after amplified and identified by the peripheral circuit.
The present invention also provides a method for manufacturing the above-mentioned capacitor-less DRAM cell structure, which has the feature that one photolithography plate is repeatedly used for many times, and can reduce the process cost, as described below with reference to fig. 3 to 10.
First, a semiconductor substrate 1 is provided. The semiconductor substrate is optionally subjected to a pretreatment such as cleaning, polishing, or the like in an actual process.
Next, a first isolation layer 2 is formed on the surface of the substrate 1. A suitable forming means is selected depending on the type of material of the first separation layer 2. Taking silicon oxide as an example, typical methods such as PVD, ALD, CVD, etc. can be used for deposition, and the type of precursor used is not limited.
And forming a lower source electrode and a lower drain electrode on the surface of the first isolation layer 2, wherein the lower source electrode and the lower drain electrode are separated by a first groove to form a lower source drain layer 3, and the bottom of the first groove is in contact with the first isolation layer 2. This can be achieved by masking the area of the first isolation layer 2 where the first recess will be formed, and depositing a conductive material such as metal or titanium nitride in the non-masked area, thereby forming the source and drain. Or directly arranging a layer of conductor material on the surface of the first isolation layer 2 by deposition or evaporation, sputtering and the like, and then etching the area in which the first groove is preset to form the first groove. Or by other feasible means, and the present invention is not particularly limited thereto.
A lower active region 4 is then formed to fill the first recess and cover at least part of the surface of the lower source and/or the lower drain. The active region is formed by typical methods including but not limited to PVD, ALD, CVD, etc. The lower active region is typically significantly thinner than the thickness of the source and drain and therefore typically fills only a portion of the height of the first recess, as shown. Meanwhile, the lower active region 4 does not need to cover all the surfaces of the drain and the source, so that the lower active region needs to be grown by a photoetching plate, and the photoetching plate can be used for the growth of a lower gate electrode layer, an upper active region and an upper gate electrode layer in the following process, so that the effect of one plate with multiple purposes is realized.
A lower gate dielectric layer 5 is next formed overlying the surface of the lower active region 4. The forming means includes but is not limited to typical methods of PVD, ALD, CVD, etc. It should be noted that, in order to prevent the leakage current and other problems, the lower gate dielectric layer 5 is required to cover not only the surface of the lower active region 4, but also the exposed surfaces of the lower source and the lower drain.
And then forming a lower gate electrode layer 6 on the surface of the lower gate dielectric layer 5. This step can be referred to the formation of the lower active region, using the same reticle. In order to achieve the effect of complete overlapping of the upper and lower transistors, the selected position of the lower gate electrode layer 6 is preferably the same as the projected position of the lower active region 4 on the substrate 1.
A second spacer 7 is next formed covering the surface of the lower gate electrode layer 6. The second isolation layer 7 preferably adopts a large-area substrate method to completely cover the lower gate electrode layer and the gate dielectric layer, and has a larger thickness.
After the second spacer 7 is formed, a via hole 8 is etched therein, said via hole 8 penetrating to the surface of said lower gate electrode layer. The through hole 8 is used as a channel for connecting the upper layer transistor and the lower layer transistor, and the size of the through hole can be adjusted at will.
And then forming an upper source electrode and an upper drain electrode on the surface of the second isolation layer 7 and separated by a second groove to form an upper source drain layer 9, wherein the through hole 8 is synchronously filled to form a contact hole 8a, and the bottom of the second groove is in contact with the second isolation layer 7. This step synchronizes the complete via filling and the formation of the upper source drain layer 9. In an actual process, if the through hole is deep, in order to ensure that the through hole is completely filled, the deposition thickness of the source/drain electrode material may be too large, and the material can be etched back to a proper thickness of the source/drain electrode. The second groove may be formed by a method referred to the first groove.
An upper active region 10 is then formed to fill the second recess and cover at least part of the surface of the upper source and/or the upper drain. This step can use the reticle of the lower active region 10 to have the same shape while reducing the process cost.
Next, an upper gate dielectric layer 11 is formed to cover the surface of the upper active region 10, in reference to the formation process of the lower gate dielectric layer 5.
Then, an upper gate electrode layer 12 is formed on the surface of the upper gate dielectric layer 11, referring to the formation process of the lower gate electrode layer 6.
And finally, performing necessary subsequent processes, such as electrode extraction, packaging and the like.
In the above manufacturing method, the same photolithography plate is used when forming the lower active region 4, the lower gate electrode layer 6, the upper active region layer 10, and the upper gate electrode layer 12, which greatly reduces the process cost. In addition, the same photolithography plate may be used for the lower source drain layer 3 and the upper source drain layer 9.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. A DRAM cell structure without capacitor is characterized by comprising the following components which are stacked in sequence from bottom to top: the semiconductor device comprises a semiconductor substrate, a first isolation layer, a lower source drain layer, a lower active region, a lower gate dielectric layer, a lower gate electrode layer, a second isolation layer, an upper source drain layer, an upper active region layer, an upper gate dielectric layer and an upper gate electrode layer;
the lower source-drain layer comprises a lower source electrode and a lower drain electrode which are separated by a first groove, the bottom of the first groove is in contact with the first isolation layer, and the lower active region fills the first groove and covers at least part of the surface of the lower source electrode and/or the lower drain electrode;
the upper source drain layer comprises an upper source electrode and an upper drain electrode which are separated by a second groove, the bottom of the second groove is in contact with the second isolation layer, and the upper active region fills the second groove and covers at least part of the surface of the upper source electrode and/or the upper drain electrode; the lower gate electrode layer is electrically connected with the upper source drain layer through a contact hole formed in the second isolation layer.
2. The capacitorless DRAM cell structure of claim 1, wherein the lower active region, the lower gate electrode layer, the upper active region layer, and the upper gate electrode layer are conformal.
3. The capless DRAM cell structure of claim 1 or 2, wherein said lower active region covers at least a portion of a surface of said lower source or said lower drain; the upper active region covers at least a portion of a surface of the upper source or the upper drain.
4. The capless DRAM cell structure of claim 1, wherein said semiconductor substrate is at least one of a silicon substrate, a glass substrate, and a polymer substrate.
5. The capacitorless DRAM cell structure of claim 1, wherein the first isolation layer and the second isolation layer each independently employ at least one of silicon oxide, hafnium oxide, and aluminum oxide.
6. The capacitorless DRAM cell structure of claim 1, wherein said upper source drain layer, said upper gate electrode layer, said lower source drain layer, and said lower gate electrode layer each independently employ at least one of molybdenum, titanium nitride, and tungsten.
7. The capless DRAM cell structure of claim 1, wherein said upper and lower gate dielectric layers each independently employ at least one of silicon oxide, hafnium oxide, and aluminum oxide.
8. The capless DRAM cell structure of claim 1 or 2, wherein the lower active region, the lower gate electrode layer, the upper active region layer, and the upper gate electrode layer are projected onto the semiconductor substrate at the same location.
And/or the presence of a gas in the gas,
and the projection positions of the upper source drain layer and the lower source drain layer on the semiconductor substrate are the same.
9. The method of fabricating a capacitorless DRAM cell structure of any one of claims 1 to 8, comprising:
providing a semiconductor substrate;
forming a first isolation layer on the surface of the semiconductor substrate;
forming a lower source electrode and a lower drain electrode which are separated by a first groove on the surface of the first isolation layer to form a lower source drain layer, wherein the bottom of the first groove is in contact with the first isolation layer;
forming a lower active region to fill the first recess and cover at least a portion of a surface of the lower source and/or the lower drain;
forming a lower gate dielectric layer to cover the surface of the lower active region;
forming a lower gate electrode layer on the surface of the lower gate dielectric layer;
forming a second isolation layer to cover the surface of the lower gate electrode layer;
etching a through hole in the second isolation layer, wherein the through hole penetrates through the surface of the lower gate electrode layer;
forming an upper source electrode and an upper drain electrode which are separated by a second groove on the surface of the second isolation layer to form an upper source drain layer, wherein the through holes are synchronously filled to form contact holes, and the bottom of the second groove is in contact with the second isolation layer;
forming an upper active region to fill the second recess and cover at least a portion of a surface of the upper source and/or the upper drain;
forming an upper gate dielectric layer to cover the surface of the upper active region;
and forming an upper gate electrode layer on the surface of the upper gate dielectric layer.
10. The manufacturing method according to claim 9, wherein the same photolithography plate is used in forming the lower active region, the lower gate electrode layer, the upper active region layer, and the upper gate electrode layer.
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