CN117098395A - Three-dimensional vertical structure memory structure and preparation method thereof - Google Patents

Three-dimensional vertical structure memory structure and preparation method thereof Download PDF

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Publication number
CN117098395A
CN117098395A CN202311022432.8A CN202311022432A CN117098395A CN 117098395 A CN117098395 A CN 117098395A CN 202311022432 A CN202311022432 A CN 202311022432A CN 117098395 A CN117098395 A CN 117098395A
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layer
hole
isolation
gate
electrode layer
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高建峰
刘卫兵
李俊杰
周娜
杨涛
李俊峰
罗军
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

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  • Semiconductor Memories (AREA)

Abstract

The invention relates to a three-dimensional vertical structure memory structure and a preparation method thereof. Which comprises the following steps of sequentially stacking: a semiconductor substrate, a first isolation layer, a first and a second layer of transistors; the first layer transistor comprises a first source electrode layer, a second isolation layer, a first drain electrode layer and a third isolation layer which are stacked, and a first through hole which penetrates through the first source electrode layer in sequence, wherein the inner side wall of the first through hole is sequentially stacked with a first active layer, a first gate dielectric layer and a first gate electrode layer; the second layer transistor comprises a fourth isolation layer, a second source electrode layer and a fifth isolation layer which are stacked, and a second through hole penetrating to the first grid electrode layer, wherein a second active layer, a second grid dielectric layer and a second grid electrode layer are sequentially stacked on the inner side wall and the bottom wall of the second through hole; the first and second through holes have the same projection area and position. The upper transistor and the lower transistor are completely and vertically overlapped, so that the unit area is saved, the integration density is improved, and the manufacturing cost is reduced.

Description

Three-dimensional vertical structure memory structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor devices, in particular to a three-dimensional vertical structure memory structure and a preparation method thereof.
Background
The conventional DRAM (Dynamic Random Access Memory dynamic random access memory) unit is composed of a transistor and a capacitor, but as the integration level increases, the capacitor structure continues to shrink, the charge storage amount continues to decrease, the leakage is too fast, and the DRAM is about to reach the refresh frequency limit. In recent years, 2T0C (2transistor 0capacitor double transistor, no capacitance) DRAM cells based on two oxide semiconductor IGZO thin film transistors have appeared, as shown in fig. 1, in which the drain of one transistor is connected to the gate of the other transistor, charge is stored using the gate capacitance and the transconductance of the transistor is changed to store information, and in recent years, 2T0C memories having indium gallium zinc oxide (Indium Gallium Zinc Oxide-IGZO) as the channel have become popular because the off-state current of the IGZO thin film transistor (Thin Film Transistor-TFT) is extremely small, and the DRAM cell for 2T0C can significantly reduce the leakage rate. However, the existing 2T0CDRAM cell based on IGZO TFT generally uses 2 TFTs with horizontal channels connected on the same plane, which occupies a larger area and has a lower integration density.
For this purpose, the present invention is proposed.
Disclosure of Invention
The invention mainly aims to provide a three-dimensional vertical structure memory structure and a preparation method thereof, wherein an upper transistor and a lower transistor in the structure are completely and vertically overlapped, so that the unit area is saved, the integration density is improved, and the manufacturing cost is reduced.
In order to achieve the above technical scheme, the present invention provides the following technical scheme.
A first aspect of the present invention provides a three-dimensional vertical structure memory structure comprising, stacked in order from bottom to top: a semiconductor substrate, a first isolation layer, a first layer transistor and a second layer transistor;
the first layer transistor comprises a first source electrode layer, a second isolation layer, a first drain electrode layer and a third isolation layer which are sequentially stacked from bottom to top, and a first through hole which sequentially penetrates through the third isolation layer, the first drain electrode layer and the second isolation layer to the first source electrode layer, wherein a first active layer, a first gate dielectric layer and a first gate electrode layer are sequentially stacked on the inner side wall of the first through hole, and a first gate dielectric layer and a first gate electrode layer are sequentially stacked on the bottom wall of the first through hole;
the second-layer transistor comprises a fourth isolation layer, a second source electrode layer and a fifth isolation layer which are sequentially stacked from bottom to top, and a second through hole which sequentially penetrates through the fifth isolation layer, the second source electrode layer and the fourth isolation layer to the first grid electrode layer, wherein a second active layer, a second grid dielectric layer and a second grid electrode layer are sequentially stacked on the inner side wall and the bottom wall of the second through hole;
the projection area and the projection position of the first through hole and the second through hole on the first isolation layer are the same, and the first active layer of the inner side wall of the first through hole and the first active layer of the inner side wall of the second through hole are isolated by a dielectric material.
Therefore, the grid electrode of the first layer transistor and the drain electrode of the second layer transistor are the same electrode, and share one electrode, so that a double-transistor capacitance-free integration mode is realized, the two layers of transistors are vertically stacked, the unit area is saved compared with planar stacking, and the integration density is higher.
In addition, since the projection areas and positions of the first through hole and the second through hole are the same, the positions and the sizes of the upper layer transistor and the lower layer transistor can be the same, and the integration density can be further improved.
The above memory structure may be further improved to improve the overall performance of the device, as exemplified below.
Further, the dielectric material is the same as the first gate dielectric layer material.
Further, the semiconductor device further comprises a first contact plug, a second contact plug, a third contact plug and a fourth contact plug which are respectively and electrically connected with the first source electrode layer, the first drain electrode layer, the second source electrode layer and the second gate electrode layer in a one-to-one correspondence mode.
Further, the first contact plug, the second contact plug, the third contact plug, and the fourth contact plug are distributed in steps.
Further, the first active layer and the second active layer adopt indium gallium zinc oxide.
A second aspect of the present invention provides a method for manufacturing a three-dimensional vertical structure memory structure, comprising:
providing a semiconductor substrate;
forming a first isolation layer, a first source electrode layer, a second isolation layer, a first drain electrode layer and a third isolation layer on the surface of the semiconductor substrate from bottom to top in sequence;
etching to form a first through hole which sequentially penetrates through the third isolation layer, the first drain electrode layer and the second isolation layer to the first source electrode layer;
depositing a first active layer in the first through hole, selectively removing the first active layer on the bottom wall of the first through hole, and continuously depositing a first gate dielectric layer and a first gate layer in sequence in the first through hole;
flattening and stopping at the gate dielectric layer; or flattening and stopping at the third isolation layer, and then selectively covering the upper surface of the first active layer on the inner side wall of the first through hole with a dielectric material, and the upper surface of the first grid layer is not covered with the dielectric material;
forming a fourth isolation layer, a second source electrode layer and a fifth isolation layer above the first gate layer from bottom to top in sequence;
etching to form a second through hole which sequentially penetrates through the fifth isolation layer, the second source electrode layer and the fourth isolation layer to the first grid electrode layer;
and sequentially depositing a second active layer, a second gate dielectric layer and a second gate layer in the second through hole.
Therefore, the invention can realize that the upper and lower transistors with the same size share one electrode by at least two modes, and can avoid the interconnection of the active layers of the upper and lower transistors, and the active layers are separated by the first grid dielectric layer or the post-compensating dielectric material.
Further, after forming the second gate layer, the method further includes:
forming a sixth isolation layer over the second gate layer;
etching to form an isolation trench;
and filling insulating materials in the isolation trenches to form array units.
Further, after forming the array unit, forming a first contact hole penetrating to the first source electrode layer, a second contact hole penetrating to the first drain electrode layer, a third contact hole penetrating to the second source electrode layer, and a fourth contact hole penetrating to the second gate electrode layer, respectively;
and filling conductive materials in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole to form a first contact plug, a second contact plug, a third contact plug and a fourth contact plug.
Further, the first active layer and the second active layer adopt indium gallium zinc oxide.
Further, before forming the sixth isolation layer and after forming the second gate layer, further includes: and (5) carrying out surface planarization treatment.
Compared with the prior art, the invention achieves the following technical effects:
the upper transistor and the lower transistor in the memory structure are completely overlapped, so that the unit area is saved, the integration density is improved, the manufacturing cost is reduced, and two processes for preparing the structure are provided.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a circuit diagram of the operation of a two transistor, capacitance-free DRAM cell;
FIG. 2 is a schematic diagram of a three-dimensional vertical memory structure according to the present invention;
FIG. 3 is a functional schematic of the structures of FIG. 2 in operation;
fig. 4 to 13 are schematic structural diagrams obtained by each step in the process for manufacturing the three-dimensional vertical structure memory structure provided by the present invention, and detailed description will be given in the following.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
The 2T0C DRAM unit in the prior art is generally connected on the same plane by using 2 TFTs with horizontal channels, and has large occupied area and is not beneficial to improving the integration density.
To this end, the present invention provides a tft-based capacitorless DRAM cell structure as shown in fig. 2, which can be functionally divided into three main areas from bottom to top: the substrate, the first layer transistor, and the second layer transistor are specifically as follows.
The substrate 101 may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium on insulator, etc., with the corresponding top layer semiconductor material being silicon, germanium, silicon germanium, gallium arsenide, etc.
The substrate 101 is provided with an isolation layer 102, wherein the isolation layer 102 is made of a material such as oxide, oxynitride, or other high-k dielectric, for example, typically silicon oxide (SiO) 2 ) Silicon oxynitride, silicon nitride (SiN) x ) Etc.
With the isolation layer 102 as a boundary, the upper side is a first layer transistor, the transistor is vertically stacked, the function of a reading tube is realized, the reading tube comprises a first source layer 103, a second isolation layer 104, a first drain layer 105 and a third isolation layer 106 which are sequentially stacked from bottom to top, and a first through hole which sequentially penetrates through the third isolation layer 106, the first drain layer 105 and the second isolation layer 104 and is stopped at the first source layer 103, the inner side wall of the first through hole is sequentially stacked with a first active layer 107, a first gate dielectric layer 108 and a first gate layer 109, and the bottom wall of the first through hole is sequentially stacked with the first gate dielectric layer 108 and the first gate layer 109.
The structure of the first via determines that the first active layer 107 and the first gate dielectric layer 108 are both annular, and the cavity enclosed by the two is filled with the first gate layer 109. The bottom wall of the first via is free of the first active layer 107, so that a common electrode can be realized. In other words, the first gate layer 109 in the first layer transistor is also the drain of the upper second layer transistor, i.e. the first layer transistor shares one electrode with the second layer transistor.
The second-layer transistor is also vertically stacked to realize a writing function, and includes a fourth isolation layer 110, a second source layer 111 and a fifth isolation layer which are sequentially stacked from bottom to top, and a second through hole which sequentially penetrates through the fifth isolation layer, the second source layer 111 and the fourth isolation layer 110 and is stopped at the first gate layer 109, and the inner side wall and the bottom wall of the second through hole are sequentially stacked with a second active layer 113, a second gate dielectric layer 114 and a second gate layer 115. The structure of the second via determines that the second active layer 113 and the second gate dielectric layer 114 are both annular, and the cavity enclosed by the two is filled with the second gate layer 115.
It can be seen that the two-layer transistors are vertically stacked, and bit lines, word lines, gates and channels in each transistor are also vertically stacked, combined and connected in a surrounding manner, so that the multiple three-dimensional stacks greatly reduce the cell area and increase the integration density.
As shown in fig. 2, the first through hole and the second through hole have the same shape, that is, the projection areas and positions of the first through hole and the second through hole on the first isolation layer 102 are the same, so that the upper transistor layer and the lower transistor layer are completely overlapped, and the integration density is higher. The memory structure shown in fig. 2 also has the advantage of small parasitic capacitance compared to other vertically stacked 2t0c DRAMs, because: the first layer transistor and the second layer transistor are only metal electrodes in the through holes, especially storage nodes, and the parasitic capacitance between the first layer transistor and other electrodes of the transistor is greatly reduced by using the first layer transistor gate in situ as the second layer transistor drain.
In addition, to prevent the active layers of the first and second layer transistors from being electrically interconnected, the active layers are separated by a first gate dielectric layer or a post-repair dielectric material. Specifically, the first active layer 107 on the inner side wall of the first through hole and the first active layer 107 on the inner side wall of the second through hole are isolated by a dielectric material, and the dielectric material may be a gate dielectric material 108a conformally covered when the first gate dielectric layer 108 is deposited, or may be other dielectric materials added later.
A large area of deposited dielectric material can be provided over the second layer of transistors to fill and isolate the second layer of transistors. Meanwhile, in order to lead out each electrode, the semiconductor device further comprises a first contact plug 116, a second contact plug 117, a third contact plug 118 and a fourth contact plug 119 which are respectively and electrically connected with the first source electrode layer 103, the first drain electrode layer 105, the second source electrode layer 111 and the second gate electrode layer 115 in a one-to-one correspondence mode, and the contact plugs can be distributed in a stepped mode so as to reduce short circuit phenomenon and reduce process implementation difficulty.
The working circuit of the capacitor-free memory structure of the present invention is shown in fig. 1 (the positions of the transistors in the figure are only for convenience in illustrating the working principle and do not represent the actual position layout) and fig. 3 (the function of each electrode is marked), wherein the first layer of transistors is used as a reading tube, the second layer of transistors is used as a writing tube, the grid electrode of the first layer of transistors and the drain electrode of the second layer of transistors are the same electrode, and the charge in the grid capacitance of the reading tube is changed through the writing tube, so that the resistance state between the source electrode and the drain electrode of the reading tube is affected, and the specific principle is as follows.
In the process of writing "1", a positive voltage (greater than the threshold voltage Vth) is applied to the write word line WWL to turn on the write tube, and a positive voltage is applied to the write tube source (i.e., the write bit line WBL) to inject charge into the read tube gate capacitance (i.e., the storage node). After the charge injection, the gate and source voltages of the write tube are removed, and the "1" state is preserved.
And in the process of reading 1, a reading voltage is applied to the drain electrode of the reading tube, and the reading tube is in a lower resistance state due to certain charges in the gate capacitance, so that a larger current is obtained, and the process of reading 1 is completed after the peripheral circuit is amplified and identified.
The write "0" process, where a positive voltage (greater than the threshold voltage Vth) is applied to the read tube gate electrode (i.e., write word line WWL) to turn on the write tube, and a negative voltage is applied to the write tube source (i.e., write bit line WBL) to draw charge to the read tube gate capacitance (i.e., storage node). After the charge is extracted, the grid electrode and source electrode voltages of the writing tube are removed, and a 0 state is stored;
and in the process of reading 0, a reading voltage is applied to a drain electrode (RBL) of a reading tube, and the reading tube is in a higher resistance state because of no charge in a gate capacitor, so that smaller current is obtained, and the process of reading 0 is completed after the reading tube is amplified and identified by a peripheral circuit.
The above memory structure may be made of any material capable of realizing its basic function in terms of material selection, but each layer has its preferred material for further improving the electrical properties and use effect of the memory.
For example, the first active layer 107 and the second active layer 113 may each independently use In as a channel 2 O 3 At least one of ZnO and IGZO (indium gallium zinc oxide). Among them, the thin film transistor of IGZO can hold information of the storage node for a long time because its off-state leakage is very low.
The first gate dielectric layer 108 and the second gate dielectric layer 114 serve as insulation between the gate and the channel, and preferably a material with a wide band gap and a high dielectric constant is selectedOr materials suitable for making devices of very small dimensions, e.g. SiO 2 、HfO 2 、Al 2 O 3 At least one of them.
As electrodes to be connected to a power source, the first source layer 103, the first drain layer 105, the first gate layer 109, the second source layer 111, and the second gate layer 115 are preferably made of a metal material or a doped semiconductor material having good conductivity, including, but not limited to, at least one of Mo, tiN, ti, al, W, indium tin oxide, and indium zinc oxide. In addition, the first source layer 103, the first drain layer 105, the first gate layer 109, the second source layer 111, and the second gate layer 115 are preferably made of the same material or materials having very close properties in view of the rapid and stable current transfer between electrodes.
The first isolation layer 102, the second isolation layer 104, the third isolation layer 106, the fourth isolation layer 110, and the fifth isolation layer may be made of a material such as oxide, oxynitride, or other high-k dielectric, for example, typical silicon oxide (SiO) 2 ) Silicon oxynitride, silicon nitride (SiN) x ) Etc.
The invention also provides a method for manufacturing the memory structure, which has simple flow and good compatibility with the existing 3D semiconductor device processing technology, and is combined with figures 4 to 13 and 2, and the specific process is as follows.
First, a first insulating layer 102, a first source layer 103, a second insulating layer 104, a first drain layer 105, and a third insulating layer 106 are formed on the surface of the semiconductor substrate 101101 as shown in fig. 4. The layers are stacked from bottom to top and are deposited in a large area, and can be deposited by adopting deposition methods such as Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic layer deposition and the like.
Next, the first via structure is patterned to expose the first source layer 103, which may keep the via sidewall vertical, as shown in fig. 5 below.
Then depositing a first active layer 107 in the first through hole, and performing anisotropic etching to remove active materials on the upper surface, wherein only the first active layer 107 on the side wall of the first through hole is reserved; as in fig. 6.
Sequentially depositing a first gate dielectric layer 108 and a first gate electrode layer, flattening the first through hole structure, and stopping on the surface of the gate dielectric layer; as shown in fig. 7. The gate dielectric material remaining on the third spacer 106 may separate the channels of the upper and lower transistor layers. Or other processes may be used to achieve the above isolation. For example, planarization is stopped at the third isolation layer 106, and then the upper surface of the first active layer 107 on the inner sidewall of the first via hole is selectively covered with a dielectric material and the upper surface of the first gate layer 109 is not covered with the dielectric material. This step of the present invention is not limited to the two means listed above, as long as the active material on the inner sidewall of the first via can be isolated from the active material in the second via formed later.
Next, depositing a fourth isolation layer 110, a second source layer 111, a fifth isolation layer; as in fig. 8.
Patterning and etching the second via structure to expose the first gate layer 109; as in fig. 9.
Sequentially depositing a second active layer 113, a second gate dielectric layer 114 and a second gate layer 115, and flattening the second through hole; as in fig. 10.
Thereafter, a sixth isolation layer 120 is deposited, as shown in fig. 11 below. The sixth isolation layer 120 may be made of a material such as oxide, oxynitride, or the like, which is a high-k dielectric, for example, typically silicon oxide (SiO) 2 ) Silicon oxynitride, silicon nitride (SiN) x ) Etc.
A trench structure is formed by patterning process to isolate the source and drain layers and split into array cells, as shown in fig. 12 below.
The isolation groove is filled with a medium to form an isolation structure 121, and a flattening process is performed; as shown in fig. 13.
Finally, forming contact holes communicated with the electrodes through an etching process, wherein the contact holes comprise a first contact hole penetrating to the first source electrode layer 103, a second contact hole penetrating to the first drain electrode layer 105, a third contact hole penetrating to the second source electrode layer 111 and a fourth contact hole penetrating to the second gate electrode layer 115; the contact holes are distributed in a step shape as shown in fig. 2.
The above contact holes are filled with a conductive material to form a first contact plug 116, a second contact plug 117, a third contact plug 118, and a fourth contact plug 119, completing the interconnection process, as shown in fig. 2.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (10)

1. A three-dimensional vertical structure memory structure comprising, stacked in order from bottom to top: a semiconductor substrate, a first isolation layer, a first layer transistor and a second layer transistor;
the first layer transistor comprises a first source electrode layer, a second isolation layer, a first drain electrode layer and a third isolation layer which are sequentially stacked from bottom to top, and a first through hole which sequentially penetrates through the third isolation layer, the first drain electrode layer and the second isolation layer and is stopped at the first source electrode layer, wherein a first active layer, a first gate dielectric layer and a first gate electrode layer are sequentially stacked on the inner side wall of the first through hole, and a first gate dielectric layer and a first gate electrode layer are sequentially stacked on the bottom wall of the first through hole;
the second-layer transistor comprises a fourth isolation layer, a second source electrode layer and a fifth isolation layer which are sequentially stacked from bottom to top, and a second through hole which sequentially penetrates through the fifth isolation layer, the second source electrode layer and the fourth isolation layer and is stopped at the first grid electrode layer, and a second active layer, a second grid dielectric layer and a second grid electrode layer are sequentially stacked on the inner side wall and the bottom wall of the second through hole;
the projection area and the projection position of the first through hole and the second through hole on the first isolation layer are the same, and the first active layer of the inner side wall of the first through hole and the first active layer of the inner side wall of the second through hole are isolated by a dielectric material.
2. The three-dimensional vertical structure memory structure of claim 1, wherein said dielectric material is the same as said first gate dielectric layer material.
3. The three-dimensional vertical structure memory structure of claim 1, further comprising a first contact plug, a second contact plug, a third contact plug, a fourth contact plug electrically interconnected with the first source layer, the first drain layer, the second source layer, the second gate layer, respectively, in a one-to-one correspondence.
4. The three-dimensional vertical structure memory structure of claim 3, wherein the first contact plug, the second contact plug, the third contact plug, and the fourth contact plug are distributed in a stepwise manner.
5. The three-dimensional vertical structure memory structure according to any one of claims 1-4, wherein said first and second active layers are indium gallium zinc oxide.
6. A method for fabricating a three-dimensional vertical structure memory structure, comprising:
providing a semiconductor substrate;
forming a first isolation layer, a first source electrode layer, a second isolation layer, a first drain electrode layer and a third isolation layer on the surface of the semiconductor substrate from bottom to top in sequence;
etching to form a first through hole which penetrates through the third isolation layer, the first drain electrode layer and the second isolation layer in sequence and is stopped at the first source electrode layer;
depositing a first active layer in the first through hole, selectively removing the first active layer on the bottom wall of the first through hole, and continuously depositing a first gate dielectric layer and a first gate layer in sequence in the first through hole;
flattening and stopping at the gate dielectric layer; or flattening and stopping at the third isolation layer, and then selectively covering the upper surface of the first active layer on the inner side wall of the first through hole with a dielectric material, and the upper surface of the first grid layer is not covered with the dielectric material;
forming a fourth isolation layer, a second source electrode layer and a fifth isolation layer above the first gate layer from bottom to top in sequence;
etching to form a second through hole which penetrates through the fifth isolation layer, the second source electrode layer and the fourth isolation layer in sequence and is stopped at the first grid electrode layer;
and sequentially depositing a second active layer, a second gate dielectric layer and a second gate layer in the second through hole.
7. The method of manufacturing according to claim 6, further comprising, after forming the second gate layer:
forming a sixth isolation layer over the second gate layer;
etching to form an isolation trench;
and filling insulating materials in the isolation trenches to form array units.
8. The method of manufacturing as claimed in claim 7, wherein after forming the array unit, a first contact hole penetrating to the first source layer, a second contact hole penetrating to the first drain layer, a third contact hole penetrating to the second source layer, and a fourth contact hole penetrating to the second gate layer are formed, respectively;
and filling conductive materials in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole to form a first contact plug, a second contact plug, a third contact plug and a fourth contact plug.
9. The method of any one of claims 6-8, wherein the first and second active layers are indium gallium zinc oxide.
10. The method of manufacturing of claim 9, further comprising, before forming a sixth isolation layer and after forming the second gate layer: and (5) carrying out surface planarization treatment.
CN202311022432.8A 2023-08-14 2023-08-14 Three-dimensional vertical structure memory structure and preparation method thereof Pending CN117098395A (en)

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