CN114759030A

CN114759030A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN114759030A
Application number: CN202210280670.8A
Authority: CN
Inventors: 孙超; 江宁; 刘威
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-21
Filing date: 2022-03-21
Publication date: 2022-07-15

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof; the semiconductor structure includes: at least one transistor, the transistor comprising: a channel region in the semiconductor layer; a gate at least on one side of the channel region; a source region at a first end of the channel region; a drain region at a second end of the channel region; the first end and the second end are two ends of the channel region opposite to each other in a first direction respectively, and the first direction is the thickness direction of the semiconductor layer; at least one of the source region and the drain region includes a first layer region and a second layer region, each of the source region and the drain region includes a third layer region; the first layer area is positioned at one side close to the channel area; the third layer area is positioned on one side far away from the channel area; the second layer region is positioned between the first layer region and the third layer region; the doping type of the second layer region is different from the doping type of the first layer region and the doping type of the third layer region, or the second layer region is an intrinsic non-doping region. The embodiment of the invention can reduce the parasitic capacitance of the transistor and improve the response speed of the transistor.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method for fabricating the same.

Background

Transistors in semiconductor structures are widely used as switching devices or driving means in electronic devices. For example, the transistor may be used in a Dynamic Random Access Memory (DRAM) for controlling each Memory cell. It can be understood that the basic memory cell structure of the dynamic random access memory is composed of a transistor and a storage capacitor, and the main action principle is to use the magnitude of the stored charge in the capacitor to represent whether a binary bit (bit) is l or 0.

However, the existing transistors still have many problems to be improved.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for fabricating the same.

An embodiment of the present invention provides a semiconductor structure, including: at least one transistor, the transistor comprising: a channel region in the semiconductor layer;

a gate at least on one side of the channel region;

a source region at a first end of the channel region;

a drain region at a second end of the channel region; the first end and the second end are two opposite ends of the channel region in a first direction respectively, and the first direction is the thickness direction of the semiconductor layer;

At least one of the source region and the drain region comprises a first layer region and a second layer region, each of the source region and the drain region comprising a third layer region; the first layer area is positioned on one side close to the channel area; the third layer region is positioned on one side far away from the channel region; the second layer region is located between the first layer region and the third layer region;

the doping type of the second layer region is different from the doping types of the first layer region and the third layer region, or the second layer region is an intrinsic non-doping region.

In the above scheme, the doping types of the first layer region and the third layer region are both N-type doping;

the doping type of the second layer region is P-type doping.

In the above scheme, the maximum doping concentration of the third layer region is greater than the maximum doping concentration of the first layer region; the maximum doping concentration of the first layer region is greater than or equal to the maximum doping concentration of the second layer region.

In the above solution, a projection of the gate along a second direction does not completely overlap a projection of the second layer region along the second direction; the second direction is perpendicular to the first direction and is directed toward the channel region by the gate.

In the foregoing solution, a projection of the gate along a second direction does not overlap with a projection of the second layer region along the second direction.

In the above solution, the material of the second layer region and the material of the semiconductor layer both include monocrystalline silicon or polycrystalline silicon.

In the above scheme, the material of the second layer region includes silicon germanium, polysilicon, or a composite material of silicon germanium and polysilicon; the material of the semiconductor layer includes single crystal silicon.

In the above aspect, the at least one transistor includes a first transistor and a second transistor that are arranged in parallel and separated by an insulating layer;

the grid electrode of the first transistor is positioned on one side, far away from the insulating layer, of two sides of the first transistor; the gate of the second transistor is located on one of two sides of the second transistor, which is far away from the insulating layer.

In the above scheme, the type of the transistor includes one of:

a pillar-type gate transistor;

a semi-wrap around gate transistor;

a fully wrap around gate transistor.

An embodiment of the present invention further provides a semiconductor structure, including:

an array of memory cells; each memory cell in the array of memory cells includes a transistor extending in a first direction and a memory cell coupled to the transistor, wherein the transistor includes a semiconductor body extending in the first direction and a gate in contact with at least one side of the semiconductor body;

A plurality of bit lines; the plurality of bit lines coupled to the memory cells and extending in a second direction perpendicular to the first direction, a respective one of the bit lines and a respective memory cell coupled to opposite ends of each of the memory cells in the first direction;

wherein the semiconductor body comprises:

a channel region in the semiconductor layer;

a source region at a first end of the channel region;

In the above scheme, the doping types of the third layer region and the first layer region are both N-type doping;

the doping type of the second layer area is P-type doping.

In the above solution, the maximum doping concentration of the third layer region is greater than the maximum doping concentration of the first layer region; the maximum doping concentration of the first-layer region is greater than or equal to the maximum doping concentration of the second-layer region.

In the above scheme, one of the source region and the drain region of the transistor is coupled to the memory cell in the corresponding memory cell.

In the above scheme, the other of the source region and the drain region of the transistor is coupled to a corresponding bit line.

In the above solution, the semiconductor structure includes: a dynamic random access memory, a ferroelectric memory, a phase change memory, a magneto-resistive memory, or a resistive memory.

In the above scheme, the semiconductor structure includes a dynamic random access memory, and the memory cell includes a storage capacitor;

one end of the storage capacitor is coupled with the third layer region of the source region of the transistor;

the bit line is coupled with a third layer region of drain regions of the transistors.

The embodiment of the invention also provides a manufacturing method of the semiconductor structure,

Forming a memory cell array; each memory cell in the array of memory cells comprises a transistor extending in a first direction and a memory cell coupled to the transistor;

forming a plurality of bit lines; the plurality of bit lines coupled to the memory cells and extending in a second direction perpendicular to the first direction, a respective one of the bit lines and a respective memory cell coupled to opposite ends of each of the memory cells in the first direction;

the manufacturing method of the transistor comprises the following steps:

providing a semiconductor layer having at least one active pillar therein;

forming a source region at a first end of the active pillar;

forming a gate on at least one side of the active pillar;

forming a drain region at a second end of the active pillar; the first end and the second end are two opposite ends of the active column in a first direction respectively, and the first direction is the thickness direction of the semiconductor layer; an active pillar between the source region and the drain region constitutes a channel region of the transistor;

The doping type of the second layer region is different from the doping type of the first layer region and the doping type of the third layer region, or the second layer region is an intrinsic non-doping region.

In the foregoing solution, forming the second layer region includes:

the second layer region is formed by a diffusion process or an in-situ doping process.

In the above scheme, the material of the second layer region is the same as the material of the semiconductor layer;

forming a source region at a first end of the active pillar; forming a drain region at a second end of the active pillar; the method comprises the following steps:

sequentially carrying out ion implantation with different concentrations on the first end of the active column close to the first surface of the semiconductor layer to form a first layer region, a second layer region and a third layer region of the source region respectively;

thinning the semiconductor layer from the second surface of the semiconductor layer along a direction vertical to the semiconductor layer to expose a second end of the active column away from the first surface of the semiconductor layer; wherein the second surface is opposite the first surface;

and sequentially carrying out ion implantation with different concentrations on the second end of the active column to form a first layer region, a second layer region and a third layer region of the drain region respectively.

In the above scheme, the material of the second layer region is different from the material of the semiconductor layer;

performing ion implantation on a first end, close to the first surface of the semiconductor layer, of the active column to form a first layer region of the source region;

forming a first material layer on the first layer region of the source region, and performing ion implantation on the first material layer to form a second layer region of the source region;

forming a second material layer on the second layer region of the source region, and performing ion implantation on the second material layer to form a third layer region of the source region;

performing ion implantation on the second end of the active column to form a first layer region of the drain region;

forming a third material layer on the first layer region of the drain region, and performing ion implantation on the third material layer to form a second layer region of the drain region;

And forming a fourth material layer on the second layer region of the drain region, and performing ion implantation on the fourth material layer to form a third layer region of the drain region.

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: at least one transistor, the transistor comprising: a channel region in the semiconductor layer; the grid is at least positioned on one side of the channel region; a source region at a first end of the channel region; a drain region at a second end of the channel region; the first end and the second end are two opposite ends of the channel region in a first direction respectively, and the first direction is the thickness direction of the semiconductor layer; at least one of the source region and the drain region comprises a first layer region and a second layer region, each of the source region and the drain region comprising a third layer region; the first layer area is positioned on one side close to the channel area; the third layer region is positioned on one side far away from the channel region; the second layer region is located between the first layer region and the third layer region; the doping type of the second layer region is different from the doping types of the first layer region and the third layer region, or the second layer region is an intrinsic non-doping region. In each embodiment of the invention, a first layer region and a second layer region are arranged on a source region and/or a drain region, a third layer region is arranged on the source region and the drain region, and the doping types of the second layer region, the first layer region and the third layer region are different, so that a capacitor is formed between the third layer region and the first layer region and between the third layer region and the second layer region, and the capacitor is connected in series with a parasitic capacitor of a bit line, so that the parasitic capacitor of the transistor is reduced; the sensing allowance of the transistor is further increased, and the reliability of the reading safety coefficient is improved; meanwhile, the forming speed of inversion layer minority carriers between the grid and the channel region can be reduced, and the parasitic capacitance of the grid is further reduced, so that the sensing margin is increased, and the reliability is improved; in addition, the junction depth of the bit line connected with the drain region or the source region can be reduced, and the response speed of the transistor can be improved.

Drawings

FIG. 1a is a schematic circuit diagram of a DRAM transistor according to an embodiment of the present invention;

fig. 1b is a schematic structural diagram of a transistor provided in an embodiment of the present invention;

FIG. 2a is a schematic diagram of a semiconductor structure I according to an embodiment of the present invention;

FIG. 2b is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

fig. 2c is a schematic diagram of a semiconductor structure provided in the embodiment of the present invention;

FIG. 3a is a schematic view of another semiconductor structure provided in an embodiment of the present invention;

FIG. 3b is a schematic view of another semiconductor structure provided in an embodiment of the present invention;

fig. 4 is a schematic flow chart illustrating a method for manufacturing a transistor according to an embodiment of the present invention;

fig. 5a to fig. 5c are schematic views illustrating an implementation flow of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

fig. 6a to 6j are schematic views illustrating an implementation flow of another method for fabricating a semiconductor structure according to an embodiment of the present invention;

FIG. 7 is a schematic view of another semiconductor structure provided in an embodiment of the present invention;

FIG. 8 is a diagram illustrating test results of a simulation process according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a memory according to an embodiment of the present invention.

Description of the reference numerals

20-a transistor; 201-a channel region; 202-a source region; 203-a drain region; 204-a gate; 205-a first zone; 206-a second zone; 207-third zone; 208-a gate oxide layer; 209 a-a first material layer; 209 b-a second material layer; 209 c-a third material layer; 209 d-a fourth material layer; 210-a bit line; 211-storage capacitor contacts; 30-a first transistor; 301 — a channel region of a first transistor; 304-a gate of a first transistor; 305-a first storage capacitance; 40-a second transistor; 401 — a channel region of a second transistor; 404-a gate of the second transistor; 405-a second storage capacitance; 50-an insulating layer; 60-a semiconductor structure; n1 — doping concentration of the third layer region; n2 — doping concentration of the first layer region; n3 — doping concentration of the second layer region; t1 — transistors not provided with a second layer region; t2-a transistor provided with a second layer region;

in the drawings described above (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated with reference to the drawings and the embodiments. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

It is to be understood that the meaning of "on … …", "over … …" and "over … …" in the present invention should be interpreted in the broadest sense such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" with intervening features or layers therebetween.

Furthermore, spatially relative terms such as "on … …," "over … …," "over … …," "on," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In embodiments of the present invention, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, arsenic, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

In embodiments of the present invention, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.

In the embodiments of the present invention, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

Embodiments of the present invention relate to semiconductor structures that are to be used in subsequent processing to form at least a portion of a final device structure. Here, the final device may include a Memory, which includes but is not limited to a Dynamic Random Access Memory (DRAM), and the following description is only given by taking the DRAM as an example.

However, the following examples are only illustrative of the present invention and are not intended to limit the scope of the present invention.

With the development of dynamic random access memory technology, the size of the memory cell is getting smaller and smaller, and the array architecture thereof is made up of 8F²To 6F²To 4F²(ii) a In addition, based on the requirements for ions and leakage current in dynamic random access memories, the memory architecture is from Planar array transistors (Planar array transistors) to recessed gate array transistors (recessed gate array transistors), from recessed gate array transistors to Buried channel array transistors (Buried channel array transistors), and from Buried channel array transistors to Vertical channel array transistors (Vertical channel array transistors).

In some embodiments of the present invention, the dram, whether a planar Transistor or a buried Transistor, is composed of a plurality of memory cell structures, each memory cell structure is mainly composed of a Transistor and a memory cell (storage capacitor) controlled by the Transistor, that is, the dram includes a structure of 1 Transistor (T, Transistor) and 1 capacitor (C) (1T 1C); the main action principle is to use the magnitude of the stored charge in the capacitor to represent whether a binary bit is l or 0.

Fig. 1a is a schematic diagram of a control circuit adopting an architecture of 1T1C according to an embodiment of the present invention, as shown in fig. 1a, a drain of a transistor T is electrically connected to a Bit Line (BL), a source region of the transistor T is electrically connected to one electrode plate of a capacitor C, another electrode plate of the capacitor C may be connected to a reference voltage, the reference voltage may be a ground voltage or another voltage, and a gate of the transistor T is connected to a Word Line (WL); the transistor T is controlled to be turned on or off by applying a voltage to the word line WL, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.

It can be understood that, as shown in fig. 1b, the Source (S) and the Drain (D, Drain) of the transistor T are respectively located at two sides of the Gate (G, Gate), and a channel region is between the Source and the Drain; the projection of the gate in the X-axis direction needs to cover the projection of the channel region in the X-axis direction, but some embodiments of the present invention are based on the difference of the processes, so that there may be a partial Overlap (overlay) between the projection of the gate in the X-axis direction and the source and/or the drain, as shown by the dashed circle in fig. 1 b.

Therefore, two adjacent transistors in the plurality of transistors in the dynamic random access memory are closer to each other, and further parasitic capacitance from the grid electrode to the bit line is increased; in addition, when an operating voltage is applied to the Drain and a voltage applied to the Gate is less than 0, Gate Induced Drain Leakage (GIDL) may occur under a region where the Drain and the Gate overlap; when the problem of gate-induced drain leakage is too large, a floating body effect is generated in the transistor, and charge loss of a memory cell or a Storage node (Storage node) is caused.

In view of one or more of the above problems, embodiments of the present invention provide a semiconductor structure; fig. 2a to fig. 2c are schematic perspective views of a semiconductor structure according to an embodiment of the present invention, and as shown in fig. 2a, fig. 2b, and fig. 2c, the semiconductor structure includes: at least one transistor 20, said transistor 20 comprising:

A channel region 201 in the semiconductor layer;

a source region 202 at a first end of the channel region;

a drain region 203 at a second end of the channel region; the first end and the second end are two opposite ends of the channel region 201 in a first direction, respectively, where the first direction is a direction of a thickness of the semiconductor layer;

a gate 204 at least located at one side of the channel region 201;

at least one of the source region 202 and the drain region 203 comprises a first layer region 205 and a second layer region 206, the source region 202 and the drain region 203 each containing a third layer region 207; the first layer region 205 is located on a side near the channel region; the third layer region 207 is located on a side away from the channel region; the second layer region 206 is located between the first layer region 205 and the third layer region 207;

wherein, the doping type of the second layer region 206 is different from the doping types of the first layer region 205 and the third layer region 207, or the second layer region 206 is an intrinsic undoped region.

Here and hereinafter, the first direction is a direction of a thickness of the semiconductor layer; the second direction is vertical to the first direction and is vertical to the surface of the semiconductor layer; the third direction is perpendicular to both the first direction and the second direction; for convenience of describing the first direction, the second direction and the third direction in the embodiment of the present invention, in the following embodiment, the first direction is represented as the Z direction in the drawings; the second direction is indicated as the X direction in the drawing; the third direction is represented as the Y direction in the drawing; it should be noted that the above description of the direction is only for illustrating the present invention and is not intended to limit the scope of the present invention.

For example, when the first direction is a Z-axis direction, the parallel arrangement direction of the source region 202, the channel region 201, and the drain region 203 may be parallel to the Z-axis direction.

Here, the semiconductor layer may include an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

In some embodiments of the present invention, transistor 20 has a vertical channel (i.e., channel region 201), and source region 202 and drain region 203 of transistor 20 are located at two opposite ends (i.e., a first end and a second end) of the vertical channel, respectively. Here, a source region 202 is located at a first end of the channel region 201; a drain region 203 is located at a second end of the channel region 201; wherein the positions of the source region 202 and the drain region 203 may be interchanged. Namely, the source region 202 and the drain region 203 are two ends of the channel region 201 which are oppositely arranged in the Z-axis direction and can be interchanged.

In some embodiments of the present invention, the gate 204 may be located at one side of the channel region 201; or may be located on opposite sides of channel region 201; but may also be located around the channel region 201. The specific position can be set according to the actual requirement of the transistor; here, the gate 204 is positioned on one side of the channel region 201 as an example.

Here, the material of the gate 204 may include metal or polysilicon (Poly).

It should be noted that in some embodiments of the present invention, a Gate oxide layer (Gate oxide layer)208 is further disposed between the Gate 204 and the channel region 201 for electrically isolating the channel region 201 and the Gate 204.

It is understood that the gate oxide layer in the transistor can be used to induce different electric fields and applied on the surface of the channel region, so that minority carriers of the substrate (semiconductor layer) are absorbed to the surface of the channel region to accumulate and invert, and the gate oxide layer becomes the same doping type of the source region and the drain region, thereby realizing conduction between the source region and the drain region.

In some embodiments, after a gate voltage is applied to the gate, that is, after a strong electric field is generated, electrons continuously drift along the direction of the electric field and are continuously accelerated, so that a large kinetic energy can be obtained, and when the electrons collide with the gate oxide layer due to the existence of a voltage difference from a source region to a drain region, the electrons are injected into the gate oxide layer, so that a hot carrier effect is generated; this hot carrier effect has a large influence on the reliability of the transistor.

Here, the material of the gate oxide layer 208 may include, but is not limited to, silicon oxide.

In the embodiment of the present invention, the first layer region 205 and the second layer region 206 are disposed in the source region 202 and/or the drain region 203; a third layer region 207 is disposed in both the source region 202 and the drain region 203.

In some embodiments, first layer region 205 can be understood to be a lightly doped drain region; the second layer region 206 can be understood as a doped region; or an intrinsic undoped region; the third layer region 207 in the source region 202 can be understood as the source; the third layer region 207 in the drain region 203 can be understood as a drain.

It is understood that the lightly doped drain region is a structure adopted by the device to reduce the electric field of the drain region to improve the hot carrier effect, i.e. a drain region with low doping concentration is arranged near the channel region close to the drain region or the source region, so that the lightly doped drain region bears partial voltage, and the structure can prevent the hot carrier effect.

That is, in some embodiments of the present invention, the first layer region 205 may be used to prevent hot carrier effects.

Here, the second layer region 206 is a doped region, which can be understood as an ion doping of the second layer region 206 to provide doping properties.

While the second layer region 206 is an intrinsic undoped region, it is understood that the second layer region 206 is a layer of undoped pure semiconductor material, such as a silicon layer.

Here, the doping type of the second layer region 206 is different from the doping type of the first layer region 205.

It is noted that in some embodiments of the present invention, the first layer region 205 can be provided with only the source region 202; may be provided only in the drain region 203; it may also be provided at both source region 202 and drain region 203. The second layer region 206 is preferably disposed in the source region 202 and/or the drain region 203 at the same time as the first layer region 205.

Exemplarily, the first layer region 205 and the second layer region 206 are only provided in the source region 202, with reference to fig. 2 a.

Exemplarily, the first layer region 205 and the second layer region 206 are only provided in the drain region 203, with reference to fig. 2 b.

Illustratively, the first layer region 205 and the second layer region 206 are disposed at both the source region 202 and the drain region 203, with reference to fig. 2 c.

Illustratively, the first layer region 205 and the second layer region 206 are disposed in the source region 202, and only the first layer region 205 is disposed in the drain region 203.

Illustratively, the first layer region 205 and the second layer region 206 are disposed in the drain region 203, and only the first layer region 205 is disposed in the source region 202.

Here, the doping type of the second layer region 206 is different from the doping type of each of the first layer region 205 and the third layer region 207.

It can be understood that, during the read operation performed on the memory cell, the doping type of the second layer region 206 is different from the doping types of the first layer region 205 and the third layer region 207, so that a capacitor is formed between the second layer region 206, the first layer region 205 and the third layer region 207; the capacitor is connected in series with a parasitic capacitor from the gate 204 to the bit line, so that the parasitic capacitor of the transistor is reduced, the sensing margin of the transistor is increased, and the reliability of the reading safety coefficient is improved.

In addition, the second layer region 206 is disposed between the third layer region 207 and the first layer region 205, which can also reduce the junction depth at the junction between the bit line and the third layer region 207 and improve the response speed of the transistor.

Illustratively, when the third layer region 207 of the drain region 203 is connected to a bit line, the junction depth at the connection of the third layer region 207 of the drain region 203 and the bit line may be reduced, which may improve the response speed of the transistor 20.

In some embodiments of the present invention, transistor 20 may be an N-type transistor; or may be a P-type transistor.

Illustratively, in an N-type transistor, the doping types of the first layer region 205 and the third layer region 207 are both N-type doping; and the doping type of the second layer region 206 is P-type doping.

In the P-type transistor, the doping types of the first layer region 205 and the third layer region 207 are both P-type doping; and the doping type of the second layer region 206 is N-type doping.

It is understood that the doping type of the second layer region 206 is different from the doping type of the third layer region 207, so that the formation speed of inversion layer minority carriers between the gate 204 and the channel region 201 is reduced, and the parasitic capacitance from the gate 204 to the bit line is reduced.

In addition, when the doping type of the third layer region 207 is different from the doping type of the second layer region 206, the second layer region 206 and the first layer region 205 are mutually depleted, so as to reduce the voltage difference between the drain region 203 and the gate 204 and/or between the source region 202 and the gate 204, and further reduce the problem of gate-induced drain leakage.

In some embodiments of the present invention, the concentration of the second layer region 206 can be adjusted according to actual needs.

In some embodiments, the maximum doping concentration of the third layer region 207 is greater than the maximum doping concentration of the first layer region 205; the maximum doping concentration of the first layer region 205 is greater than or equal to the maximum doping concentration of the second layer region 206.

In some embodiments of the present invention, the doping concentrations of the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203 are both N1; the doping concentrations of the first layer region 205 of the source region 202 and the first layer region 205 of the drain region 203 are both N2; the doping concentration of the second layer region 206 of the source region 202 and the doping concentration of the second layer region 206 of the drain region 203 are both N3, here, the doping concentration N1 of the third layer region 207 is greater than the doping concentration N2 of the first layer region 205, i.e., N1 > N2; the doping concentration N2 of the first layer region 205 is greater than or equal to the doping concentration N3 of the second layer region 206, i.e., N2 ≧ N3.

For example, the doping concentration ranges of the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203 may be: 1e19atom/cm³To 1e21atom/cm³(ii) a The doping concentration range of the first layer region 205 of the source region 202 and the first layer region 205 of the drain region 203 may be: 1e16atom/cm ³To 1e19atom/cm³(ii) a The doping concentration ranges of the second layer region 206 of the source region 202 and the second layer region 206 of the drain region 203 may be: 1e0atom/cm³To 1e16atom/cm³. Here, the atom/cm³Representing the number of atoms contained in each cubic centimeter.

It should be noted that, in some specific examples, after the first layer region 205 of the source region 202 and the first layer region 205 of the drain region 203, the second layer region 206 of the source region 202 and the second layer region 206 of the drain region 203, and the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203 are formed, in the source region 202 or the drain region 203, the doping concentration of the regions, which overlap each other, among the first layer region 205, the second layer region 206, and the third layer region 207 is complicated, and a situation different from the above-mentioned doping concentration rule may occur.

Based on this, for the sake of expression stringency, it is defined herein that the maximum doping concentration of the third layer region 207 of the source region 202 or the drain region 203 is greater than the maximum doping concentration of the first layer region 205 of the source region 202 or the drain region 203; the maximum doping concentration of the first layer region 205 of the source region 202 or the drain region 203 is greater than or equal to the maximum doping concentration of the second layer region 206 of the source region 202 or the drain region 203.

It should be noted that the maximum concentration here is understood to mean the doping concentration that is expected to be achieved by manufacturing, and the case where the doping concentration is different from the above-mentioned doping concentration rule due to manufacturing difference or special position of the structure (such as the boundary of different doping concentrations) is included in the protection scope of the present application.

In some embodiments of the present invention, the material of the second layer region 206 can be the same as or different from the material of the channel region 201.

In some embodiments, the material of the second layer region 206 of the source region 202 or the drain region 203 is the same as the material of the semiconductor layer.

Illustratively, the material of the second layer region 206 of the source region 202 or the drain region 203 and the material of the semiconductor layer each include single crystal silicon (Si) or polycrystalline silicon (Poly).

In some embodiments, the material of the second layer region 206 of the source region 202 or the drain region 203 is different from the material of the semiconductor layer.

Illustratively, the material of the second layer region 206 of the source region 202 or the drain region 203 includes silicon germanium (SiGe), polysilicon, or a composite material of silicon germanium and polysilicon; the material of the semiconductor layer includes single crystal silicon.

In some embodiments of the present invention, the thickness of the second layer region 206 of the source region 202 or the drain region 203 needs to be matched with the total thickness of the transistor, and the thickness of the second layer region 206 of the source region 202 or the drain region 203 can be set according to the actual thickness of the transistor or the actual requirement of a person skilled in the art.

In some embodiments, the thickness of the second layer region 206 of the source region 202 or the second layer region 206 of the drain region 203 is: 10nm-20 nm.

It should be noted that, in some embodiments of the present invention, two ends of the gate 204 and the gate oxide layer 208 may extend to be flush with two ends of the third layer region 207 of the source region 202 or the third layer region 207 extending to the drain region 203; however, it is understood that the projection of the gate 204 and the gate oxide 208 along the second direction only needs to cover the channel region 201 to ensure the normal operation of the transistor 20, and when the projection of the gate 204 and the gate oxide 208 along the second direction extends beyond the channel region 201 to two ends, the more the extension is, the larger the overlap region of the projection of the gate 204 and the third layer region 207 in the source region 202 or the projection of the gate 204 and the third layer region 207 in the drain region 203 along the second direction is, the larger the parasitic capacitance in the transistor 20 is.

Based on this, in some embodiments of the present invention, a projection of the gate 204 along a second direction does not completely overlap with a projection of the second layer region 206 along the second direction; the second direction is perpendicular to the first direction and is directed by the gate 204 toward the channel region 201.

Here, a projection of the gate 204 in the second direction may partially overlap a projection of the second layer region 206 in the second direction, or may not overlap a projection of the second layer region 206 in the second direction.

In order to satisfy the basic function of the transistor, the projection of the gate 204 along the second direction needs to completely cover the channel region, and the less the overlap between the projection of the gate along the second direction and the source region or the drain region, the smaller the parasitic capacitance of the transistor; in addition, the probability of the occurrence of the gate-induced drain leakage problem can be reduced.

In practical applications, the projection length of the gate along the second direction may also be set according to process requirements. It should be noted that, in the embodiment of the present invention, the semiconductor structure may include one or more transistors.

In some embodiments, as shown in fig. 3a, the semiconductor structure includes a first transistor 30 and a second transistor 40 disposed side-by-side and separated by an insulating layer;

the gate 304 of the first transistor 30 is located on one of the two sides of the first transistor 30 that is distal from the insulating layer 50; the gate 404 of the second transistor 40 is located on one of two sides of the second transistor 40 away from the insulating layer 50.

In some embodiments of the present invention, referring to fig. 3a and 3b, an insulating layer 50 is disposed between the first transistor 30 and the second transistor 40.

Here, the material of the insulating layer 50 may be a silicon dioxide material or other insulating material.

In the first transistor 30, the channel region 301 includes a first side and a second side; the first side of the channel region 301 may be understood as the side of the two sides of the first transistor 30 which is remote from said insulating layer 50, and the second side of the channel region 301 may be understood as the side of the two sides of the first transistor 30 which is close to said insulating layer 50, where the gate 304 is located at the first side of the channel region 301.

In the second transistor 40, the channel region 401 includes a first side and a second side; wherein, the first side of the channel region 401 may be understood as one of the two sides of the second transistor 40 close to the insulating layer 50; the second side of the channel region 401 may be understood as the side of the two sides of the second transistor 40 facing away from the insulating layer 50; here, a gate 404 is located at a second side of the channel region 401.

It should be noted that the aforementioned arrangement of the second layer region 206 of the source region 202 between the third layer region 207 of the source region 202 and the first layer region 205 of the source region 202, and/or the arrangement of the second layer region 206 of the drain region 203 between the third layer region 207 of the drain region 203 and the first layer region 205 of the drain region 203 may be applied to both the first transistor 30 and the second transistor 40. In practice, the transistors may comprise different types of transistors. In particular, the amount of the solvent to be used,

According to the difference of the number of gates, the transistor can comprise: single gate transistors, double gate transistors.

According to the position relationship between the gate and the channel region, the transistor may further include: a pillar gate transistor, a half-wrap gate transistor, a full-wrap gate transistor, etc.

According to the sectional shapes of the source region, the drain region and the channel region in the XZ plane, the transistor may include: an I-type gate transistor, an L-type gate transistor, a T-type gate transistor, a U-type gate transistor, etc.

According to the cross-sectional shapes of the source region and the drain region in the XZ plane, the transistor may include: square transistors, oval transistors, semi-circular transistors, etc.

In the transistor, the cross-sectional shape of the second layer region 206 is the same as the (horizontal) cross-sectional shapes of the third layer region of the source region and the third layer region of the drain region.

In some embodiments of the invention, the type of the transistor comprises one of:

a pillar-type gate transistor;

a semi-wrap around gate transistor;

a fully wrap around gate transistor.

In the column type grid transistor, a grid electrode is surrounded around a channel region in a column form; in the semi-surrounding type grid electrode transistor, a grid electrode semi-surrounds a channel region; in the all-around gate transistor, the gate completely surrounds the channel region.

It should be noted that the transistor types in the embodiment of the present invention may include the above-mentioned various types, but are not limited thereto.

Here, fig. 3b is a schematic view of another semiconductor structure provided in the embodiment of the present invention. As shown in fig. 3b, the semiconductor structure further includes a bit line 210 connected to the third layer region 207 of the drain region 203, a first storage capacitor 305 and a second storage capacitor 405 connected to the third layer region 207 of the source region 202, first electrodes of the first storage capacitor 305 and the second storage capacitor 405 are connected to the third layer region 207 of the source region 202 through a storage capacitor contact 211, and a second electrode of the first storage capacitor 305 is connected to a common terminal (not shown); here, the first storage capacitor 305 and the second storage capacitor 405 are used to store data.

Based on the semiconductor structure, the embodiment of the invention also provides a manufacturing method of the semiconductor structure; wherein the step of forming the semiconductor structure comprises:

the method comprises the following steps: forming a memory cell array; each memory cell in the array of memory cells includes a transistor extending in a first direction and a memory cell coupled to the transistor;

Step two: forming a plurality of bit lines; the plurality of bit lines are coupled to the memory cells and extend in a second direction perpendicular to the first direction, a respective one of the bit lines and a respective memory cell are coupled to opposite ends of each of the memory cells in the first direction.

It should be noted that the process for forming the memory cell array and the corresponding bit lines is mature, and will not be described herein again.

Here, a method for forming a transistor is provided in an embodiment of the present invention, and fig. 4 is a schematic flow chart of the method for forming a transistor according to the embodiment of the present invention. As shown in fig. 4, the method of forming the transistor includes the steps of:

step 401: providing a semiconductor layer having at least one active pillar therein;

step 402: forming source/drain regions at a first end of the active pillar;

step 403: forming a gate on at least one side of the active pillar;

step 404: forming a drain/source region at a second end of the active pillar; the first end and the second end are two opposite ends of the active column in a first direction respectively, and the first direction is the thickness direction of the semiconductor layer; the active column between the source region and the drain region forms a channel region of the transistor;

It should be understood that the steps shown in FIG. 4 are not exclusive, and other steps may be performed before, after, or between any of the steps in the operations shown; the steps shown in fig. 4 may be sequentially adjusted according to actual needs. Fig. 5a to 5c are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the invention, and fig. 6a to 6j are schematic cross-sectional views illustrating a manufacturing process of another semiconductor structure according to an embodiment of the invention. The method for fabricating the semiconductor structure according to the embodiment of the present invention is described in detail below with reference to fig. 4, fig. 5a to fig. 5c, and fig. 6a to fig. 6 j.

It should be noted that, in the embodiment of the present invention, the source region and the drain region need to be respectively disposed at two sides of the channel region; in other words, if the source region is formed in step 402, the drain region is formed in step 404; alternatively, if the drain region is formed in step 402, the source region is formed in step 404. Here, to form a source region in step 402; the formation of the drain region in step 404 is described as an example; here, the formation order of step 402, step 403, and step 404 may be set according to implementation requirements. In other words, the execution sequence of the steps in the following embodiments is only for illustrating the present invention and is not intended to limit the scope of the present invention.

In step 401, as shown in fig. 5a, a semiconductor layer is provided.

Wherein the semiconductor layer has at least one active pillar therein; the active pillars extend in a first direction; the first direction is a thickness direction of the semiconductor layer.

Illustratively, the first direction is a Z-axis direction along which the active pillars extend.

It should be noted that the extending direction of the active pillars can be selected according to actual requirements; here, the active pillars are described as extending in the Z-axis direction.

The material of the semiconductor layer may include silicon (Si), germanium (Ge), a silicon germanium (SiGe) substrate, etc.; in some embodiments, the semiconductor layer may also be Silicon-On-Insulator (SOI) or Germanium-On-Insulator (GOI);

In some embodiments of the present invention, the semiconductor Layer may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, and the like.

In step 402, source region 202 is formed at a first end of the active pillar, as shown in fig. 5 b.

Here, the first layer region 205 can be understood as a lightly doped drain region; the second layer region 206 can be understood as a doped region; or an intrinsic undoped region; in some embodiments, the first layer region 205 and the second layer region 206 may be disposed only in the source region 202; may be provided only in the drain region 203; may also be provided in both source region 202 and drain region 203.

Preferably, the first layer region 205 and the second layer region 206 are disposed only in the drain region 203.

It should be noted that the first layer region 205 and the second layer region 206 need to be present in the source region 202 and/or the drain region 203 at the same time, which has been mentioned previously, and will not be described herein again.

Here, the source region 202 and the drain region 203 each contain a third layer region 207; in other words, the third layer region 207 of the source region 202 can be understood as a source; the third layer region 207 of the drain region 203 can be understood as a drain.

Here, in order to facilitate understanding of the formation processes of the first layer region 205, the second layer region 206, and the third layer region 207, in the following embodiments, the source region 202 and the drain region 203 each include the first layer region 205, the second layer region 206, and the third layer region 207 as an example; it is to be understood, however, that the following description of the location of the first zone 205 and the second zone 206 is provided for purposes of illustration and is not intended to limit the scope of the present invention.

Based on this, the source region 202 has a first layer region 205 of the source region 202, a second layer region 206 of the source region 202, and a third layer region 207 of the source region 202, which are sequentially arranged in parallel; a first layer region 205 of the source region 202 is located on a side near the channel region; the third layer region 207 of the source region 202 is located on a side away from the channel region; the second layer region 206 of the source region 202 is located between the first layer region 205 of the source region 202 and the third layer region 207 of the source region 202.

Here, the first end and the second end of the active pillar are respectively opposite ends of the active pillar in a first direction, where the first direction is a thickness direction of the semiconductor layer.

It should be noted that the material of the second layer region 206 can be the same as or different from the material of the active pillars; the method of forming the source and drain regions is different when the material of the second layer region 206 is the same as or different from the material of the active pillars.

In the embodiment of the present invention, the material of the second layer region 206 is the same as that of the active pillars, and the source region and the drain region are formed in the first way.

Illustratively, the material of the second layer region 206 and the material of the semiconductor layer each comprise single crystal silicon or polycrystalline silicon.

Source and drain regions are formed in a manner where the material of the second layer region 206 is different from the material of the active pillars.

Illustratively, the material of the second layer region 206 includes silicon germanium, polysilicon, or a composite structure of silicon germanium and polysilicon; the material of the semiconductor layer includes single crystal silicon.

The source region 202 and the drain region 203 are formed in the same manner as described below with reference to fig. 5 a-5 c. Here, referring to fig. 5a and 5b, a first layer region 205 of the source region 202, a second layer region 206 of the source region 202, and a third layer region 207 of the source region 202 are formed at the first end of the active pillar in parallel in this order; in particular, the amount of the solvent to be used,

and sequentially performing ion implantation with different concentrations on the first end of the active column close to the first surface of the semiconductor layer to form a first layer region 205 of the source region 202, a second layer region 206 of the source region 202 and a third layer region 207 of the source region 202 respectively.

In some embodiments, the forming the first layer region 205 of the source region 202, the second layer region 206 of the source region 202, and the third layer region 207 of the source region 202 includes:

The first layer region 205 of the source region 202, the second layer region 206 of the source region 202, and the third layer region 207 of the source region 202 are formed by a diffusion process or an in-situ doping process.

Illustratively, first, a first layer region 205 of the source region 202 is formed in the first end of the active pillar on a side close to the channel region 201 by a diffusion process or an in-situ doping process;

secondly, forming a second layer region 206 of the source region 202 on a side of the first layer region 205 of the source region 202 away from the channel region 201 by a diffusion process or an in-situ doping process;

finally, a third layer region 207 of source region 202 is formed by a diffusion process or an in-situ doping process on the side of the second layer region 206 of the source region 202 remote from the first layer region 205 of the source region 202.

In practical applications, after performing the diffusion process or the in-situ doping process, the first layer region 205 of the source region 202, the second layer region 206 of the source region 202, and the third layer region 207 of the source region 202 are formed by annealing; in practical applications, after performing the diffusion process or the in-situ doping process each time, the first layer region 205 of the source region 202, the second layer region 206 of the source region 202, or the third layer region 207 of the source region 202 may be annealed once; the annealing process may be performed on the first layer region 205 of the source region 202, the second layer region 206 of the source region 202, and the third layer region 207 of the source region 202 at the same time after performing three diffusion processes or in-situ doping process operations. The annealing mode can be selected according to actual requirements.

In practical applications, the annealing process is mature, and is not described herein again.

Here, the material of the second layer region 206 of the source region 202 and the material of the semiconductor layer both comprise single crystal silicon or polycrystalline silicon.

In some embodiments, the dopant ions of the first layer region 205 of the source region 202 and the third layer region 207 of the source region 202 may be N-type ions or P-type ions; the dopant ions in the second region 206 of the source region 202 can be P-type ions or N-type ions; however, in the embodiment of the present invention, the doping type of the second layer region 206 of the source region 202 is different from that of the first layer region 205 of the source region 202 and the third layer region 207 of the source region 202; therefore, when the doping ions of the first layer region 205 of the source region 202 and the third layer region 207 of the source region 202 are N-type ions, the doping ions of the second layer region 206 of the source region 202 are P-type ions; when the doping ions of the first layer region 205 of the source region 202 and the third layer region 207 of the source region 202 are P-type ions, the doping ions of the second layer region 206 of the source region 202 are N-type ions.

It should be noted that, in other embodiments, when the second layer region 206 of the source region 202 is an intrinsic undoped region, no ion doping operation is performed on the second layer region 206 of the source region 202 during the formation of the second layer region 206 of the source region 202.

In step 403, referring to fig. 5b, a gate and a gate oxide layer are formed.

When the semiconductor structure includes a plurality of transistors, that is, in the process of forming a plurality of gates and gate oxide layers, a plurality of gate isolation structures need to be formed on the semiconductor layer; the grid isolation structures are arranged at intervals with the grids, and the grid isolation structures are used for isolating the grids.

Illustratively, in some embodiments of the present invention, the method of forming the gate isolation structure may include: forming an isolation oxide layer, depositing nitride, etching a mask layer, a shallow trench isolation structure and the shallow trench isolation structure, filling oxide in a shallow trench isolation region, removing the nitride, and performing Chemical Mechanical Polishing (CMP) on the filled oxide.

It should be noted that, in the embodiments of the present invention, the gate isolation structure may be deposited by any suitable deposition process, and the material of the gate isolation structure includes any insulating material, such as silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide.

Here, for the convenience of clearly describing the formation process of the transistor, the semiconductor structure including one transistor is taken as an example for explanation, but it should be noted that the description is only for explaining the present invention and is not intended to limit the scope of the present invention.

In some embodiments of the present invention, referring to fig. 5b, before forming the gate electrode 204, a gate oxide layer 208 is formed on one side of the active pillar; the gate oxide layer 208 may be used to suppress short channel effects, among other things. In addition, the thickness of the gate oxide layer 208 is set to be an oxide layer with different thickness degrees, so that the matching problem of the semiconductor structure under different voltage requirements can be solved. Here, the thickness of the gate oxide layer 208 may be set according to actual requirements of the transistor.

Next, a gate 204 is formed on the side of the gate oxide layer 208 away from the active pillars.

Here, the material of the gate electrode 204 may include polysilicon, but is not limited thereto.

The manner of forming the gate includes, but is not limited to, PVD, CVD, ALD, and the like.

Note that the thickness of the gate oxide layer 208 is smaller than the thickness of the gate electrode 204. In practical applications, as shown in fig. 5b, the active pillars include a first end and a second end; here, the material forming the active pillars includes, but is not limited to, single crystal silicon.

In step 404, referring to fig. 5c, a drain region 203 is formed at the second end of the active pillar. Here, the drain region 203 has a first layer region 205 of the drain region 203, a second layer region 206 of the drain region 203, and a third layer region 207 of the drain region 203, which are arranged in parallel in this order; the first layer region 205 of the drain region 203 is located on a side near the channel region; a third layer region 207 of the drain region 203 is located on a side away from the channel region; the second layer region 206 of the drain region 203 is located between the first layer region 205 of the drain region 203 and the third layer region 207 of the drain region 203.

Thinning the semiconductor layer from the second surface of the semiconductor layer along a direction vertical to the semiconductor layer to expose a second end of the active column, which is far away from the first surface of the semiconductor layer; wherein the second surface is opposite the first surface;

and sequentially carrying out ion implantation with different concentrations on the second end of the active column close to the first surface of the semiconductor layer to respectively form a first layer region 205 of the drain region 203, a second layer region 206 of the drain region 203 and a third layer region 207 of the drain region 203.

In some embodiments, the forming the first layer region 205 of the drain region 203, the second layer region 206 of the drain region 203, and the third layer region 207 of the drain region 203 comprises:

the second layer region 206 of the drain region 203, the first layer region 205 of the drain region 203, and the third layer region 207 of the drain region 203 are formed through a diffusion process or an in-situ doping process.

Illustratively, first, a first layer region 205 of the drain region 203 is formed in the first end of the active pillar on a side close to the channel region 201 by a diffusion process or an in-situ doping process;

secondly, forming a second layer region 206 of the drain region 203 on one side of the first layer region 205 away from the channel region 201 through a diffusion process or an in-situ doping process;

Finally, a third layer region 207 of the drain region 203 is formed on the side of the second layer region 206 remote from the first layer region 205 by a diffusion process or an in-situ doping process.

In practical applications, after performing a diffusion process or an in-situ doping process each time, annealing the first layer region of the formed drain region 203, the second layer region of the drain region 203, and the third layer region of the drain region 203; in practical applications, after performing the diffusion process or the in-situ doping process each time, the first layer region 205 of the drain region 203, the second layer region 206 of the drain region 203, or the third layer region 207 of the drain region 203 may be subjected to an annealing process; the annealing process may be performed on the first layer region 205 of the drain region 203, the second layer region 206 of the drain region 203, and the third layer region 207 of the drain region 203 at the same time after performing three diffusion processes or in-situ doping process operations. The annealing mode can be selected according to actual requirements.

Here, the material of the second layer region 206 of the drain region 203 and the material of the semiconductor layer each include single crystal silicon or polycrystalline silicon.

It should be noted that, in the actual process operation, the source region 202 may be formed first and then the drain region 203 may be formed; the drain region 203 may be formed first and then the source region 202 may be formed; the actual process operation flow can be selected and set according to actual requirements.

Here, the thickness of the second layer region 206 of the drain region 203 is less than the thickness of the third layer region 207 of the drain region 203.

In some embodiments, the third layer 207 of the drain region 203 is a drain, which is a heavily doped region; the first layer 205 of the drain region 203 is a lightly doped region, in other words, the doping concentration of the third layer 207 of the drain region 203 is greater than that of the first layer 205 of the drain region 203; here, the first layer region 205 of the drain region 203 is greater than or equal to the doping concentration of the second layer region 206 of the drain region 203.

In some embodiments, the doping ions of the first layer region 205 of the drain region 203 and the third layer region 207 of the drain region 203 may be N-type ions or P-type ions; the doping ions of the second layer region 206 of the drain region 203 can be P-type ions or N-type ions; however, the doping type of the second layer region 206 of the drain region 203 is different from that of the first layer region 205 of the drain region 203 and the third layer region 207 of the drain region 203; therefore, when the doping ions of the first layer region 205 of the drain region 203 and the third layer region 207 of the drain region 203 are N-type ions, the doping ions of the second layer region 206 of the drain region 203 are P-type ions; when the doping ions of the first layer region 205 of the drain region 203 and the third layer region 207 of the drain region 203 are P-type ions, the doping ions of the second layer region 206 of the drain region 203 are N-type ions.

In addition, in the transistor, the doping types of the third layer region 207 of the source region 202 and the third layer region 207 of the drain region 203 are the same. Based on this, the doping types of the first layer region 205 of the source region 202, the third layer region 207 of the source region 202, the first layer region 205 of the drain region 203, and the third layer region 207 of the drain region 203 are N-type ions, and the doping types of the second layer region 206 of the source region 202 and the second layer region 206 of the drain region 203 are P-type ions, for example, for explanation.

It should be noted that in other embodiments, the second layer region 206 of the drain region 203 can also be an intrinsic undoped region, which has the same function as that of the P-type ions described above, and is not described herein again.

The manner in which the source region 202 and the drain region 203 are formed is described below in conjunction with fig. 6 a-6 c.

Forming a source region 202 at a first end of the active pillar; forming a drain region 203 at a second end of the active pillar; the method comprises the following steps:

as shown in fig. 6a, a first end of the active pillar near the first surface of the semiconductor layer is ion implanted to form a first layer region 205 of the source region 202.

As shown in fig. 6b, a first material layer 209a is formed on the first layer region 205 of the source region 202, and the first material layer 209a is ion implanted to form a second layer region 206 of the source region 202; as shown in fig. 6 c.

As shown in fig. 6d, a second material layer 209b is formed on the second layer region 206 of the source region 202, and the second material layer 209b is ion implanted to form a third layer region 207 of the source region 202, referring to fig. 6 e.

Here, the material of the second layer region 206 of the source region 202 includes silicon germanium, polysilicon, or a composite of silicon germanium and polysilicon; the material of the semiconductor layer includes single crystal silicon.

Next, a gate electrode 204 and a gate oxide layer 208 are formed on at least one side of the channel region 201; the formation process and the process of the gate electrode 204 and the gate oxide layer 208 are described above, and are not described herein again, referring to fig. 6 e.

Then, thinning the semiconductor layer from the second surface of the semiconductor layer along the direction vertical to the semiconductor layer to expose a second end of the active column away from the first surface of the semiconductor layer; wherein the second surface is opposite to the first surface.

As shown in fig. 6f, ion implantation is performed on the second end of the active pillar to form a first layer region 205 of the drain region 203;

as shown in fig. 6g, a third material layer 209c is formed on the first layer region 205 of the drain region 203, and the third material layer 209c is ion-implanted to form a second layer region 206 of the drain region 203; as shown with reference to fig. 6 h.

As shown in fig. 6i, a fourth material layer 209d is formed on the second layer region 206 of the drain region 203, and the fourth material layer 209d is ion implanted to form a third layer region 207 of the drain region 203; refer to fig. 6 j.

Here, the material of the second layer region 206 of the drain region 203 includes silicon germanium, polysilicon, or a composite structure of silicon germanium and polysilicon; the material of the semiconductor layer includes single crystal silicon.

Here, the thicknesses of the first layer region 205 of the drain region 203, the second layer region 206 of the drain region 203, and the third layer region 207 of the drain region 203 may be the same or different, and the specific dimensions thereof may be set according to actual requirements.

In other embodiments, the second layer region 206 is disposed at the drain region 203, and the third layer region 207 of the source region 202 is in direct contact with the first layer region 205 of the source region 202 when the second layer region 206 is not disposed at the source region 202, as shown in fig. 7; the total thickness of the source region 202 in the first direction may be the same as or different from the total thickness of the drain region 203 in the first direction; the specific size can be set according to actual needs.

It should be noted that, the embodiment of the present invention performs simulation processing on the transistor (T1) not provided with the second layer region 206 and the transistor (T2) provided with the second layer region 206; the simulation test result is shown in fig. 8.

In some embodiments of the present invention and referring to fig. 8, the capacitance of a transistor having the second layer region 206 disposed at the source region 202 and/or the drain region 203 is less when accumulated and inverted than a transistor having no second layer region 206 disposed at the source region 202 and/or the drain region 203.

Based on this, it can be understood that the second layer region 206 with a doping type different from that of the first layer region 205 and the third layer region 207 is additionally arranged on the source region 202 and/or the drain region 203, so that the parasitic capacitance of the transistor can be reduced, and the reliability of the transistor can be improved.

In the semiconductor structure formed by the method for manufacturing a semiconductor structure provided by the above embodiment of the present invention, since the first layer region and the second layer region are disposed on the source region and/or the drain region, and the third layer region is disposed on both the source region and the drain region, and the doping type of the second layer region is different from that of the first layer region and that of the third layer region, a capacitor can be formed between the third layer region and the first layer region and between the third layer region and the first layer region, and between the third layer region and the second layer region, and the capacitor is connected in series with the parasitic capacitance of the bit line, so that the parasitic capacitance of the transistor is reduced; the sensing margin of the transistor is further increased, and the reliability of the reading safety factor is improved; meanwhile, the forming speed of an inversion layer minority carrier between the grid and the channel region can be reduced, so that the parasitic capacitance of the grid is reduced, the sensing allowance is increased, and the reliability is improved; in addition, the junction depth of a bit line connected to a drain region or a source region can be reduced, thereby improving the response speed of the transistor.

On the other hand, the projection of the gate and the second layer area in the second direction does not completely overlap, so that the projection of the gate and the drain area or the projection of the gate and the source area in the second direction does not overlap; the overlapping area can be reduced, and the probability of grid-caused drain leakage can be reduced; the reliability of the transistor is improved.

The embodiment of the invention also provides another semiconductor structure, and fig. 9 is a schematic perspective structure diagram of another semiconductor structure provided by the embodiment of the invention; as shown in fig. 9, the semiconductor structure 60 includes:

Wherein the semiconductor body comprises:

a channel region in the semiconductor layer;

a source region;

a drain region; the source region and the drain region are two opposite ends of the channel region in a first direction respectively, and the first direction is the thickness direction of the semiconductor layer;

In some embodiments, the angle between the first direction and the second direction is 90 degrees, i.e. the first direction and the second direction are perpendicular.

In some embodiments, the doping types of the first layer region and the second layer region are both N-type doping;

the layer type of the second layer region is P-type doping.

In some embodiments, the doping types of the first layer region and the second layer region are both N-type doping or P-type doping, and the second layer region is an intrinsic non-doping region.

In some embodiments, the doping concentration of the third-layer regions is greater than the doping concentration of the first-layer regions; the doping concentration of the first layer region is greater than or equal to the doping concentration of the second layer region.

In some embodiments, one of the third layer regions of the source and drain regions of the transistor is coupled to the memory cell in a respective memory cell.

In some embodiments, the other of the third layer region of the source region and the drain region of the transistor is coupled to a respective bit line.

In some embodiments, the semiconductor structures provided by embodiments of the present invention include various types of memory. For example, NAND Flash memory (Flash), Nor Flash memory, static random access memory, dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory. In some embodiments, the semiconductor structure comprises a dynamic random access memory, the memory cell comprises a storage capacitor;

In some embodiments of the present invention, the storage capacitor may take on a variety of configurations. In some embodiments, the storage capacitor comprises a cup, cylinder, or pillar capacitor.

Illustratively, the storage capacitor may include a CUP capacitor CUP, a cylinder capacitor CYL, and a pillar capacitor PIL. The CUP capacitor CUP, the cylinder capacitor CYL and the pillar capacitor PIL each include a bottom electrode, a top electrode and a dielectric layer between the bottom electrode and the top electrode.

It should be noted that, a bottom electrode is connected to the source region 202 of a transistor in the semiconductor structure, and a top electrode of the CUP-shaped capacitor CUP is grounded, and the CUP-shaped capacitor CUP is used for storing written data.

In the case where the areas of the bottom electrodes in the CUP-shaped capacitor CUP, the cylindrical capacitor CYL, and the pillar-shaped PIL are equal to each other, the area of the top electrode in the cylindrical capacitor CYL is the largest, and the area of the top electrode in the cylindrical capacitor CYL and the pillar-shaped PIL is the second largest. Based on this, in some embodiments of the present invention, the cylindrical capacitor CYL may be used as a storage unit of the memory, which is beneficial to the integration level of the extremely high memory.

In some embodiments, the semiconductor structure comprises a resistive random access memory, and the memory cell comprises an adjustable resistor connected between the bit line and a source region 202 of a transistor in the semiconductor structure; alternatively, the adjustable resistor is connected between the bit line and the drain region 203 of a transistor in the semiconductor structure, and the adjustable resistor is used for adjusting the state of stored data through the bit line voltage provided by the bit line.

In the embodiments of the present invention, some common memories are listed by way of example only, and the scope of protection of the present invention is not limited thereto, and any memory including the semiconductor structure provided by the embodiments of the present invention falls within the scope of protection of the present invention.

For technical features not disclosed in the embodiments of the present invention in detail, please refer to the above embodiments for understanding, and details are not repeated herein.

In some embodiments, the semiconductor structure further comprises: a resistance;

the resistor is connected between the bit line and the third layer region of the source region of the transistor, or between the bit line and the third layer region of the drain region of the transistor, and the resistor is used for adjusting the state of data stored in the memory array through the bit line voltage provided by the bit line.

In the several embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.

The features disclosed in the several method or apparatus embodiments provided by the present invention may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A semiconductor structure, comprising: at least one transistor, the transistor comprising:

a channel region in the semiconductor layer;

a gate at least on one side of the channel region;

a source region at a first end of the channel region;

2. The semiconductor structure of claim 1, wherein the doping types of the first layer region and the third layer region are both N-type doping;

the doping type of the second layer region is P-type doping.

3. The semiconductor structure of claim 1,

the maximum doping concentration of the third layer region is greater than that of the first layer region; the maximum doping concentration of the first layer region is greater than or equal to the maximum doping concentration of the second layer region.

4. The semiconductor structure of claim 1, wherein a projection of the gate in a second direction does not completely overlap a projection of the second layer region in the second direction; the second direction is perpendicular to the first direction and is directed toward the channel region by the gate.

5. The semiconductor structure of claim 4, wherein a projection of the gate in a second direction does not overlap a projection of the second layer region in the second direction.

6. The semiconductor structure of claim 1, wherein the material of the second layer region and the material of the semiconductor layer each comprise single crystal silicon or polycrystalline silicon.

7. The semiconductor structure of claim 1, wherein a material of the second layer region comprises silicon germanium, polysilicon, or a composite of silicon germanium and polysilicon; the material of the semiconductor layer includes single crystal silicon.

8. The semiconductor structure of claim 1, wherein the at least one transistor comprises a first transistor and a second transistor disposed side-by-side and separated by an insulating layer;

9. The semiconductor structure of claim 1, wherein the type of the transistor comprises one of:

a pillar-type gate transistor;

a semi-wrap around gate transistor;

a fully wrap around gate transistor.

10. A semiconductor structure, comprising:

wherein the semiconductor body comprises:

a channel region in the semiconductor layer;

a source region at a first end of the channel region;

11. The semiconductor structure of claim 10, wherein the doping types of the third layer region and the first layer region are both N-type doping;

the doping type of the second layer region is P-type doping.

12. The semiconductor structure of claim 10,

13. The semiconductor structure of claim 10, wherein one of the source region and the drain region of the transistor is coupled to the memory cell in a respective memory cell.

14. The semiconductor structure of claim 13, wherein the other of the source region and the drain region of the transistor is coupled to a respective bit line.

15. The semiconductor structure of claim 10, wherein the semiconductor structure comprises: a dynamic random access memory, a ferroelectric memory, a phase change memory, a magneto-resistive memory, or a resistive memory.

16. The semiconductor structure of claim 15, wherein the semiconductor structure comprises a dynamic random access memory, the memory cell comprises a storage capacitor;

17. A method for fabricating a semiconductor structure is provided,

the manufacturing method of the transistor comprises the following steps:

providing a semiconductor layer having at least one active pillar therein;

forming a source region at a first end of the active pillar;

forming a gate on at least one side of the active pillar;

18. The method of fabricating the semiconductor structure of claim 17, wherein forming the second layer region comprises:

19. The method of claim 18, wherein the material of the second layer region is the same as the material of the semiconductor layer;

20. The method of fabricating a semiconductor structure according to claim 18, wherein a material of the second layer region is different from a material of the semiconductor layer;

and forming a fourth material layer on the second layer area of the drain region, and performing ion implantation on the fourth material layer to form a third layer area of the drain region.