WO2024130961A1 - Semiconductor device, fabrication method therefor and electronic apparatus - Google Patents

Abstract

A semiconductor device, a fabrication method therefor, and an electronic device. The fabrication method for the semiconductor device comprises: forming a stacked structure comprising a sacrificial layer and a conductive layer which are alternately arranged; forming a via hole penetrating through the stacked structure, the via hole comprising a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, the orthographic projection of the first sub-holes falling within the orthographic projection of the second sub-holes on a plane parallel to a substrate; forming a semiconductor layer, a gate insulating layer and a gate electrode in the via hole, wherein a gate electrode of a transistor of different layers is a part of a word line; etching to remove the sacrificial layer to expose the semiconductor layer located in the first sub-holes; and etching to remove the semiconductor layer located in the first sub-holes.

Description

Semiconductor device and manufacturing method thereof, and electronic device

This application claims priority to a Chinese patent application filed with the Chinese Patent Office on December 22, 2022, with application number 202211659232.9 and invention name “A 3D memory, a method for preparing the same, and an electronic device”, the contents of which should be understood to be incorporated into this application by reference.

Technical Field

The embodiments of the present disclosure relate to, but are not limited to, the field of device design and manufacturing of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device.

Background technique

Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

Taking DRAM as an example, the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

In order to reduce the cost of products as much as possible, people hope to make as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products.

Summary of the invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of memory cells, word lines, and bit lines stacked in a direction perpendicular to a substrate, wherein the memory cells comprise a transistor, wherein the transistor comprises a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode. The method for manufacturing the semiconductor device comprises:

Providing a substrate, on which a sacrificial layer film and a conductive film are alternately deposited in sequence, and patterned to form a plurality of stacked structures, each of which comprises a stack of alternately arranged sacrificial layers and conductive layers, wherein the conductive layer comprises a preset electrode pattern; the preset electrode pattern comprises the bit line to be formed and the first electrode and the second electrode of the transistor;

A via hole is formed in a direction perpendicular to the substrate and penetrates through each sacrificial layer and each conductive layer of the stacked structure at the same time, the sidewall of the via hole exposes each conductive layer and the sacrificial layer, and the via hole enables the preset electrode pattern of the conductive layer of each layer to form at least one pair of first and second electrodes separated from each other; different areas of the via hole include a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, and on a plane parallel to the substrate, the orthographic projection of the first sub-hole falls within the orthographic projection of the second sub-hole;

A semiconductor film and a gate insulating film are sequentially deposited on the sidewalls of the via holes to form a semiconductor layer and a gate insulating layer of a multilayer transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode, and a channel between the first electrode and the second electrode in the same transistor is a horizontal channel; a gate electrode and a word line of each transistor are formed by depositing and filling the via holes in the via holes, and the gate electrodes of the transistors of different layers are part of the word line;

The sacrificial layer is removed by etching to expose the semiconductor layer in the first sub-hole, and the semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors at different layers.

In some embodiments, the patterning to form a plurality of stacked structures comprises:

Patterning the sacrificial layer film and the conductive film by dry etching, removing the sacrificial layer film and the conductive film located in a preset isolation area to form a stack of the alternating sacrificial layers and the conductive layers; the preset isolation area is complementary to the pattern of the preset electrode pattern;

A first insulating film is deposited in the preset isolation region to form a first insulating layer, wherein the first insulating film is made of a different material from that of the sacrificial layer film.

In some embodiments, after the patterning forms a plurality of stacked structures, before forming a via hole penetrating the stacked structures in a direction perpendicular to the substrate, the method further comprises:

Dry etching is used to remove the first insulating layer located in the preset capacitor region to expose the end face and side face of each sacrificial layer, and wet etching is used to remove the exposed sacrificial layer laterally to expose the end face of the first electrode of each layer of the transistor and the side wall whose distance from the end face is less than or equal to a set distance;

A second insulating film and a conductive material are sequentially deposited in the preset capacitor region to form a second insulating layer and a second electrode of the capacitor, wherein the second insulating layer covers the exposed region of the first electrode, and the second electrode wraps the exposed region of the first electrode and is insulated from the first electrode by the second insulating layer.

In some embodiments, forming a via hole penetrating the stacked structure in a direction perpendicular to the substrate comprises:

An initial via hole penetrating the stacked structure in a direction perpendicular to the substrate is formed by dry etching, and the conductive layer is laterally etched by wet etching to form the second sub-hole, wherein the first electrode and the second electrode in the conductive layer are disconnected by the second sub-hole.

In some embodiments, the sacrificial layer thin film includes polysilicon or silicon oxide.

In some embodiments, the first insulating film includes silicon nitride or aluminum oxide.

In some embodiments, after etching away the semiconductor layer in the first sub-hole, the method further includes: etching away at least a portion of the gate insulating layer in the first sub-hole.

In some embodiments, the bit line and the second electrode are connected.

In some embodiments, the etching and removing the sacrificial layer to expose the semiconductor layer in the first sub-hole, and the etching and removing the semiconductor layer in the first sub-hole includes:

The entire sacrificial layer is removed by wet etching to expose the semiconductor layer in the first sub-hole, and the semiconductor layer in the first sub-hole is removed by wet etching.

In some embodiments, before the etching removes the sacrificial layer, the method further comprises:

A portion of the first insulating layer close to one side of the capacitor is dry-etched to expose the sacrificial layer without exposing the semiconductor layer.

In some embodiments, the method further includes etching to remove the remaining first insulating layer, and depositing a third insulating film to form a third insulating layer filling between the memory cells.

An embodiment of the present disclosure provides a semiconductor device, which is manufactured using the method for manufacturing a semiconductor device described in any of the above embodiments.

In some embodiments, the semiconductor device further includes: an insulating layer filling the connections between the memory cells to form an integrated structure.

In some embodiments, a thickness of the gate insulating layer in the first sub-hole is smaller than a thickness of the gate insulating layer in the second sub-hole.

The embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described above or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments.

Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description and the drawings.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation on the technical solution.

FIG1A is a schematic cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to a substrate;

FIG1B is a schematic cross-sectional view of a semiconductor device along the aa′ direction provided by an exemplary embodiment;

FIG2 is a schematic cross-sectional view of a stacked structure provided by an exemplary embodiment;

3A is a cross-sectional view along a direction parallel to a substrate after a conductive layer pattern is formed, provided by an exemplary embodiment;

FIG3B is a cross-sectional view along the bb' direction after forming a conductive layer pattern provided by an exemplary embodiment;

FIG4A is a cross-sectional view along a direction parallel to the substrate after a preset capacitance region is opened, provided by an exemplary embodiment;

FIG4B is a cross-sectional view along the aa′ direction after the preset capacitance area is opened provided by an exemplary embodiment;

5A is a cross-sectional view along a direction parallel to the substrate after forming a second pole provided by an exemplary embodiment;

FIG5B is a cross-sectional view along the aa' direction after forming the second pole provided by an exemplary embodiment;

FIG5C is a cross-sectional view along the bb' direction after forming the second pole provided by an exemplary embodiment;

FIG6A is a cross-sectional view along a direction parallel to the substrate after forming a via hole provided by an exemplary embodiment;

FIG6B is a cross-sectional view along the aa' direction after forming a via hole provided by an exemplary embodiment;

FIG6C is a cross-sectional view along the bb' direction after forming a via hole provided by an exemplary embodiment;

FIG. 7A is a cross-sectional view of an enlarged via hole along a direction parallel to the substrate provided by an exemplary embodiment;

FIG. 7B is a cross-sectional view along the aa′ direction after the via hole is enlarged according to an exemplary embodiment;

FIG7C is a cross-sectional view along the bb' direction after the via hole is enlarged provided by an exemplary embodiment;

8A is a cross-sectional view along a direction parallel to the substrate after a gate electrode is formed, provided by an exemplary embodiment;

FIG8B is a cross-sectional view along the aa′ direction after forming a gate electrode provided by an exemplary embodiment;

FIG8C is a cross-sectional view along the bb' direction after forming a gate electrode provided by an exemplary embodiment;

FIG9A is a cross-sectional view along a direction parallel to the substrate after the sacrificial layer is removed according to an exemplary embodiment;

FIG9B is a cross-sectional view along the aa' direction after the sacrificial layer is removed provided by an exemplary embodiment;

FIG9C is a cross-sectional view along the bb' direction after removing the sacrificial layer provided by an exemplary embodiment;

FIG10A is a cross-sectional view along a direction parallel to the substrate after etching a semiconductor layer provided by an exemplary embodiment;

FIG10B is a cross-sectional view along the aa′ direction after etching the semiconductor layer provided by an exemplary embodiment;

FIG10C is a cross-sectional view along the bb' direction after etching the semiconductor layer provided by an exemplary embodiment;

11A is a cross-sectional view along a direction parallel to the substrate after forming a third insulating layer provided by an exemplary embodiment;

FIG11B is a cross-sectional view along the aa' direction after forming a third insulating layer provided by an exemplary embodiment;

11C is a cross-sectional view along the bb' direction after forming a third insulating layer provided by an exemplary embodiment;

FIG. 12 is a flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment.

Detailed ways

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a physical connection, or an electrical signal connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, among the three terminals of the above-mentioned transistor, the two electrodes other than the gate electrode are the first electrode and the second electrode. The first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In the present disclosure, "connected" or "electrically connected" includes the case where the components are connected together through an element having some electrical function. "An element having some electrical function" means any component that can be connected. There is no particular limitation on the transmission and reception of electrical signals between elements. Examples of "elements having some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

The phrase “the orthographic projection of B is within the range of the orthographic projection of A” in the present disclosure means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A.

With the development of the stacked structure of 3D memory arrays, various problems will be encountered; as the number of stacked layers increases, the array becomes larger, and the unit devices become closer, the presence of parasitic MOS tubes between different layers will have a great impact on the retention of capacitor storage charge and the overall stability of the device. Therefore, in the research and development of 3D DRAM devices, while overcoming the complex process structure, it is necessary to fully consider the optimization or even elimination of some parasitic MOS tubes. In the disclosed embodiment, the parasitic MOS tube can be eliminated by etching away the semiconductor layer between the layers.

Fig. 1A is a schematic cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to a substrate. Fig. 1B is a schematic cross-sectional view of a semiconductor device provided by an exemplary embodiment along an aa' direction.

The semiconductor device may be a transistor, or a memory cell including a transistor, or a memory cell array including a memory cell, or a 3D stacked structure including a memory cell array, or a memory including a transistor or a memory cell array, etc.

As shown in FIG. 1A and FIG. 1B , the semiconductor device provided in this embodiment may include: a plurality of memory cells stacked in a direction perpendicular to a substrate 1, and a word line 40, wherein the word line 40 extends in a direction perpendicular to the substrate 1 and passes through the memory cells in different layers;

The memory cell may include: a transistor, which may include a first electrode 51, a second electrode 52, a gate electrode 25 extending in a direction perpendicular to the substrate 1, and a semiconductor layer 23 surrounding the gate electrode 25 and insulated from the gate electrode 25; wherein the channel between the first electrode 51 and the second electrode 52 may be a horizontal channel; the semiconductor layers 23 of the transistors of the memory cells of different layers are spaced apart in a direction perpendicular to the substrate 1; and the gate electrode 25 is connected to the word line 40.

In the semiconductor device provided by this embodiment, the semiconductor layers of transistors in different layers are arranged separately, which can eliminate parasitic MOS tubes between layers and improve the stability of the device.

In an exemplary embodiment, the storage unit may further include a capacitor, and the capacitor may include a first pole 41 and a second pole 42 , wherein the first pole 41 is connected to the first electrode 51 .

A horizontal channel is a channel in which the carrier transmission direction is generally lateral or horizontal, relative to a vertical transistor.

In an exemplary embodiment, the first pole 41 and the first electrode 51 may be of an integrated design or of a separate electrically connected design.

In an exemplary embodiment, the transistor may further include a gate insulating layer 24 surrounding the gate electrode 25 .

In an exemplary embodiment, the semiconductor layer 23 may be a fully surrounding type, and fully surrounds the side wall of the gate electrode 25, that is, the cross section of the semiconductor layer 23 along the direction parallel to the substrate is a closed loop. Exemplarily, the semiconductor layer 23 is annular, and the annular shape is adapted to the outer contour of the cross section of the gate electrode 25. Exemplarily, the cross section of the gate electrode 25 is, for example, a circular, elliptical, square, or other structure.

In an exemplary embodiment, along a direction perpendicular to the substrate 1, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate.

In an exemplary embodiment, the semiconductor layers 23 disposed at intervals are disconnected from each other, and the gate insulating layer 24 is exposed.

In an exemplary embodiment, the gate electrode 25 of transistors of different layers may be a part of the word line 40. It is understandable that before and after the word line is formed, there is no need to make a separate gate, and after the word line is made, a part of the word line acts as a gate electrode. The local morphology of the word line is not limited here, and the word line as a whole extends in a direction perpendicular to the substrate. Locally, corresponding to each transistor, the gate electrode of this area may extend in the horizontal direction and the vertical direction, but the semiconductor layer is formed on the side wall of the word line, and the area wrapped with the semiconductor layer in the side wall of the word line may be the main surface of the film layer including an extension in a direction perpendicular to the substrate, or in addition to the vertical extension area, it also includes an area extending in the horizontal direction.

In an exemplary embodiment, as shown in FIG1A , the memory cells in the same layer form an array (referred to as a memory cell array) distributed along the first direction X and the second direction Y, respectively. Each layer of the memory cell array may further include: a bit line 30, and the bit line 30 is connected to the second electrode 52 of the transistor in the same column in a layer. FIG1A shows that each layer includes three rows and two columns of memory cells, but the embodiments of the present disclosure are not limited thereto, and each layer may include memory cells of other numbers of rows and columns, for example, may include only one memory cell.

In an exemplary embodiment, the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30 .

In an exemplary embodiment, the second electrode 52 of the transistor may be a part of the bit line 30 connected to the second electrode 52. For example, the bit line 30 is a straight line, and the sidewall of the straight line is connected to the semiconductor layer 23, or the bit line 30 has an integrally designed branch, and the branch is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as being approximately perpendicular.

The branches may be a plurality of branches on one sidewall of the bit line 30 , or a plurality of branches on both sidewalls at the same time, and each branch may form a transistor or a memory cell.

In an exemplary embodiment, the bit line 30 may extend along the second direction Y.

In an exemplary embodiment, the first electrode 51 may extend along a first direction X.

In an exemplary embodiment, the first pole 41 may extend along the first direction X, and the second pole 42 may wrap an end surface of the first pole 41 and a side wall whose distance from the end surface is less than or equal to a preset distance.

In an exemplary embodiment, the second poles 42 of the capacitors in the same column of different layers can be connected as an integrated structure as a common capacitor electrode. As shown in Figures 1A and 1B, the second poles 42 of the capacitors in the first column of different layers are connected as an integrated structure. The second poles 42 of the capacitors in the second column of different layers are connected as an integrated structure, that is, the capacitors in the same column of different layers share the same electrode as the second pole 42.

In an exemplary embodiment, the capacitor may further include a second insulating layer 13 disposed between the first electrode 41 and the second electrode 42. The second insulating layer 13 serves as a dielectric layer between the first electrode 41 and the second electrode 42.

The above embodiments are described with reference to a 1T1C structure, but the embodiments of the present disclosure are not limited thereto, and the transistors may be applied to other structures, such as a 2T0C storage structure, including the design of the above-mentioned stacked transistors, and the like.

The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

In this embodiment, each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.

In an exemplary embodiment, a process for manufacturing a semiconductor device may include:

S101) A sacrificial layer film 9 and a conductive film 11 are alternately deposited on a substrate 1 in sequence to form a stacked structure, as shown in FIG. 2 .

In one exemplary embodiment, plasma enhanced chemical vapor deposition (Plasma The sacrificial layer film 9 and the conductive film 11 are deposited by a PECVD (Enhanced Chemical Vapor Deposition) method.

As used herein, the term "substrate" means and includes a base material or structure on which a material such as a vertical field effect transistor is formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

In an exemplary embodiment, the substrate 1 may be a semiconductor substrate, such as a silicon substrate.

In an exemplary embodiment, the sacrificial film layer 9 may include but is not limited to a film layer having a relatively large etching selectivity with the conductive film 11 , such as polysilicon.

In an exemplary embodiment, the conductive film 11 may include but is not limited to a material having a higher etching selectivity ratio with the sacrificial layer film 9, such as a multilayer structure of titanium nitride (TiN)/tungsten (W), or may be other metals, alloys, metal nitrides, metal oxides, metal carbides, etc.

The stacked structure shown in FIG. 2 includes four layers of sacrificial film layers 9 and three layers of conductive film layers 11 , which is only an example. In other embodiments, the stacked structure may include more or fewer layers of sacrificial film layers 9 and conductive film layers 11 that are alternately arranged.

S102) Patterning the stacked structure to form a sacrificial layer 10 and a conductive layer 12, wherein the conductive layer 12 may include a preset electrode pattern and a bit line 30, wherein the preset electrode pattern may include a plurality of first sub-divisions 21 and a plurality of second sub-divisions 22, wherein the bit line 30 connects the first sub-division 21 and the second sub-division 22, wherein the first sub-division 21 may extend along a first direction X, wherein the second sub-division 22 may extend along a first direction X, wherein the bit line 30 may extend along a second direction Y, wherein the first sub-division 21 subsequently forms a first electrode 51 and a second electrode 52 of a transistor, wherein the second sub-division 22 subsequently forms a first electrode 51 and a second electrode 52 of another adjacent transistor. The sacrificial layer film 9 and the conductive film 11 located in the preset isolation region may be etched away to form the sacrificial layer 10 and the conductive layer 12. It can be understood that the patterns of the preset isolation region and the conductive layer 12 are complementary.

A first insulating film is filled in the preset isolation area to form a first insulating layer 2 to isolate different devices, as shown in Figures 3A and 3B, wherein Figure 3A is a cross-sectional view parallel to the direction of the substrate 1 (a cross-sectional view of the area where the conductive layer 12 is located, and subsequent cross-sectional views parallel to the direction of the substrate 1 are all cross-sectional views of the area where the conductive layer 12 is located, which will not be repeated), and Figure 3B is a cross-sectional view along the bb' direction in Figure 3A.

The first sub-portions 21 of adjacent conductive layers 12 are isolated from each other by a sacrificial layer 10 , and in the same layer, two adjacent first sub-portions 21 are isolated from each other by a first insulating layer 2 .

In an exemplary embodiment, the stacked structure may be etched by a dry etching method to form the conductive layer 12 and the isolation layer between the conductive layers 12 .

In an exemplary implementation, the first insulating film may include but is not limited to silicon nitride (SiN). The first insulating layer 2 and the sacrificial layer 10 may be made of different materials and have a certain etching selectivity to ensure that when the sacrificial layer 10 is subsequently etched, the semiconductor layer wrapped by the sacrificial layer 10 is not affected.

S103) opening the preset capacitance area 100;

The opening of the preset capacitance region 100 may include:

Using dry etching to remove the first insulating layer 2 located in the preset capacitance region 100, exposing the end surface and side wall of the first sub-portion 21 away from the bit line 30 (including the end surface of the first sub-portion 21 away from the bit line 30 and the side surface of the first sub-portion 21 located in the preset capacitance region 100 that is perpendicular to the substrate 1, that is, the end surface of the first electrode 51 and the side wall whose distance from the end surface is less than or equal to the set distance), and exposing the end surface and side wall of the second sub-portion 22 away from the bit line 30 (including the end surface of the second sub-portion 22 and the side surface of the second sub-portion 22 located in the preset capacitance region 100 that is perpendicular to the substrate 1);

The sacrificial layer 10 located in the preset capacitor area 100 in the stacked structure is laterally etched using wet etching to expose the side of the first sub-portion 21 located in the preset capacitor area 100 parallel to the substrate 1, and to expose the side of the second sub-portion 22 located in the preset capacitor area 100 parallel to the substrate 1, as shown in Figures 4A and 4B, wherein Figure 4A is a cross-sectional view parallel to the direction of the substrate 1 (a cross-sectional view of the area where the conductive layer 12 is located), and Figure 4B is a cross-sectional view along the aa’ direction in Figure 4A, wherein the aa’ direction can be parallel to the extension direction of the first sub-portion 21.

S104) A second insulating film and a conductor material are sequentially deposited on the preset capacitance region 100 to form a second insulating layer 13 and a second electrode 42, respectively. The second insulating layer 13 covers the exposed region of the first sub-portion 21, that is, the second insulating layer 13 covers the exposed region of the first sub-portion 21, that is, the end surface and part of the side wall of the first sub-portion 21 away from the bit line 30, and the second electrode 42 wraps the exposed region of the first electrode 51 and is insulated from the first electrode 51 by the second insulating layer 13. As shown in Figures 5A, 5B and 5C, Figure 5A is a cross-sectional view parallel to the direction of the substrate 1, Figure 5B is a cross-sectional view along the aa' direction in Figure 5A, and Figure 5C is a cross-sectional view along the bb' direction in Figure 5A.

The second insulating layer 13 serves as a medium between the capacitor electrodes, the second electrode 42 serves as one electrode of the capacitor, and the first sub-portion 21 or the second sub-portion 22 serves as the other electrode of the capacitor, namely, the first electrode 41 .

In an exemplary embodiment, the second insulating film and the conductor material can be deposited by atomic layer deposition (ALD).

In an exemplary embodiment, the second insulating film may be a dielectric layer, such as a Low-K material, such as silicon oxide. Or it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), High-K materials such as hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).

In an exemplary embodiment, the conductor material includes but is not limited to at least one of the following or a combination thereof:

Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide ITO, indium-doped zinc oxide IZO, indium oxide InO, aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

In an exemplary embodiment, before depositing the second insulating film, TiN or the like may be deposited in the preset capacitor region 100, and together with a portion of the first sub-portion 21 or the second sub-portion 22, serve as the first electrode 41 of the capacitor, that is, an adhesive film layer such as TiN is provided between the first electrode 51 and the second insulating layer 13 to enhance the adhesion between the first electrode 51 and the second insulating layer 13. The adhesive film layer covers the exposed area of the first electrode 51, and the adhesive film layers attached to the first electrodes 51 of different layers are disconnected, that is, after depositing the adhesive film layer, before depositing the second insulating film, the adhesive film layer may be etched to disconnect the adhesive film layers attached to the first electrodes 51 of different layers.

S105) forming a plurality of initial via holes K0;

After completing the above-mentioned capacitor production, a via hole penetrating the entire stacked structure is then produced. The forming of multiple initial via holes K0 may include: etching the stacked structure by dry etching to form multiple initial via holes K0 penetrating the multiple conductive layers 12, the sidewalls of the initial via holes K0 expose each of the conductive layers 12, and the aperture sizes of the initial via holes K0 in different layers are basically the same, and the initial via holes K0 do not disconnect the conductive layer 12, and all areas of the conductive layer 12 remain connected. Wherein, the first sub-section 21 and the second sub-section 22 are both provided with the via hole K0, as shown in Figures 6A, 6B and 6C, wherein Figure 6A is a cross-sectional view parallel to the direction of the substrate 1, Figure 6B is a cross-sectional view along the aa' direction in Figure 6A, and Figure 6C is a cross-sectional view along the bb' direction in Figure 6A. The bb' direction may be perpendicular to the aa' direction. The initial via hole K0 may extend in a direction perpendicular to the substrate 1. The initial via hole K0 includes a first sub-hole K11 located in the sacrificial layer 10 and a second initial sub-hole K12 located in the conductive layer 12 .

In an exemplary embodiment, when the stacked structure is dry-etched, a high aspect ratio etching (HAR ET) method is adopted for etching, wherein the aspect ratio (Aspect ratio) is, for example, >6:1.

In an exemplary embodiment, the orthographic projection of the initial via hole K0 on a plane parallel to the substrate 1 may be a circle or an ellipse, but is not limited thereto, and may be a square, a hexagon, or the like.

In an exemplary embodiment, the orthographic projection of the initial via K0 on a plane parallel to the substrate 1 may be located within the orthographic projection of the conductive layer 12. For example, on a plane parallel to the substrate 1, the orthographic projection of the initial via K0 penetrating the first sub-portion 21 is located within the orthographic projection of the first sub-portion 21, and the orthographic projection of the initial via K0 penetrating the second sub-portion 22 is located within the orthographic projection of the second sub-portion 22. It can be understood that the initial via K0 does not disconnect the conductive layer 12, and the conductive layer 12 is not divided into unconnected areas by the initial via K0.

S106) etching the conductive layer 12 in a direction away from the initial via hole K0, which can be understood as lateral etching, so as to expand the second initial sub-hole K12 of the initial via hole K0 located in the conductive layer 12 in a direction away from the initial via hole K0 to form a second sub-hole K12', and the sacrificial layer 10 is hardly affected by the etching, so that on a plane parallel to the substrate 1, the orthographic projection of the first sub-hole K11 located in the sacrificial layer 10 falls within the orthographic projection of the second sub-hole K12' located in the conductive layer 12, and the conductive layer 12 forms a first electrode 51 and a second electrode 52 separated from each other; as shown in Figures 7A, 7B and 7C, wherein Figure 7A is a cross-sectional view parallel to the direction of the substrate 1, Figure 7B is a cross-sectional view along the aa' direction in Figure 7A, and Figure 7C is a cross-sectional view along the bb' direction in Figure 7A. A plurality of the first sub-holes K11 and a plurality of the second sub-holes K12' constitute a via K1, and the via K1 forms a plurality of dumbbell-shaped structures, such as forming a plurality of two types of holes with different aperture sizes. The aperture of the second sub-hole K12' located in the conductive layer 12 is larger than the aperture of the first sub-hole K11 located in the sacrificial layer 10, and the first sub-hole K11 located in the sacrificial layer 10 does not disconnect the sacrificial layer 10, and the second sub-hole K12' located in the conductive layer 12 exposes the first insulating layer 2. In an exemplary embodiment, wet etching can be used to select an acid solution with a high etching selectivity ratio for the sacrificial layer 10 and the first insulating layer 2 and the conductive layer 12, and the conductive layer 12 is laterally etched to a preset thickness L in a direction away from the initial via K0. Due to the high etching selectivity, the sacrificial layer 10 and the first insulating layer 2 are almost not etched. At this time, the first insulating layer 2 acts as an etching barrier layer, which can control the morphology of the via, ensure a deeper etching depth in the channel length direction, and a relatively small aperture in the vertical channel length direction. Take the case where the cross section of the via K1 parallel to the substrate 1 is circular. At this time, the diameter of the via K1 located in the conductive layer 12 is D, the diameter of the via K1 located in the sacrificial layer 10 is d, and D=d+2*L. In an exemplary embodiment, D is, for example, 80nm to 110nm, d is, for example, 50nm±10%, and L is, for example, 15nm to 30nm, for example, D can be 80nm, L can be 15nm, or D is 90nm, L is 20nm, or D is 100nm, L is 25nm, or D is 110nm, L is 30nm. If the cross section of the via K1 parallel to the substrate 1 is not circular, the above diameter can be the minimum size or the average diameter of multiple positions.

S107) forming a semiconductor layer 23, a gate insulating layer 24 and a gate electrode 25.

The forming of the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 25 may include:

A semiconductor film and a gate insulating film are sequentially deposited on the side wall of the via hole K1 to form a semiconductor layer 23 and a gate insulating layer 24. After the semiconductor layer 23 and the gate insulating layer 24 are deposited, the size of the via hole K1 located in the parasitic MOS region 300 (the redundant semiconductor layer, the gate electrode, and the gate insulating layer formed between two adjacent layers of storage cells as the parasitic MOS tube) is larger than that of the via hole K1 located in the MOS channel region 200. The dimension of the hole K1 in the first direction X is small.

A gate electrode film is deposited in the via hole K1 to form a gate electrode 25, and the gate electrode 25 fills the via hole K1. As shown in Fig. 8A, Fig. 8B and Fig. 8C, Fig. 8A is a cross-sectional view parallel to the direction of the substrate 1, Fig. 8B is a cross-sectional view along the aa' direction in Fig. 8A, and Fig. 8C is a cross-sectional view along the bb' direction in Fig. 8A.

In an exemplary embodiment, the semiconductor film, the gate insulating film and the gate electrode film may be deposited by ALD.

In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide does not exclude compounds containing other elements, such as N, Si, etc., nor does it exclude the presence of other small amounts of doping elements.

In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10-15A, thereby improving the operating performance of the dynamic memory.

The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

In an exemplary embodiment of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. may be included. Exemplary, for example, may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

In an exemplary embodiment, the gate electrode film can be one of the following different types of materials: One or more kinds:

For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

In an exemplary embodiment, the thickness of the semiconductor layer 23 along the radial direction of the via hole K1 may be 3 nm±10%, and the thickness of the gate insulation layer 24 along the radial direction of the via hole K1 may be 10 nm±10%. This is only an example, and the thicknesses of the semiconductor layer 23 and the gate insulation layer 24 may be other values.

S108) etching and removing the sacrificial layer 10.

The sacrificial layer 10 of each region is removed by etching. The etching and removing of the sacrificial layer 10 may include: using dry etching to etch the first insulating layer 2 between two adjacent memory cells on the same bit line 30, removing the first insulating layer 2 close to the capacitor side by making a vertical through hole or groove, exposing the conductive layer 12 and the sacrificial layer 10 between the conductive layers 12, and not exposing the semiconductor layer 23. At this time, the semiconductor layer 23 at the memory cell layer is wrapped by the first insulating layer 2.

Then, an etching solution with a high etching selectivity ratio for the semiconductor layer 23 and the gate insulating layer 24 and the sacrificial layer 10 (i.e., an etching solution with a slow etching speed for the semiconductor layer 23 and the gate insulating layer 24 and a fast etching speed for the sacrificial layer 10) is used to laterally etch the sacrificial layer 10, and each sacrificial layer 10 between the conductive layers 12 is etched away. At this time, the sacrificial layer 10 in each area between the conductive layers 12 can be laterally etched through an opening vertical to the substrate, and there is no need to make a separate opening horizontally to remove the semiconductor layer 23 in the direction of the vertical channel length.

The sacrificial layer 10 between the two word lines 40 can be etched away around the via K1, as shown in Figures 9A, 9B, and 9C, wherein Figure 9A is a cross-sectional view parallel to the direction of the substrate 1, Figure 9B is a cross-sectional view along the aa' direction in Figure 9A, and Figure 9C is a cross-sectional view along the bb' direction in Figure 9A.

In an exemplary embodiment, the etching solution is, for example, an acid solution, such as nitric acid (HNO 3 ).

S109) The above step has exposed the semiconductor layer 23 in the sacrificial layer 10. The step of removing the semiconductor layer 23 in the via K1 of the sacrificial layer 10 may include: when the semiconductor layer 23 is a metal oxide, a hydrofluoric acid (HF) solution of a preset concentration may be used to etch the semiconductor layer 23 in the via K1 of the sacrificial layer 10, that is, to etch the semiconductor layer 23 in the via K1 of the parasitic MOS region 300, as shown in Figures 10A, 10B, and 10C, wherein Figure 10A is a cross-sectional view parallel to the direction of the substrate 1, Figure 10B is a cross-sectional view along the aa' direction in Figure 10A, and Figure 10C is a cross-sectional view along the bb' direction in Figure 10A.

In an exemplary embodiment, in order to ensure that the semiconductor layer 23 of the parasitic MOS is completely removed, part or all of the gate insulating layer 24 in the via hole K1 in the parasitic MOS region 300 may be etched and removed, and etching and removing the gate insulating layer 24 is conducive to eliminating the parasitic MOS tube. The solution provided in this embodiment can fully remove the semiconductor layer 23 in the via hole K1 in the parasitic MOS region 300, thereby removing the parasitic MOS tube, which is conducive to improving the stability of the device.

In this embodiment, since the semiconductor layer 23 located in the MOS channel region 200 is protected by the conductive layer 12 and the first insulating layer 2, the semiconductor layer 23 in the MOS channel region 200 will not be etched too much, and therefore, the effective length of the channel will not be greatly affected.

S110) remove the first insulating layer 2, deposit a third insulating film, form a third insulating layer 3, and realize isolation between different devices, as shown in Figures 11A, 11B, and 11C, wherein Figure 11A is a cross-sectional view parallel to the direction of the substrate 1, Figure 11B is a cross-sectional view along the aa' direction in Figure 11A, and Figure 11C is a cross-sectional view along the bb' direction in Figure 11A. The third insulating layer 3 is filled between the storage cells to isolate the storage cells. In this embodiment, the insulating layer connection between the storage cells is an integrated structure, that is, the storage cells are isolated by the third insulating layer 3 formed by one-time patterning.

When the first insulating layer 2 is a Low-K material and has little effect on the channel, step S110 may not be performed. When the first insulating layer 2 is a material that affects the channel, or has a high dielectric constant, a material with a lower dielectric constant may be used to replace the first insulating layer 2 to reduce parasitic MOS tubes between devices. For example, when the first insulating layer 2 is SiN, SiO may be used as the third insulating layer 3 to replace the first insulating layer 2.

In an exemplary embodiment, the first insulating layer 2 may be removed using dry etching or wet etching.

In an exemplary embodiment, the third insulating film may be deposited by using an ALD method.

In an exemplary embodiment, the third insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

The solution provided in this embodiment can effectively eliminate parasitic MOS tubes and increase device stability by etching away the semiconductor layer and the gate insulation layer between the layers.

FIG12 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure. In this embodiment, the semiconductor device includes a plurality of memory cells, word lines, and bit lines stacked in a direction perpendicular to a substrate, the memory cells include: a transistor, the transistor includes a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode. As shown in FIG12, the method for manufacturing the semiconductor device may include:

Step 1201, providing a substrate, alternately depositing a sacrificial layer film and a conductive film on the substrate, and patterning to form a plurality of stacked structures, wherein the plurality of stacked structures are spaced apart in a row direction, and grooves are provided between adjacent stacked structures, wherein the grooves expose the end surface of each film layer of the stacked structures;

Each of the stacked structures includes a stack of alternately arranged sacrificial layers and conductive layers, wherein the conductive layers include a preset electrode pattern, and the preset electrode pattern includes the bit line to be formed and the transistor a first electrode and a second electrode;

Step 1202, forming a via hole that simultaneously penetrates each of the sacrificial layers and each of the conductive layers of the stacked structure in a direction perpendicular to the substrate, wherein the sidewall of the via hole exposes each of the conductive layers and the sacrificial layer, and the via hole enables the preset electrode pattern of the conductive layer of each layer to form at least one pair of first electrodes and second electrodes separated from each other; different regions of the via hole include a plurality of first sub-holes respectively located in the sacrificial layers and a plurality of second sub-holes respectively located in the conductive layers, and on a plane parallel to the substrate, the orthographic projection of the first sub-hole falls within the orthographic projection of the second sub-hole;

Step 1203, sequentially depositing a semiconductor film and a gate insulating film on the sidewall of the via hole to form a plurality of semiconductor layers and a gate insulating layer of the transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode, and the channel between the first electrode and the second electrode in the same transistor is a horizontal channel; depositing and filling the via hole to form a gate electrode and the word line of each transistor; the gate electrodes of the transistors of different layers are part of the word line;

Step 1204 , etching and removing the sacrificial layer to expose the semiconductor layer in the first sub-hole, and etching and removing the semiconductor layer in the first sub-hole to disconnect the semiconductor layers of transistors in different layers.

The solution provided in this embodiment is to set a sacrificial layer between the conductive layers, and to etch the sacrificial layer to expose the semiconductor layer between the conductive layers so as to etch the semiconductor layer between the conductive layers, thereby eliminating parasitic MOS tubes between transistors in different layers and improving device performance.

In an exemplary embodiment, the channel between the first electrode and the second electrode may be a horizontal channel.

In an exemplary embodiment, the patterning to form a plurality of stacked structures may include:

Patterning the sacrificial layer film and the conductive film by dry etching, removing the sacrificial layer film and the conductive film located in a preset isolation area to form a stack of the alternating sacrificial layers and the conductive layers; the preset isolation area is complementary to the pattern of the preset electrode pattern;

A first insulating film is deposited in the preset isolation region to form a first insulating layer, wherein the first insulating film is made of a different material from that of the sacrificial layer film.

In an exemplary embodiment, after patterning to form a plurality of stacked structures, before forming a via hole penetrating the stacked structures in a direction perpendicular to the substrate, the method may further include:

Dry etching is used to remove the first insulating layer located in the preset capacitor region to expose the end face and side face of each sacrificial layer, and wet etching is used to remove the exposed sacrificial layer laterally to expose the end face of the first electrode of each layer of the transistor and the side wall whose distance from the end face is less than or equal to a set distance;

A second insulating film and a conductor material are sequentially deposited in the preset capacitor region to form a second insulating layer and a second electrode of the capacitor, wherein the second insulating layer covers the exposed region of the first electrode, and the second electrode wraps the exposed region of the first electrode and is connected to the first electrode through the second insulating layer. insulation.

In an exemplary embodiment, forming a via hole penetrating the stacked structure in a direction perpendicular to the substrate may include:

An initial via hole penetrating the stacked structure in a direction perpendicular to the substrate is formed by dry etching, and the conductive layer is laterally etched by wet etching to form the second sub-hole, wherein the first electrode and the second electrode in the conductive layer are disconnected.

In an exemplary embodiment, the sacrificial layer thin film may include polysilicon or silicon oxide.

In an exemplary embodiment, the first insulating film may include silicon nitride or aluminum oxide.

In an exemplary embodiment, after etching away the semiconductor layer in the first sub-hole, the method further includes: etching away at least a portion of the gate insulating layer in the first sub-hole. The solution provided in this embodiment can ensure that the semiconductor layer in the first sub-hole is completely etched away, and the parasitic MOS tube is eliminated as much as possible, and etching a portion of the gate insulating layer is also helpful in eliminating the parasitic MOS tube.

In an exemplary embodiment, when the semiconductor layer in the first sub-hole is etched and removed, a portion of the semiconductor layer in the second sub-hole adjacent to the first sub-hole is etched.

In an exemplary embodiment, the bit line is connected to the second electrode. Each layer of the semiconductor device may include a plurality of memory cells, and the second electrodes of the plurality of memory cells are connected to the bit line.

In an exemplary embodiment, the etching and removing the sacrificial layer to expose the semiconductor layer in the first sub-hole, and the etching and removing the semiconductor layer in the first sub-hole may include:

The entire sacrificial layer is removed by wet etching to expose the semiconductor layer in the first sub-hole, and the semiconductor layer in the first sub-hole is removed by wet etching.

In an exemplary embodiment, before the etching to remove the sacrificial layer, the method may further include:

A portion of the first insulating layer close to one side of the capacitor is dry-etched to expose the sacrificial layer without exposing the semiconductor layer.

In an exemplary embodiment, the method further includes etching to remove the remaining first insulating layer, and depositing a third insulating film to form a third insulating layer filling between the memory cells.

In this embodiment, the structure, materials, related parameters and detailed manufacturing process of each film layer can refer to the aforementioned manufacturing process embodiment, which will not be repeated here.

An embodiment of the present disclosure provides a semiconductor device, which is manufactured using the above-mentioned method for manufacturing a semiconductor device.

In an exemplary embodiment, the semiconductor device may further include: an insulating layer filling the connections between the memory cells to form an integrated structure.

In an exemplary embodiment, the thickness of the gate insulating layer in the first sub-hole may be smaller than the thickness of the gate insulating layer in the second sub-hole. The thickness of the gate insulating layer parallel to the substrate direction, i.e., the film thickness of the gate insulating layer, in this embodiment, when the gate insulating layer is deposited and formed, the thickness of the gate insulating layer located in the first sub-hole is consistent with that of the gate insulating layer located in the second sub-hole, and when the semiconductor layer located in the first sub-hole is etched, a portion of the gate insulating layer located in the first sub-hole is also etched, so the thickness of the gate insulating layer located in the first sub-hole is reduced. The thickness of the gate insulating layer located in the first sub-hole is reduced, which can eliminate the parasitic MOS tube and improve the device performance.

The present disclosure also provides an electronic device, including the semiconductor device described in the above embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted for facilitating the understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims (15)

1. A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of memory cells, word lines, and bit lines stacked in a direction perpendicular to a substrate, the memory cells comprising: a transistor, the transistor comprising a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, the method for manufacturing the semiconductor device comprising:

   Providing a substrate, on which a sacrificial layer film and a conductive film are alternately deposited in sequence, and patterned to form a plurality of stacked structures, each of which comprises a stack of alternately arranged sacrificial layers and conductive layers, wherein the conductive layer comprises a preset electrode pattern; the preset electrode pattern comprises the bit line to be formed and the first electrode and the second electrode of the transistor;

   A via hole is formed in a direction perpendicular to the substrate and penetrates through each sacrificial layer and each conductive layer of the stacked structure at the same time, the sidewall of the via hole exposes each conductive layer and the sacrificial layer, and the via hole enables the preset electrode pattern of the conductive layer of each layer to form at least one pair of first and second electrodes separated from each other; different areas of the via hole include a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, and on a plane parallel to the substrate, the orthographic projection of the first sub-hole falls within the orthographic projection of the second sub-hole;

   A semiconductor film and a gate insulating film are sequentially deposited on the sidewalls of the via holes to form a semiconductor layer and a gate insulating layer of the transistors in multiple layers, wherein the semiconductor layer is connected to the first electrode and the second electrode, and the channel between the first electrode and the second electrode in the same transistor is a horizontal channel; a via hole is deposited in the via hole to fill the via hole to form a gate electrode and the word line of each transistor; the gate electrodes of the transistors in different layers are part of the word line;

   The sacrificial layer is removed by etching to expose the semiconductor layer in the first sub-hole, and the semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors at different layers.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the patterning to form a plurality of stacked structures comprises:

   Patterning the sacrificial layer film and the conductive film by dry etching, removing the sacrificial layer film and the conductive film located in a preset isolation area to form a stack of the alternating sacrificial layers and the conductive layers; the preset isolation area is complementary to the pattern of the preset electrode pattern;

   A first insulating film is deposited in the preset isolation region to form a first insulating layer, wherein the first insulating film is made of a different material from that of the sacrificial layer film.
3. The method for manufacturing a semiconductor device according to claim 2, wherein after the patterning forms a plurality of stacked structures and before forming a via hole penetrating the stacked structures in a direction perpendicular to the substrate, the method further comprises:

   The first insulating layer in the preset capacitor region is removed by dry etching to expose the end surface and On the side, removing the exposed sacrificial layer by lateral wet etching to expose the end surface of the first electrode of each layer of the transistor and the side wall whose distance from the end surface is less than or equal to a set distance;

   A second insulating film and a conductive material are sequentially deposited in the preset capacitor region to form a second insulating layer and a second electrode of the capacitor, wherein the second insulating layer covers the exposed region of the first electrode, and the second electrode wraps the exposed region of the first electrode and is insulated from the first electrode by the second insulating layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the via hole formed in a direction perpendicular to the substrate and penetrating the stacked structure comprises:

   An initial via hole penetrating the stacked structure in a direction perpendicular to the substrate is formed by dry etching, and the conductive layer is laterally etched by wet etching to form the second sub-hole, wherein the first electrode and the second electrode in the conductive layer are disconnected by the second sub-hole.
5. The method for manufacturing a semiconductor device according to claim 2, wherein the etching and removing the sacrificial layer to expose the semiconductor layer located in the first sub-hole, and the etching and removing the semiconductor layer located in the first sub-hole comprises:

   The entire sacrificial layer is removed by wet etching to expose the semiconductor layer in the first sub-hole, and the semiconductor layer in the first sub-hole is removed by wet etching.
6. The method for manufacturing a semiconductor device according to claim 3, wherein before the etching removes the sacrificial layer, the method further comprises:

   A portion of the first insulating layer close to one side of the capacitor is dry-etched to expose the sacrificial layer without exposing the semiconductor layer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the method further comprises etching away the remaining first insulating layer, and depositing a third insulating film to form a third insulating layer filling between the memory cells.
8. The method for manufacturing a semiconductor device according to claim 1, wherein after etching away the semiconductor layer located in the first sub-hole, the method further comprises: etching away at least a portion of the gate insulating layer located in the first sub-hole.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial layer thin film comprises polysilicon or silicon oxide.
10. The method for manufacturing a semiconductor device according to claim 2, wherein the first insulating film comprises silicon nitride or aluminum oxide.
11. The method for manufacturing a semiconductor device according to claim 1, wherein the bit line and the second electrode are connected.
12. A semiconductor device is manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 11.
13. The semiconductor device according to claim 12, wherein the semiconductor device further comprises: an insulating layer filled in the connection between the memory cells to form an integrated structure.
14. The semiconductor device according to claim 12, wherein a thickness of the gate insulating layer located in the first sub-hole is smaller than a thickness of the gate insulating layer located in the second sub-hole.
15. An electronic device comprising a semiconductor device as claimed in any one of claims 12 to 14, or a semiconductor device formed by the method for manufacturing a semiconductor device as claimed in any one of claims 1 to 11.