WO2023207109A1

WO2023207109A1 - Dynamic memory and manufacturing method therefor, and storage device

Info

Publication number: WO2023207109A1
Application number: PCT/CN2022/137299
Authority: WO
Inventors: 王祥升; 王桂磊; 赵超
Original assignee: 北京超弦存储器研究院
Priority date: 2022-04-25
Filing date: 2022-12-07
Publication date: 2023-11-02
Also published as: CN116209245B; CN116209245A

Abstract

The present application provides a dynamic memory and a manufacturing method therefor, and a storage device. The dynamic memory comprises a substrate and a plurality of storage arrays arranged on the substrate in a stacked mode, the storage arrays comprise a plurality of storage units arranged in an array, and each storage unit comprises a transistor and a capacitor. Word lines of the dynamic memory are located at the gates of the transistors and are connected to the transistors, a bit line penetrates through the plurality of storage units, and the transistors in the plurality of storage units are connected by means of the bit line. By arranging the storage arrays comprising the plurality of storage units in a stacked mode, the dynamic memory having a three-dimensional structure is formed, so that the storage capacity of the dynamic memory is improved, and the structural layout of the storage units is more compact. In addition, the bit line penetrates through the plurality of storage units, and the plurality of stacked transistors can be connected by means of one bit line, such that the structure and the manufacturing process of the dynamic memory are simplified.

Description

A dynamic memory and its production method and storage device

This application requests the priority of the patent application submitted to the State Intellectual Property Office of China on April 25, 2022, with the application number 202210442185.6 and the invention title "A dynamic memory and its production method and storage device".

Technical field

The present application relates to the technical field of semiconductor devices. Specifically, the present application relates to a dynamic memory, a manufacturing method thereof, and a storage device.

Background technique

Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density. With the development of technology, DRAM memory is increasingly used in electronic devices such as servers, smartphones, and personal computers.

Contents of the invention

This application proposes a dynamic memory, a manufacturing method thereof, and a storage device.

In a first aspect, embodiments of the present application provide a dynamic memory, including a substrate and a plurality of stacked memory arrays arranged on the substrate. The memory array includes a plurality of memory cells arranged in an array. The memory cells include:

A transistor includes a semiconductor layer, the semiconductor layer includes a source electrode, a drain electrode, and a channel between the source electrode and the drain electrode, and the material of the semiconductor layer includes IGZO; the transistor also includes a gate electrode;

Capacitor, electrically connected to the transistor, the capacitor is located at the drain of the transistor;

The word line is located at the gate and is electrically connected to the transistor;

The dynamic memory also includes a bit line, which runs through the semiconductor layer of the transistors in the plurality of memory cells. The bit line is located at the source electrode, and the transistors in the plurality of memory cells are electrically connected through the bit line.

Optionally, the capacitor includes an inner electrode, a dielectric layer and an outer electrode located at the drain. The inner electrode, the dielectric layer and the outer electrode all surround the drain of the semiconductor layer. The inner electrode, the dielectric layer and the outer electrode are in a direction away from the semiconductor layer. distributed in sequence.

Optionally, the capacitors of the memory cells in two adjacent layers of memory arrays share external electrodes.

Optionally, the transistor further includes a gate insulating layer, the gate electrode and the gate insulating layer surround the semiconductor layer, and the gate insulating layer and the gate electrode are sequentially distributed in a direction away from the semiconductor layer.

Optionally, in the same layer of memory array, at least two transistors share a bit line.

Optionally, the material of the word line includes ITO; and/or the material of the bit line includes tungsten.

Optionally, the orthographic projection of the capacitor on the substrate overlaps with the orthographic projection of the drain of the transistor on the substrate.

Optionally, word lines are located between gate electrodes on the same layer.

Optionally, the orthographic projection of the bit line on the substrate is located within the orthographic projection of the source on the substrate.

Optionally, the extension direction of the word line and the extension direction of the semiconductor layer are perpendicular to each other.

Optionally, along a direction gradually away from the substrate, the lengths of the plurality of word lines in a direction parallel to the substrate gradually decrease.

Optionally, the semiconductor layer is directly connected to the capacitor contact to achieve electrical connection between the drain of the semiconductor layer and the capacitor; and/or the semiconductor layer is directly connected to the bit line contact to achieve electrical connection between the source of the semiconductor layer and the bit line.

Optionally, the transistor further includes an interlayer insulating layer, and gates of transistors located on different layers are insulated from each other through the interlayer insulating layer.

In a second aspect, an embodiment of the present application provides a storage device, including the dynamic memory in the embodiment of the present application.

In the third aspect, embodiments of the present application provide a method for making a dynamic memory, including:

provide a substrate;

A plurality of transistors are produced on one side of the substrate. The transistors include a semiconductor layer. The semiconductor layer includes a source electrode, a drain electrode and a channel between the source electrode and the drain electrode. The transistor also includes a gate electrode;

Make a word line at the gate of the transistor, and the word line is electrically connected to the transistor;

Make a capacitor at the drain of the transistor, and the capacitor is electrically connected to the transistor;

A bit line is formed at the source of the semiconductor layer, and the bit line penetrates multiple semiconductor layers, and multiple transistors are electrically connected through the bit line.

Optionally, fabricate multiple transistors on one side of the substrate, including:

A plurality of semiconductor layers are produced on one side of the substrate, and the semiconductor layers include oppositely arranged source electrodes and drain electrodes;

A gate insulating layer, a gate electrode and an interlayer insulating layer surrounding the semiconductor layer are sequentially produced. The gate insulating layer, gate electrode, interlayer insulating layer and semiconductor layer constitute a transistor.

Optionally, multiple semiconductor layers are made on one side of the substrate, including:

Multi-layer oxide films are stacked on one side of the substrate through a deposition process, and each layer of oxide film includes a sacrificial layer and a semiconductor layer that are stacked in sequence;

Etching the multi-layer sacrificial layer and the multi-layer semiconductor layer to form a plurality of semiconductor layers arranged at intervals;

Etch the portions of the sacrificial layer located at both ends of the semiconductor layer to form trenches;

Make support layers at both ends of the semiconductor layer through a deposition process, and fill the trenches with the support layers;

Remove the sacrificial layer between the semiconductor layers.

Optionally, forming a capacitor at the drain of the transistor includes: sequentially forming an inner electrode layer, a dielectric layer and an outer electrode layer surrounding the semiconductor layer at the drain of the semiconductor layer to form the capacitor.

Optionally, fabricating a word line at the gate of the transistor includes etching the word line through a modified etching process so that the word lines located at different layers are in a stepped shape.

The beneficial technical effects brought by the technical solutions provided by the embodiments of this application include:

The dynamic memory in the embodiment of the present application includes a substrate and a plurality of stacked memory arrays arranged on the substrate. The memory array includes a plurality of memory cells arranged in an array. The memory unit includes a transistor and a capacitor, the capacitor is electrically connected to the transistor, and the capacitor is located at the drain of the transistor. The dynamic memory also includes a word line and a bit line. The word line is located at the gate of the transistor and is electrically connected to the transistor. The bit line runs through the semiconductor layer of the transistor in multiple memory cells. The bit line is located at the source. The transistors are electrically connected through bit lines. By stacking storage arrays including multiple storage units, a dynamic memory with a three-dimensional structure is formed. While increasing the storage capacity of the dynamic memory, it avoids the excessive area of the dynamic memory caused by arranging the storage units on the same plane. Large size makes the structural layout of the memory unit more compact, which improves the storage density and is more conducive to device integration. On the other hand, by allowing the bit lines to penetrate the semiconductor layers of the transistors in multiple memory cells, multiple stacked transistors can be electrically connected through one bit line, thereby simplifying the structure and manufacturing process of the dynamic memory.

Advantages of embodiments of the application will be set forth in part in the description that follows, and will be apparent from the description, or may be learned through practice of the application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic top structural view of a dynamic memory provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of section AA in Figure 1;

Figure 3 is a schematic structural diagram of section BB in Figure 1;

Figure 4 is a schematic structural diagram of the section CC in Figure 3;

Figure 5 is a schematic structural diagram of the section DD in Figure 3;

Figure 6 is a schematic flowchart of a method for manufacturing a dynamic memory provided by an embodiment of the present application;

Figures 7a to 7j are schematic structural diagrams of different processes for producing dynamic memory provided by embodiments of the present application.

In the picture:

10-dynamic memory; 11-substrate; 12-storage array; 120-storage unit;

121-transistor; 123-word line; 124-bit line; 125-gate; 126-gate insulating layer; 127-capacitor; 1271-internal electrode; 1272-dielectric layer; 1273-external electrode; 128-interlayer insulating layer ;

20-oxide film; 21-sacrificial layer; 22-semiconductor layer; 23-trench; 24a-support layer; 24b-isolation layer; 25-through hole;

31-channel; 32-source; 33-drain.

Detailed ways

The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. Furthermore, detailed descriptions of known technologies are omitted if they are unnecessary to illustrate the features of the present application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and cannot be construed as limiting the present application.

Those skilled in the art will understand that, unless expressly stated otherwise, the singular forms "a", "an", "the" and "the" used herein may also include the plural form. It should be further understood that the word "comprising" used in the description of this application refers to the presence of stated features, integers, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, Integers, steps, operations, elements, components and/or groups thereof. It will be understood that when we refer to an element being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Additionally, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. As used herein, the term "and/or" includes all or any unit and all combinations of one or more of the associated listed items.

DRAM memory usually includes multiple storage cells. The storage unit in DRAM memory usually includes a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and a capacitor. Its structure is relatively simple. The capacity per unit volume is higher. The main working principle of DRAM memory is to use capacitors to store charges, and determine whether a binary bit is 1 or 0 based on the amount of charge stored in the capacitor. DRAM memory can also adopt a capacitorless design, that is, two MOS tubes, a read MOS tube and a write MOS tube, are provided in the memory unit. The gate of the read MOS tube is electrically connected to the source and drain of the write MOS tube. Therefore, no additional capacitor device is needed, further simplifying the structure of the memory.

In order to increase the storage capacity of DRAM memory, the number of memory cells needs to be increased. Inventors in the field have considered that in the existing 1T1C memory (that is, a MOS transistor and a capacitor are arranged in the memory unit), the memory unit usually adopts a planar layout. When the memory adopts a large-capacity design, the number of memory units needs to be increased. , However, increasing the number of memory cells leads to occupying a larger area, making the structure not compact enough, which is not conducive to device integration.

The dynamic memory, its manufacturing method, and the storage device provided by the embodiments of the present application are intended to solve the above technical problems of the prior art.

The dynamic memory, its manufacturing method, and the storage device provided by the embodiments of the present application will be introduced in detail below with reference to the accompanying drawings.

As shown in Figure 1, Figure 2 and Figure 3, Figure 1 is a schematic structural diagram of the dynamic memory provided by the embodiment of the present application. Figure 2 is a schematic structural diagram of the section AA in Figure 1. Figure 3 is a schematic structural diagram of the section BB in Figure 1. is a schematic structural diagram. The dynamic memory 10 in the embodiment of the present application includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11. The memory array 12 includes a plurality of memory cells 120 arranged in an array. The memory cells 120 include:

The transistor 121 includes a semiconductor layer 22. The semiconductor layer 22 includes a source electrode 32, a drain electrode 33 and a channel 31 provided between the source electrode 32 and the drain electrode 33. The material of the semiconductor layer 22 includes IGZO; the transistor 121 also includes a gate electrode. 125;

Capacitor 127 is electrically connected to transistor 121, and capacitor 127 is located at the drain 33 of transistor 121;

Word line 123 is located at gate 125, and word line 123 is electrically connected to transistor 121;

The dynamic memory 10 further includes a bit line 124 that penetrates the semiconductor layer 22 of the transistors 121 in the plurality of memory cells 120. The bit line 124 is located at the source 32, and the transistors 121 in the plurality of memory cells 120 are electrically connected through the bit line 124. .

Specifically, the material of the substrate 11 includes silicon, and a multi-layer memory array 12 is provided on the substrate 11. Each layer of the memory array 12 includes a plurality of memory cells 120 arranged in an array. It should be noted that the number of layers of the storage array 12 and the number of storage units 120 in each layer of the storage array 12 can be adjusted according to actual conditions. Each memory cell 120 includes a transistor 121 and a capacitor 127 . As shown in Figure 1, the transistor 121 includes a semiconductor layer 22. The material of the semiconductor layer 22 can be Indium Gallium Zinc Oxide (IGZO) or other metal oxides, which can be determined according to the actual situation. Sure. It should be noted that the material of the semiconductor layer 22 may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZ naOd、SixInyZnzOa、ZnxSnyOz , AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials. When the material of the semiconductor layer 22 is IGZO, multi-layer semiconductor layers 22 are produced through a deposition process during the production process of the dynamic memory 10, and the number of stacked semiconductor layers 22 can be larger, which is beneficial to improving the storage capacity of the dynamic memory 10. density. The semiconductor layer 22 includes a source electrode 32 , a drain electrode 33 , and a channel 31 provided between the source electrode 32 and the drain electrode 33 . During the fabrication process of the dynamic memory 10, after the semiconductor layer 22 is fabricated, the source electrode 32, the channel 31 and the drain electrode 33 are formed on the semiconductor layer 22 through an in-situ doping process.

The memory unit 120 includes a capacitor 127 disposed at the drain 33 of the transistor 121 . The dynamic memory 10 includes multiple word lines 123. There are multiple memory cells 120 (memory cells 120 arranged in the same direction) in each layer of the memory array 12 that share one word line 123. That is, multiple memory cells 120 in each layer of the memory array 12 share one word line 123. The transistor 121 of the memory unit 120 is electrically connected through a word line 123 (the word line 123 is connected to the gate 125 of the transistor 121). The extending direction of the word line 123 is perpendicular to the extending direction of the semiconductor layer 22. The material of the word line 123 includes indium tin oxide. (Indium tin oxide, ITO). The dynamic memory 10 also includes a plurality of bit lines 124. As shown in FIGS. 1, 2 and 3, the bit lines 124 are located at the source electrode 32 of the semiconductor layer 22, and each bit line 124 runs through the multi-layer memory array 12. The transistor 121 and the plurality of transistors 121 penetrated by the bit line 124 are electrically connected through the bit line 124 . The material of the bit line 124 includes tungsten and other materials with good conductive properties, and the details can be determined according to actual conditions.

As shown in FIG. 1 , FIG. 2 and FIG. 3 , when the dynamic memory 10 is in the writing mode, a high voltage is applied to the gate 125 of the transistor 121 through the word line 123 , between the source 32 and the drain 33 of the semiconductor layer 22 The channel 31 is turned on, so that the transistor 121 is in an on state. The data signal is transmitted to the transistor 121 through the bit line 124, and then transmitted to the capacitor 127 through the transistor 121 to write data into the memory unit 120. The level of the data signal voltage determines the amount of charge on the capacitor 127, which in turn determines whether the binary value of the written data signal is 0 or 1. When the dynamic memory 10 is in the read mode, a high voltage is applied to the gate 125 of the transistor 121 through the word line 123, so that the transistor 121 is in the on state, and the electrical signal in the capacitor 127 is transmitted to the external read and write circuit through the bit line 124 (Fig. 1 to FIG. 3 ), that is, the read-write circuit reads the data in the storage unit 120 through the bit line 124 . It should be noted that by directly connecting the semiconductor layer 22 with the capacitor 127 and the bit line 124, the drain electrode 33 of the semiconductor layer 22 and the capacitor 127 can be electrically connected, and the source electrode 32 of the semiconductor layer 22 can be electrically connected with the bit line 124. Therefore, There is no need to provide a metal electrode (source or drain) on the semiconductor layer 22 .

In the embodiment of the present application, the dynamic memory 10 with a three-dimensional structure is formed by stacking the storage array 12 including a plurality of storage units 120, which improves the storage capacity of the dynamic memory 10 while avoiding the need to store the storage units 120. When arranged on the same plane, the area of the dynamic memory 10 is too large, thus making the structural layout of the memory unit 120 more compact, which improves storage density and is more conducive to device integration. On the other hand, by allowing the bit line 124 to penetrate the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120, the plurality of stacked transistors 121 can be electrically connected through one bit line 124, that is, the plurality of stacked transistors 121 are shared. One bit line 124 is therefore beneficial to simplifying the structure and manufacturing process of the dynamic memory 10 .

Optionally, in the embodiment of the present application, as shown in FIGS. 1 , 3 and 4 , the capacitor 127 includes an inner electrode 1271 located at the drain 33 , a dielectric layer 1272 and an outer electrode 1273 . The inner electrode 1271 , dielectric The layer 1272 and the external electrode 1273 both surround the drain electrode 33 of the semiconductor layer 22 , and the internal electrode 1271 , the dielectric layer 1272 and the external electrode 1273 are sequentially distributed in a direction away from the semiconductor layer 22 .

Specifically, during the manufacturing process of the dynamic memory 10, the internal electrode 1271, the dielectric layer 1272 and the external electrode 1273 are sequentially grown at the drain electrode 33 of the semiconductor layer 22. The internal electrode 1271, the dielectric layer 1272 and the external electrode 1273 all surround the semiconductor. The layers 22 are arranged and distributed sequentially in a direction away from the semiconductor layer 22 . The outer electrode 1273, the inner electrode 1271, and the dielectric layer 1272 overlap each other to form the capacitor 127. By arranging the external electrode 1273, the internal electrode 1271, and the dielectric layer 1272 around the semiconductor layer 22, the overlapping area of the external electrode 1273 and the internal electrode 1271 can be increased, which is beneficial to increasing the capacity of the capacitor 127. In addition, the thickness of the dielectric layer 1272 does not need to be very thin (the smaller the thickness of the dielectric layer 1272, the greater the capacity of the capacitor 127. In order to increase the capacity of the capacitor 127, the thickness of the dielectric layer 1272 can be reduced). Therefore, it is beneficial to reduce the cost of the dynamic memory 10. Difficulty of production. The materials of the inner electrode 1271 and the outer electrode 1273 include titanium nitride and other materials with good conductive properties. The material of the dielectric layer 1272 is selected from materials with high dielectric constant, which can be determined according to the actual situation.

Optionally, in this embodiment of the present application, the capacitors 127 of the memory cells 120 in two adjacent layers of memory arrays 12 share the outer electrode 1273. Specifically, as shown in Figure 3, the external electrode 1273 located between the two layers of memory cells 120 is both the external electrode 1273 of the capacitor 127 in the memory unit 120 of the upper layer and the capacitor 127 of the memory unit 120 of the next layer. The outer electrode 1273 thus simplifies the structure of the dynamic memory 10 and is beneficial to reducing the thickness of the dynamic memory 10 in the first direction in FIG. 3 . On the other hand, during the fabrication process of the dynamic memory 10, only one layer of external electrode 1273 needs to be fabricated between two adjacent layers of memory cells 120, thus simplifying the fabrication process of the dynamic memory 10.

In the embodiment of the present application, the transistor 121 includes a gate electrode 125 and a gate insulating layer 126 surrounding the semiconductor layer 22 . The gate insulating layer 126 and the gate electrode 125 are sequentially distributed in a direction away from the semiconductor layer 22 . Specifically, as shown in FIGS. 1 , 2 , 3 and 5 , the gate electrode 125 and the gate insulating layer 126 surround the semiconductor layer 22 , and the gate insulating layer 126 and the gate electrode 125 are sequentially distributed in a direction away from the semiconductor layer 22 . Gate electrodes 125 of transistors 121 located at different layers are insulated from each other by interlayer insulating layers 128 . By disposing the gate insulating layer 126 and the gate electrode 125 around the semiconductor layer 22, the overlapping area of the gate electrode 125 and the semiconductor layer 22 can be increased, thus making it easier to control the switching of the transistor 121.

Optionally, in the embodiment of the present application, in the same layer of memory array 12, at least two transistors 121 share a bit line 124. Specifically, as shown in Figure 1 and Figure 3, in the same layer of memory array 12, the transistors 121 in two adjacent memory cells 120 (the transistors 121 located on the same straight line in Figure 1) share the bit line 124. Therefore, while increasing the number of memory units 120 and improving storage density, it also avoids occupying too much area, which is beneficial to improving the integration of the device. It should be noted that in the same layer of memory array 12, the number of transistors 121 sharing the bit line 124 can be adjusted according to the actual situation. The greater the number of transistors 121 sharing the bit line 124, the more conducive to reducing the area of the dynamic memory 10 , improve the integration level of the dynamic memory 10.

Based on the same inventive concept, an embodiment of the present application also provides a storage device, which includes the dynamic memory 10 in the above embodiment and has the beneficial effects of the dynamic memory 10 in the above embodiment, which will not be described again here. Specifically, the storage device in the embodiment of the present application may be the main memory of the computer (referred to as main memory), etc. The details may be determined according to the actual situation and are not limited here.

Based on the same inventive concept, the embodiment of the present application also provides a method for manufacturing the dynamic memory 10, as shown in Figure 6, including:

S101. Provide a substrate;

S102. Make multiple transistors on one side of the substrate. The transistors include a semiconductor layer. The semiconductor layer includes a source electrode and a drain electrode arranged oppositely, and a channel between the source electrode and the drain electrode. The transistor also includes a gate electrode;

S103. Make a word line at the gate of the transistor, and electrically connect the word line to the transistor;

S104. Make a capacitor at the drain of the transistor, and the capacitor is electrically connected to the transistor;

S105. Create a bit line at the source of the semiconductor layer, and make the bit line penetrate multiple semiconductor layers. Multiple transistors are electrically connected through the bit line.

In the manufacturing method provided by the embodiment of the present application, the dynamic memory 10 includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11. The memory array 12 includes a plurality of memory cells 120 arranged in an array. Unit 120 includes transistor 121 and capacitor 127 . The dynamic memory 10 also includes a word line 123 and a bit line 124. The word line 123 is located at the gate 125 of the transistor 121 and is electrically connected to the transistor 121. The bit line 124 penetrates the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120. The bit line 124 is located at the source 32 , and the transistors 121 in the plurality of memory cells 120 are electrically connected through the bit line 124 . By stacking the storage array 12 including multiple storage units 120, a dynamic memory 10 with a three-dimensional structure is formed, which increases the storage capacity of the dynamic memory 10 and avoids the problem caused by arranging the storage units 120 on the same plane. The area of the dynamic memory 10 is too large, which makes the structural layout of the memory unit 120 more compact, which improves the storage density and is more conducive to device integration.

It should be noted that during the manufacturing process of the dynamic memory 10, the word lines 123 can be etched through a modified etching process so that the lengths of the word lines 123 located on different layers are inconsistent, even if the word lines 123 on different layers are in a stepped shape. . As shown in FIG. 1 and FIG. 2 , along the first direction in FIG. 2 (the direction gradually away from the substrate 11 ), the plurality of word lines 123 are in the second direction in FIG. 2 (the direction parallel to the substrate 11 ). The length is gradually reduced, so the word lines 123 located on different layers can be conveniently connected to the read and write circuits (not shown in Figures 1 and 2) through wiring.

Optionally, in a specific embodiment of the present application, multiple transistors 121 are fabricated on one side of the substrate 11, including:

A plurality of semiconductor layers are produced on one side of the substrate, and the semiconductor layers include oppositely arranged source electrodes and drain electrodes and a channel located between the source electrode and the drain electrode;

Optionally, in a specific embodiment of the present application, multiple semiconductor layers 22 are produced on one side of the substrate 11, including:

Multi-layer oxide films are stacked on one side of the substrate through a deposition process, and each layer of oxide film includes a sacrificial layer and a semiconductor layer 22 that are stacked in sequence;

Remove the sacrificial layer between the semiconductor layers.

Optionally, in a specific embodiment of the present application, fabricating a capacitor at the drain of the transistor includes: sequentially fabricating an internal electrode layer, a dielectric layer and an external electrode layer surrounding the semiconductor layer at the drain of the semiconductor layer, to form a capacitor.

The manufacturing method of the dynamic memory 10 in the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

As shown in Figure 7a, first, a substrate 11 is provided, and the material of the substrate 11 includes silicon.

As shown in FIG. 7b , then, a multi-layer oxide film 20 is stacked on one side of the substrate 11 through a deposition process (which may be an atomic deposition process or a chemical vapor deposition process, etc.). Each layer of the oxide film 20 includes an edge along the In Figure 7b, the sacrificial layer 21 and the semiconductor layer 22 are distributed in the first direction. The material of the sacrificial layer 21 includes aluminum zinc oxide (AZO), and the material of the semiconductor layer 22 includes IGZO. While the semiconductor layer 22 is being produced, the source electrode 32 , the drain electrode 33 and the channel 31 between the source electrode 32 and the drain electrode 33 are formed through a semiconductor oxide in-situ doping process. The number of layers of the oxide film 20 can be determined according to actual conditions, for example, it can be 8 layers, 16 layers, or 32 layers. When the material of the semiconductor layer 22 is IGZO, multi-layer semiconductor layers 22 can be produced through a deposition process during the production process of the dynamic memory 10, and the number of stacked semiconductor layers 22 can be larger, which is beneficial to improving the storage capacity of the dynamic memory 10. density. It should be noted that the three-layer oxide film 20 is only shown in FIG. 7b as an illustration and does not represent the actual situation.

As shown in FIG. 7c , the multi-layer sacrificial layer 21 and the multi-layer semiconductor layer 22 are then etched to remove part of the material of the sacrificial layer 21 and part of the semiconductor layer 22 so that the semiconductor layers 22 form a spaced-apart structure. The number of semiconductor layers 22 and the distance d between two adjacent semiconductor layers 22 can be adjusted according to actual conditions.

As shown in FIG. 7d , then, the portions of the sacrificial layer 21 located at both ends of the semiconductor layer 22 are etched to form trenches 23 . The width w of the groove 23 in the third direction in Figure 7d can be adjusted according to actual conditions.

As shown in FIG. 7e , next, a support layer 24a (the support layer 24a is located at both ends of the semiconductor layer 22) and an isolation layer 24b are deposited through an atomic deposition process or a chemical vapor deposition process, and the support layer 24a fills the trench 23. The material of the support layer 24a includes silicon nitride, and the material of the isolation layer 24b includes silicon oxide and other materials with good insulating properties, which may be determined based on actual conditions. It should be noted that the purpose of making the trench 23 and the support layer 24a is that after the sacrificial layer 21 is subsequently removed, the support layer 24a can support the semiconductor layer 22 and prevent the structure from collapsing. The material of the support layer 24a includes oxides, nitrides, etc. (such as silicon oxide and silicon nitride), and the details can be adjusted according to actual conditions.

As shown in FIG. 7f, next, by adjusting the etching selectivity ratio of the sacrificial layer 21 and the semiconductor layer 22 (making the etching rate of the sacrificial layer 21 greater than the etching rate of the semiconductor layer 22), the sacrificial layer located between the semiconductor layers 22 is 21 is etched and removed, leaving the semiconductor layer 22 as a plurality of semiconductor layers 22 . The support layers 24a at both ends of the semiconductor layer 22 can support the semiconductor layer 22 .

As shown in FIG. 7g , then, the gate insulating layer 126 surrounding the semiconductor layer 22 , the gate electrode 125 and the interlayer insulating layer 128 are sequentially grown on the semiconductor layer 22 , and the conductive material continues to grow between the gate electrodes 125 on the same layer. , to form the connection word line 123. The word lines 123 are etched through a modified etching process, so that the lengths of the word lines 123 located on different layers are inconsistent, that is, the word lines 123 on different layers are stepped.

As shown in FIG. 7h, next, the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 surrounding the semiconductor layer 22 are sequentially grown in the area where the capacitor 127 is to be formed on the semiconductor layer 22 (ie, the drain electrode 33 of the semiconductor layer 22). The electrode 1271, the dielectric layer 1272 and the external electrode 1273 constitute the capacitor 127. The external electrode 1273 located between the two semiconductor layers 22 is not only the external electrode 1273 of the capacitor 127 corresponding to the semiconductor layer 22 of the upper layer, but also the external electrode 1273 of the capacitor 127 corresponding to the semiconductor layer 22 of the lower layer. This simplifies the structure of the dynamic memory and also simplifies the manufacturing process of the dynamic memory. The materials of the inner electrode 1271 and the outer electrode 1273 include titanium nitride, and the details can be determined according to actual conditions.

As shown in FIG. 7i , next, a through hole 25 is opened at the source electrode 32 of the semiconductor layer 22 through an etching process, and the through hole 25 penetrates the multi-layer semiconductor layer 22 .

As shown in FIG. 7j , metal material is then filled into the through hole 25 to form the bit line 124 . Sources 32 of transistors 121 located at different layers are electrically connected through bit lines 124 . It should be noted that the blank area between the word line 123 and the bit line 124 can also be filled with an isolation material with good insulation properties (not shown in FIG. 7j ) to avoid gaps in the structure of the dynamic memory 10 .

Using the manufacturing method in the embodiment of the present application, it is relatively easy to manufacture the dynamic memory 10 with a stacked structure, making it possible to mass-produce the dynamic memory 10 with a stacked structure.

By applying the embodiments of this application, at least the following beneficial effects can be achieved:

1. In the embodiment of the present application, the dynamic memory 10 includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11. The memory array 12 includes a plurality of memory cells 120 arranged in an array. The memory cells 120 Includes transistor 121 and capacitor 127. The dynamic memory 10 also includes a word line 123 and a bit line 124. The word line 123 is located at the gate 125 of the transistor 121 and is electrically connected to the transistor 121. The bit line 124 penetrates the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120. The bit line 124 is located at the source 32 , and the transistors 121 in the plurality of memory cells 120 are electrically connected through the bit line 124 . By stacking the storage array 12 including multiple storage units 120, a dynamic memory 10 with a three-dimensional structure is formed, which increases the storage capacity of the dynamic memory 10 and avoids the problem caused by arranging the storage units 120 on the same plane. The area of the dynamic memory 10 is too large, which makes the structural layout of the memory unit 120 more compact, which improves the storage density and is more conducive to device integration. On the other hand, by allowing the bit line 124 to penetrate the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120, the plurality of stacked transistors 121 can be electrically connected through one bit line 124, thus simplifying the structure of the dynamic memory 10. and production process.

2. In the embodiment of the present application, the capacitor 127 includes an inner electrode 1271, a dielectric layer 1272 and an outer electrode 1273 located at the drain 33. The inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 all surround the drain of the semiconductor layer 22. 33. The internal electrode 1271, the dielectric layer 1272 and the external electrode 1273 are sequentially distributed along the direction away from the semiconductor layer 22. By disposing the external electrode 1273, the internal electrode 1271, and the dielectric layer 1272 around the semiconductor layer 22, the areas of the external electrode 1273 and the internal electrode 1271 can be increased, which is beneficial to increasing the capacity of the capacitor 127.

3. In the embodiment of the present application, the capacitors 127 of the memory cells 120 in two adjacent layers of memory arrays 12 share the external electrode 1273, that is, the external electrode 1273 located between the two layers of memory cells 120 is the memory cell located in the upper layer. The external electrode 1273 of the capacitor 127 in the memory unit 120 is also the external electrode 1273 of the capacitor 127 in the memory unit 120 of the next layer. Therefore, the structure and manufacturing process of the dynamic memory 10 can be simplified.

4. In the embodiment of the present application, in the same layer of memory array 12, at least two transistors 121 share the bit line 124. Therefore, while increasing the number of memory cells 120 and improving the storage density, it also avoids excessive occupation. area, which is conducive to improving the integration of the device.

5. By using IGZO as the material of the semiconductor layer 22, multi-layer semiconductor layers 22 can be produced through a deposition process during the production process of the dynamic memory 10, and the number of stacked semiconductor layers 22 can be larger, which is beneficial to improving the performance of the dynamic memory 10. storage density.

In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", The orientations or positional relationships indicated by "top", "bottom", "inner", "outside", etc. are based on the orientations or positional relationships shown in the drawings. They are only for the convenience of describing the present application and simplifying the description, and are not indicated or implied. The devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be construed as limiting the application.

The terms “first” and “second” are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, "plurality" means two or more.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above are only some of the embodiments of the present application. It should be pointed out that those of ordinary skill in the art can make several improvements and modifications without departing from the principles of the present application. These improvements and modifications should also be made. regarded as the protection scope of this application.

Claims

A dynamic memory, characterized in that it includes a substrate and a plurality of stacked memory arrays arranged on the substrate. The memory array includes a plurality of memory cells arranged in an array, and the memory cells include:

A transistor includes a semiconductor layer, the semiconductor layer includes a source electrode, a drain electrode, and a channel between the source electrode and the drain electrode, the material of the semiconductor layer includes IGZO; the transistor also includes a gate electrode;

a capacitor, electrically connected to the transistor, the capacitor being located at the drain of the transistor;

A word line, located at the gate, and the word line is electrically connected to the transistor;

The dynamic memory further includes a bit line penetrating the semiconductor layer of the transistor in the plurality of memory cells, the bit line being located at the source, and the transistor in the plurality of memory cells passing through the bit line. Wire connection.
The dynamic memory according to claim 1, wherein the capacitor includes an inner electrode, a dielectric layer and an outer electrode located at the drain, and the inner electrode, the dielectric layer and the outer electrode are all surrounded by The drain electrode of the semiconductor layer, the internal electrode, the dielectric layer and the external electrode are sequentially distributed in a direction away from the semiconductor layer.
The dynamic memory of claim 2, wherein the capacitances of the memory cells in two adjacent layers of the memory arrays share the external electrode.
The dynamic memory of claim 1, wherein the transistor further includes a gate insulating layer, the gate electrode and the gate insulating layer surround the semiconductor layer, and the gate insulating layer and the gate electrode extend along the The directions away from the semiconductor layer are sequentially distributed.
The dynamic memory according to claim 1, characterized in that, in the same layer of memory array, at least two of the transistors share a bit line.
The dynamic memory according to any one of claims 1 to 5, wherein the material of the word line includes ITO; and/or the material of the bit line includes tungsten.
The dynamic memory according to any one of claims 1 to 5, characterized in that the orthographic projection of the capacitor on the substrate intersects the orthographic projection of the drain of the transistor on the substrate. Stack.
The dynamic memory according to any one of claims 1 to 5, wherein the word lines are located between the gate electrodes in the same layer.
The dynamic memory according to any one of claims 1 to 5, wherein the orthographic projection of the bit line on the substrate is located within the orthographic projection of the source on the substrate.
The dynamic memory according to any one of claims 1 to 5, wherein the extending direction of the word line and the extending direction of the semiconductor layer are perpendicular to each other.
The dynamic memory according to any one of claims 1 to 5, wherein the lengths of the plurality of word lines in a direction parallel to the substrate gradually decrease in a direction gradually away from the substrate. .
The dynamic memory according to any one of claims 1 to 5, characterized in that:

The semiconductor layer is directly connected to the capacitor to achieve electrical connection between the drain of the semiconductor layer and the capacitor; and/or,

The semiconductor layer is directly connected to the bit line to achieve electrical connection between the source of the semiconductor layer and the bit line.
The dynamic memory according to any one of claims 1 to 5, wherein the transistor further includes an interlayer insulating layer, and gate electrodes of the transistors located at different layers are insulated from each other through the interlayer insulating layer.
A storage device, characterized by comprising the dynamic memory according to any one of claims 1 to 13.
A method for making dynamic memory, which is characterized by including:

provide a substrate;

A plurality of transistors are fabricated on one side of the substrate. The transistors include a semiconductor layer, the semiconductor layer includes a source electrode, a drain electrode, and a channel between the source electrode and the drain electrode. The transistor Also includes gate;

Make a word line at the gate of the transistor, and the word line is electrically connected to the transistor;

Make a capacitor at the drain of the transistor, and the capacitor is electrically connected to the transistor;

A bit line is formed at the source of the semiconductor layer, and the bit line penetrates a plurality of the semiconductor layers, and a plurality of the transistors are electrically connected through the bit line.
The manufacturing method according to claim 15, wherein manufacturing a plurality of transistors on one side of the substrate includes:

A plurality of semiconductor layers are produced on one side of the substrate, and the semiconductor layers include oppositely arranged source electrodes and drain electrodes;

A gate insulating layer, a gate electrode and an interlayer insulating layer surrounding the semiconductor layer are sequentially produced. The gate insulating layer, the gate electrode, the interlayer insulating layer and the semiconductor layer constitute a transistor.
The manufacturing method according to claim 16, characterized in that said manufacturing a plurality of semiconductor layers on one side of the substrate includes:

Multi-layer oxide films are stacked on one side of the substrate through a deposition process, and each layer of oxide film includes a sacrificial layer and a semiconductor layer that are stacked in sequence;

Etching multiple layers of the sacrificial layer and multiple layers of the semiconductor layer to form a plurality of spaced apart semiconductor layers;

Etching the portions of the sacrificial layer located at both ends of the semiconductor layer to form trenches;

Make support layers at both ends of the semiconductor layer through a deposition process, and fill the trenches with the support layers;

The sacrificial layer between the semiconductor layers is removed.
The manufacturing method according to claim 15, characterized in that said fabricating a capacitor at the drain of the transistor includes: sequentially fabricating an internal electrode layer surrounding the semiconductor layer at the drain of the semiconductor layer, dielectric layer and external electrode layer to form a capacitor.
The manufacturing method according to claim 15, characterized in that, manufacturing the word line at the gate of the transistor includes: etching the word line through a modified etching process so that all the words located on different layers are The word line is in the shape of a staircase.