CN207719208U - Memory - Google Patents
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- CN207719208U CN207719208U CN201721420073.1U CN201721420073U CN207719208U CN 207719208 U CN207719208 U CN 207719208U CN 201721420073 U CN201721420073 U CN 201721420073U CN 207719208 U CN207719208 U CN 207719208U
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Abstract
The utility model provides a kind of memory, is initially formed contact seal, re-forms storage node contacts, and contact seal can be good at that adjacent storage node contacts are isolated as a result, to improve the reliability for being formed by memory.Further, storage node contacts correspond to contact hole and deviate and extend in bit line structure, so that storage node contacts have larger cross-sectional width, so that storage node contacts have smaller resistance value, improve the quality of storage node contacts.Meanwhile storage node contacts correspond to contact hole and deviate and extend in bit line structure, but also the capacitor being subsequently formed has the process window of bigger, reduce technology difficulty.
Description
Technical field
The utility model is related to technical field of semiconductors, more particularly to a kind of memory.
Background technology
Capacitor and transistor are generally included in memory, wherein the capacitor is storing data, the transistor
To control the access of the data to being stored in the capacitor.Specifically, the wordline (word line) of the memory is electrically connected
It is connected to the grid of the transistor, the wordline controls the switch of the transistor；Also, the source electrode of the transistor is electrically connected
To bit line structure (bit line), to form electric current transmission channel；Meanwhile the drain electrode of the transistor is electrically connected to the capacitance
Device, to achieve the purpose that data storage or output.Wherein, the drain electrode of the transistor usually by storage node contacts realize with
The resistance value of the electrical connection of the capacitor, the quality of storage node contacts, such as storage node contacts, by strong influence to institute
The quality of the memory of formation.
Therefore, the storage node contacts for how forming high quality are an extremely important problems in art technology.
Utility model content
The purpose of this utility model is to provide a kind of memory, the memory includes：
One substrate is formed with multiple active areas in the substrate, more is formed on the substrate and is extended in a first direction
Bit line structure and the more shielding wires extended in a second direction, adjacent institute's bit line structures and the adjacent shielding wire surround more
A contact hole, and drain electrode one contact hole of alignment in the active area；
One first storage node contacts structure is filled in the contact hole over the substrate, and electric with the drain electrode
Connection；
One contact seal is located on the substrate, and part covers the first storage node contacts structure and described
Bit line structure, the region for not covering first storage node contacts and institute's bit line structures in the contact seal are used for structure
At multiple openings through the contact seal, the first storage node contacts structure is accordingly locally exposed to one
In a opening；And
One second storage node contacts structure is filled in said opening, the second storage node contacts structure and institute
The electrical connection of the first storage node contacts structure is stated, to constitute a storage node contacts.
Optionally, in the memory, corresponding first storage node contacts of the opening and layer offset extension
Into institute's bit line structures, make the opening with more coinciding in the part of institute's bit line structures, in said opening simultaneously
The bit line separation layer being corresponding in the first storage node contacts structure and institute's bit line structures.
Optionally, in the memory, the bottom of the opening extends to the first storage node contacts structure
In the bit line separation layer for neutralizing institute's bit line structures.
Optionally, in the memory, the second storage node contacts structure is part potting in depth direction
And part up protrudes mode and is connected to the first storage node contacts structure；It is non-central in alignment with described in width direction
First storage node contacts structure, and the past side of part potting and part protrudes mode and is connected to first storage node contacts
Structure.
Optionally, in the memory, the storage node contacts, which correspond to the contact hole and deviate, extends to institute
In bit line structures, wherein the top surface of the storage node contacts flushes with the top surface of the contact seal or be less than institute
The top surface of contact seal is stated, the storage node contacts extend to the bottom surface in institute's bit line structures and are higher than institute's bit line conductors
Top surface.
Optionally, in the memory, the more words extended along the second direction are also formed in the substrate
Line, the shielding wire are directed at the wordline.
In memory provided by the utility model, it is initially formed contact seal, re-forms storage node contacts, as a result,
Contact seal can be good at that adjacent storage node contacts are isolated, to improve the reliability for being formed by memory.Into
One step, storage node contacts correspond to contact hole and deviate and extend in bit line structure, so that storage node contacts have
Larger cross-sectional width improves the quality of storage node contacts so that storage node contacts have smaller resistance value.Together
When, storage node contacts correspond to contact hole and deviate and extend in bit line structure, but also the capacitor being subsequently formed has more
Big process window, reduces technology difficulty.
Description of the drawings
Fig. 1 is a kind of flow diagram of memory manufacturing；
Fig. 2 is a kind of schematic top plan view of memory；
Fig. 3 is diagrammatic cross-section of the memory shown in Fig. 2 along the substrate of AA '；
Fig. 4 is the diagrammatic cross-section that connecting material layer is formed on substrate shown in Fig. 3；
Fig. 5 is the diagrammatic cross-section executed to structure shown in Fig. 4 after patterning etching technics；
Fig. 6 is that the diagrammatic cross-section after contact seal is formed in structure described in Fig. 5；
Fig. 7 is the flow diagram of the memory manufacturing of the utility model embodiment；
Fig. 8 is the schematic top plan view of the memory of the utility model embodiment；
Fig. 9 is the schematic top plan view for not forming shielding wire on the substrate of the utility model embodiment；
Figure 10 is the schematic top plan view that shielding wire has been formed on the substrate of the utility model embodiment；
Figure 11 is diagrammatic cross-section of the substrate shown in Fig. 10 along the substrate of BB '；
Figure 12 is the diagrammatic cross-section formed on the substrate shown in Figure 11 after the first storage node contacts structure；
Figure 13 is that the diagrammatic cross-section after first layer the first connecting material layer is formed on the substrate shown in Figure 11；
Figure 14 is the diagrammatic cross-section executed to structure shown in Figure 13 after patterning etching technics；
Figure 15 is that the diagrammatic cross-section after the second layer the first connecting material layer is formed in the structure shown in Figure 14；
Figure 16 is that the diagrammatic cross-section after contact seal is formed in the structure shown in Figure 12；
Figure 17 is the diagrammatic cross-section executed to structure shown in Figure 16 after patterning etching technics；
Figure 18 is the diagrammatic cross-section formed in the structure shown in Figure 17 after the second storage node contacts structure；
Figure 19 is the diagrammatic cross-section formed in the structure shown in Figure 17 after the second connecting material layer；
Wherein,
100- substrates；
110- active areas；
111- drains；
The active isolation structures of 112-；
120- bit line structures；
121- bit line conductors；
122- bit line separation layers；
130- shielding wires；
140- contact holes；
150- connecting material layers；
160- storage node contacts；
170- is open；
180- contact seals；
200- substrates；
210- active areas；
211- drains；
212- wordline；
The active isolation structures of 213-；
220- bit line structures；
221- bit line conductors；
222- bit line separation layers；
230- shielding wires；
240- contact holes；
250- the first storage node contacts structures；
251- first layers the first storage node contacts structure；
The 252- second layers the first storage node contacts structure；
251a- first layers the first connecting material layer；
The 252a- second layers the first connecting material layer；
260- contact seals；
270- is open；
280- the second storage node contacts structures；
280a- the second connecting material layers；
290- storage node contacts.
Specific implementation mode
It please refers to Fig.1 to Fig. 6, wherein Fig. 1 is a kind of flow diagram of memory manufacturing；Fig. 2 is a kind of storage
The schematic top plan view of device；Fig. 3 is diagrammatic cross-section of the memory shown in Fig. 2 along the substrate of AA '；Fig. 4 is lining shown in Fig. 3
The diagrammatic cross-section of connecting material layer is formed on bottom；Fig. 5 is the section executed to structure shown in Fig. 4 after patterning etching technics
Schematic diagram；Fig. 6 is that the diagrammatic cross-section after contact seal is formed in structure described in Fig. 5.As shown in Figures 1 to 6, described
The manufacturing method of memory includes：
Step S10：One substrate 100 is provided, is formed with multiple active areas 110 in the substrate 100, on the substrate 100
It is formed with the more bit line structures extended in a first direction 120 and the more shielding wires 130 extended in a second direction, the bit line
Structure 120 includes bit line conductors 121 and covers the bit line separation layer 122 of institute's bit line conductors 121, adjacent institute's bit line structures
120 and the adjacent shielding wire 130 surround multiple contact holes 140, and 111 alignment institutes of a drain electrode in the active area 110
State contact hole 140, wherein can be isolated by active isolation structure 112 between the adjacent active area 110；
Step S11：A connecting material layer 150 is formed on the substrate 100, the connecting material layer 150 covers described
Contact hole 140, institute's bit line structures 120 and the shielding wire 130, the connecting material layer 150 are electrically connected with the drain electrode 111
It connects；
Step S12：Patterning etches the connecting material layer 150 and institute's bit line structures 120, and etching stopping is in described
In connecting material layer 150 and in the bit line separation layer of institute's bit line structures 120, to form multiple storage node contacts 160 and position
In an opening 170 of the adjacent storage node contacts 160；And
Step S13：A contact seal 180 is formed on the substrate 100, the contact seal 180 is filled described
Opening 170.
With continued reference to FIG. 6, the opening 170 etches the connecting material layer 150 and the bitline junction by patterning
Simultaneously etching stopping is formed, institute structure 120 in the connecting material layer 150 and in the bit line separation layer of institute's bit line structures 120
State that contact seal 180 is located in the opening 170 namely the contact seal 180 is buried is placed in the adjacent storage and saves
Between point contact 160, the bottom surface of the contact seal 180 is less than the top surface of the bit line separation layer 122, as a result, by
The storage that the bit line separation layer 122 and the contact seal 180 are kept apart with the adjacent storage node contacts 160
The cross-sectional width of node contact 160 is smaller (herein i.e. along the width of second direction), to may result in the storage section
The resistance value of point contact 160 is higher.
With continued reference to FIG. 6, the resistance value for being formed by the storage node contacts 160 by above-mentioned technique is largely determined by
The cross-sectional width of the part between the bit line separation layer 122 and the contact seal 180 of the storage node contacts 160
h1。
On this basis, the utility model provides the manufacturing method of another memory, specifically, referring to FIG. 7, it is
The flow diagram of the memory manufacturing of the utility model embodiment.As shown in fig. 7, the manufacturing method packet of the memory
It includes：
Step S20：One substrate is provided, multiple active areas are formed in the substrate, more edges are formed on the substrate
The bit line structure and the more shielding wires extended in a second direction that first direction extends, adjacent institute's bit line structures and adjacent described
Shielding wire surrounds multiple contact holes, and drain electrode one contact hole of alignment in the active area；
Step S21：Alignment one first storage node contacts structure of filling is in the contact hole on the substrate, and institute
The first storage node contacts structure is stated to be electrically connected with the drain electrode；
Step S22：A contact seal is formed on the substrate, contact seal covering first storage saves
Point contact structure, institute's bit line structures and the shielding wire；
Step S23：Etch the portion that the first storage node contacts superstructure is partially located in the contact seal
Divide to form multiple openings, it is described to be open through the contact seal to expose the first storage node contacts structure,
And each first storage node contacts structure corresponds to an opening；And
Step S24：One second storage node contacts structure is filled in the opening, the second storage node contacts knot
Structure and the first storage node contacts structure electrical connection, to constitute a storage node contacts.
Correspondingly, the utility model also provides a kind of memory, the memory includes：
One substrate is formed with multiple active areas in the substrate, more is formed on the substrate and is extended in a first direction
Bit line structure and the more shielding wires extended in a second direction, adjacent institute's bit line structures and the adjacent shielding wire surround more
A contact hole, and drain electrode one contact hole of alignment in the active area；
One first storage node contacts structure is filled in the contact hole over the substrate, and electric with the drain electrode
Connection；
One contact seal is located on the substrate, and part covers the first storage node contacts structure and described
Bit line structure, the region for not covering first storage node contacts and institute's bit line structures in the contact seal are used for structure
At multiple openings through the contact seal, the first storage node contacts structure is accordingly locally exposed to one
In a opening；And
One second storage node contacts structure is filled in said opening, the second storage node contacts structure and institute
The electrical connection of the first storage node contacts structure is stated, to constitute a storage node contacts.
Subsequently, by conjunction with attached drawing to the utility model proposes memory and its manufacturing method make further specifically
It is bright.According to following explanation and claims, will be become apparent from feature the advantages of the utility model.It should be noted that attached drawing is equal
Non-accurate ratio is used using very simplified form and, only to convenient, lucidly aid illustration the utility model is real
Apply the purpose of example.
Specifically, please referring to Fig. 8 to Figure 19, wherein Fig. 8 is the vertical view signal of the memory of the utility model embodiment
Figure；Fig. 9 is the schematic top plan view for not forming shielding wire on the substrate of the utility model embodiment；Figure 10 is that the utility model is implemented
The schematic top plan view of shielding wire has been formed on the substrate of example；Figure 11 is that substrate shown in Fig. 10 is illustrated along the section of the substrate of BB '
Figure；Figure 12 is the diagrammatic cross-section formed on the substrate shown in Figure 11 after the first storage node contacts structure；Figure 13 is to scheme
The diagrammatic cross-section after first layer the first connecting material layer is formed on substrate shown in 11；Figure 14 is held to structure shown in Figure 13
Diagrammatic cross-section after row patterning etching technics；Figure 15 is formation the first connecting material of the second layer in the structure shown in Figure 14
Diagrammatic cross-section after layer；Figure 16 is that the diagrammatic cross-section after contact seal is formed in the structure shown in Figure 12；Figure 17 is
The diagrammatic cross-section after patterning etching technics is executed to structure shown in Figure 16；Figure 18 is formed in the structure shown in Figure 17
Diagrammatic cross-section after second storage node contacts structure；Figure 19 is that the second connecting material layer is formed in the structure shown in Figure 17
Diagrammatic cross-section afterwards.
As shown in Fig. 9, Figure 10 and Figure 11, first, a substrate 200 is provided, multiple active areas are formed in the substrate 200
210, it is formed with the more bit line structures extended in a first direction 220 on the substrate 200 and more extends in a second direction
Shielding wire 230, adjacent institute's bit line structures 220 and the adjacent shielding wire 230 surround multiple contact holes 240, and described active
A drain electrode 211 in area 210 is directed at the contact hole 240.
In the embodiment of the present application, the more wordline extended along the second direction are also formed in the substrate 200
212, the shielding wire 230 is directed at the wordline 212.
Wherein, institute's bit line structures 220 include bit line conductors 221 and cover the bit line separation layer of institute's bit line conductors 221
222, the bit line separation layer 222 covers the side and top surface of institute's bit line conductors 221.
In the embodiment of the present application, the first direction and the second direction are vertical.Further, the active area
210 extend along third direction, and the third direction is handed over the first direction and the second direction monoclinic phase.In the application reality
It applies in example, multiple active areas 210 are in plurality of rows, and active area 210 described in adjacent rows is staggered.Here, respectively
Positioned at the active area 210 of adjacent rows, opposite wordline 212 differs (including to be differed and part identical portions completely
Divide and differ), for example, first active area 210 correspondence first and second wordline 212 of the first row, and the
First active area 210 of two rows is described active with first of the first row only in corresponding first wordline 212
Area 210 is identical, second active area 210 of the second row only in corresponding second wordline 212 with the first row the
One active area 210 is identical.In the embodiment of the present application, active isolation junction can be passed through between the adjacent active area 210
Structure 213 is isolated.
As shown in figure 12, one first storage node contacts structure 250 of alignment filling is in the contact on the substrate 200
In window 240, and the first storage node contacts structure 250 is electrically connected with the drain electrode 211.I.e. here, first storage
Node contact structures 250 cover the contact hole 240, and expose the top surface of institute's bit line structures 220 (herein namely described in exposing
The top surface of bit line separation layer 222).
Wherein, the first storage node contacts structure 250 can be single layer structure, or multi-layer laminate structure,
Every layer of material is selected from one of polysilicon and metal in the first storage node contacts structure 250.
In the embodiment of the present application, the first storage node contacts structure 250 is two-layer sandwich comprising is formed
In on the substrate 200 the first storage node contacts of first layer structure 251 and be formed in the first memory node of the first layer
The first storage node contacts of second layer structure 252 in contact structures 251.
Specifically, the first storage node contacts structure 250 can be formed by following processing step：
One first connecting material layer is formed on the substrate 200, the first connecting material layer covers the contact hole
240, institute's bit line structures 220 and the shielding wire 230；
The thickness of the first connecting material layer is consumed in a manner of selected from one of grinding, etching and the two combination extremely
Expose institute's bit line structures 220 and the shielding wire 230, to form the first storage node contacts structure 250.
Wherein, the first connecting material layer can be single layer structure or multi-layer laminate structure.
Please refer to Fig.1 2 to Figure 15, in the embodiment of the present application, the first storage node contacts structure 250 especially by
Following technique is formed：
As shown in figure 13, first layer the first connecting material layer 251a is formed on the substrate 200, the first layer first
Connecting material layer 251a covers the contact hole 240, institute's bit line structures 220 and the shielding wire 230.Here, described first
The material of the first connecting material layer 251a of layer is polysilicon, and the first layer the first connecting material layer 251a can pass through chemical gaseous phase
The techniques such as depositing operation or physical gas-phase deposition are formed.
Then, as shown in figure 14, patternable etches the first connecting material of first layer layer 251a, removes the bit line
The part of structure 220 and the top of the shielding wire 230, to form the first storage node contacts of first layer structure 251, described first
The first storage node contacts structure 251 of layer covers the contact hole 240 and exposes institute's bit line structures 220 and the shielding wire
230。
Then, as shown in figure 15, the second layer the first connecting material layer 252a is formed on the substrate 200, described second
The first connecting material layer of layer 252a covers the first storage node contacts of first layer structure 251, institute's bit line structures 220 and institute
State shielding wire 230.Here, the material of the second layer the first connecting material layer 252a is metal, the second layer first connects
Material layer 252a can be formed by techniques such as chemical vapor deposition method or physical gas-phase depositions.
As shown in figure 12, in the embodiment of the present application, the second layer first is then thinned by grinding technics and connects material
The thickness of bed of material 252a obtains the first storage node contacts of the second layer to institute's bit line structures 220 and the shielding wire 230 is exposed
Structure 252, to form the first storage node contacts structure 250.
In the other embodiment of the application, first layer the first connecting material layer 251a can also be initially formed in the substrate
On 200 and cover the contact hole 240, institute's bit line structures 220 and the shielding wire 230；Re-form the connection of the second layer first
Material layer 252a is on the substrate 200 and the second layer the first connecting material layer 252a covers the first layer first and connect
Material layer 251a；Then, can only by a step etching technics either a step grinding technics or be applied in combination etching technics and
The first layer the first connecting material layer 251a and second layer the first connecting material layer 252a is thinned to exposing in grinding technics
Institute's bit line structures 220 and the shielding wire 230, to obtain the first storage node contacts structure 250.
In the embodiment of the present application, it is two-layer sandwich to be formed by the first storage node contacts structure 250,
In the application other embodiment, the first storage node contacts structure 250 or single layer structure, such as described first deposit
Storage node contact structures 250 are single polysilicon layer, alternatively, the first storage node contacts structure 250 or three layers
Laminated construction etc..
Then, it please refers to Fig.1 6, forms a contact seal 260 on the substrate 200, the contact seal 260
The first storage node contacts structure 250, institute's bit line structures 220 are covered (i.e. here, the contact seal 260 covers
The top surface of the bit line separation layer 222) and the shielding wire 230.I.e. in the embodiment of the present application, the contact seal 260
Bottom surface higher than institute's bit line structures 220 top surface (i.e. here, the bottom surface of the contact seal 260 be higher than the bit line every
The top surface of absciss layer 222).Wherein, the material of the contact seal 260 can be the insulation such as silicon nitride, silica, silicon oxynitride
Material.The contact seal 260 can be formed by chemical vapor deposition method.
7 are please referred to Fig.1, in the embodiment of the present application, then, is etched described in being partially located in the contact seal 260
The part of the top of first storage node contacts structure 250 to form multiple openings 270, the opening 270 through the contact every
Absciss layer 260 is to expose the first storage node contacts structure 250, and each opening 270 corresponds to one described first
Storage node contacts structure 250.Here, the contact seal 260 also covers the first storage node contacts structure 250
Part.I.e. in the embodiment of the present application, patterning etching technics is performed to the contact seal 260.
In the embodiment of the present application, the opening 270 extends to institute's bit line structures 220 and neutralizes first memory node
In contact structures 250.The forming method of the opening 270 specifically includes：
Etch the part and position for being located at 250 top of the first storage node contacts structure in the contact seal 260
Part above institute's bit line structures 220, to form the opening 270, the opening 270 corresponds to first memory node
It contacts 250 and deviates and extend in institute's bit line structures 220, so that the opening 270 is had more and coincide in institute's bit line structures 220
Part, to expose the bit line separation layer in first storage node contacts 250 and institute's bit line structures 220 simultaneously
222.Here, the contact seal 260 exposes part and the institute's bit line structures of first storage node contacts 250
The part of the bit line separation layer 222 in 220, meanwhile, the contact seal 260 covers first memory node and connects
Touch the part of the bit line separation layer 222 in 250 part and institute's bit line structures 220.
Further, the contact seal 260 is being etched to expose 250 He of the first storage node contacts structure
After institute's bit line structures 220, then etch in the first storage node contacts structure 250 and institute's bit line structures 220
The bit line separation layer 222, partly to remove the first storage node contacts structure 250 and the bit line separation layer 222, and
Etching stopping is neutralized in the first storage node contacts structure 250 in the bit line separation layer 222.
In the embodiment of the present application, the contact seal 260, the first storage node contacts structure 250 and described
Bit line separation layer 222 surrounds the opening 270.The bottom surface of the opening 270 is higher than the top surface of institute's bit line conductors 221.Exist
In the embodiment of the present application, the opening 270 is from the surface of the contact seal 260 deeply to first storage node contacts
In structure 250 and the bit line separation layer 222, there is portion between the bottom surface and the top surface of the substrate 200 of the opening 270
Divide the bit line separation layer 222 and the first storage node contacts structure 250 of thickness.
Wherein, the opening 270 can be realized by a step etching technics, can also be realized by multistep etching technics,
To improve etching precision.For example, the step patterning etching technics removal part contact seal 260 can be first passed through with dew
Go out part the first storage node contacts structure 250 and part the bit line separation layer 222；Then, then pass through (another) step
The first storage node contacts structure 250 that etching technics removal is exposed and the bit line separation layer 222 exposed are patterned,
To form the opening 270.
Please refer to Fig. 8 and Figure 18, in the embodiment of the present application, then, filling one second storage node contacts structure 280 in
In the opening 270, the second storage node contacts structure 280 and the first storage node contacts structure 250 electrical connection,
To constitute a storage node contacts 290.
Wherein, after filling the second storage node contacts structure 280 in the opening 270, second storage
The top surface of node contact structures 280 can be flushed with the top surface of the contact seal 260, the second storage node contacts knot
The top surface of structure 280 can also be less than the top surface of the contact seal 260.
In the embodiment of the present application, the second storage node contacts structure 280 is part potting and portion in depth direction
It point up protrudes mode and is connected to the first storage node contacts structure 250；The second storage node contacts structure 280 exists
Width direction is non-central in alignment with the first storage node contacts structure 250, and part potting and part are protruded toward side
Mode is connected to the first storage node contacts structure 250.
Here, the storage node contacts 290 include the first storage node contacts structure 250 and are deposited with described first
Store up the second storage node contacts structure 280 that node contact structures 250 are electrically connected.The two neighboring storage node contacts
290 are isolated by the contact seal 260 and the bit line separation layer 222.The storage node contacts 290 connect described in corresponding to
It touches window 240 and deviates and extend in institute's bit line structures 220, wherein the top surface of the storage node contacts 290 is contacted with described
The top surface of separation layer 260 flush or less than the contact seal 260 top surface, the storage node contacts 290 extend to
Bottom surface in institute's bit line structures 220 is higher than the top surface of institute's bit line conductors 221.
In the embodiment of the present application, the second storage node contacts structure 280 can specifically pass through following processing step shape
At：
As shown in figure 19, one second connecting material layer 280a is formed on the substrate 200, the second connecting material layer
The 280a fillings opening 270 simultaneously covers the contact seal 260.Here, the material of the second connecting material layer 280a
For metal.
Then, the thickness for continuing to consume the second connecting material layer 280a in a manner of grinding as shown in figure 18 extremely reveals
Go out the contact seal 260, to form the second storage node contacts structure 280.Wherein, second memory node connects
The material for touching structure 280 is metal.
Please continue to refer to Figure 18, in the embodiment of the present application, the storage node contacts are formed by by above-mentioned technique
290 resistance value is largely determined by the bit line separation layer 222 and the contact isolation of 290 opposite side of the storage node contacts
Cross-sectional width h2 between layer 260.Compare the cross-sectional width h1 in the cross-sectional width h2 and Fig. 6 in Figure 18, it is seen then that by this reality
The cross-sectional width h2 biggers in the storage node contacts 290 are formed by with new embodiment, as a result, relative to the storage
Node contact 160, the storage node contacts 290 will have lower resistance value.
To sum up, in the manufacturing method for the memory that the utility model embodiment provides, it is initially formed contact seal,
Storage node contacts are re-formed, contact seal can be good at that adjacent storage node contacts are isolated as a result, to improve
The reliability of the memory of formation.Further, storage node contacts correspond to contact hole and deviate and extend in bit line structure, by
This makes storage node contacts have larger cross-sectional width, so that storage node contacts have smaller resistance value, improves
The quality of storage node contacts.Meanwhile storage node contacts correspond to contact hole and deviate and extend in bit line structure, but also
The capacitor being subsequently formed has the process window of bigger, reduces technology difficulty.
Correspondingly, the utility model embodiment also provides a kind of memory, and please continue to refer to Figure 18, the memory packet
It includes：
One substrate 200 is formed with multiple active areas 210 in the substrate 200, more edges is formed on the substrate 200
The bit line structure 220 and the more shielding wires 230 extended in a second direction that first direction extends, adjacent institute's bit line structures 220
Multiple contact holes 240 are surrounded with the adjacent shielding wire 230, and are connect described in 211 alignment of a drain electrode in the active area 210
Touch window 240；
One first storage node contacts structure 250 is filled in the contact hole 240 on the substrate 200, and and institute
State 211 electrical connection of drain electrode；
One contact seal 260 is located on the substrate 200, and part covers the first storage node contacts structure
250 and institute's bit line structures 220, first storage node contacts 250 and institute's rheme are not covered in the contact seal 260
The region of cable architecture 220 is for constituting multiple openings 270 through the contact seal 260, the first storage section
Accordingly part is exposed in an opening 270 point contact structure 250；And
One second storage node contacts structure 280 is filled in the opening 270, the second storage node contacts knot
Structure 280 and the first storage node contacts structure 250 electrical connection, to constitute a storage node contacts 290.
In the embodiment of the present application, the more wordline extended along the second direction are also formed in the substrate 200
212, the shielding wire 230 is directed at the wordline 212.Institute's bit line structures 220 include bit line conductors 221 and the covering bit line
The bit line separation layer 222 of conductor 221, the bit line separation layer 222 cover the side and top surface of institute's bit line conductors 221.
Further, the opening 270, which corresponds to the first storage node contacts structure 250 and deviates, extends to institute's rheme
In cable architecture 220, make the opening 270 with more coinciding in the part of institute's bit line structures 220, in the opening 270
The bit line separation layer 222 being corresponding with simultaneously in the first storage node contacts structure 250 and institute's bit line structures 220.
The bottom of the opening 270 extends in the first storage node contacts structure 250 and institute's rheme of institute's bit line structures 220
In line separation layer 222.
In the embodiment of the present application, the second storage node contacts structure 280 is part potting and portion in depth direction
It point up protrudes mode and is connected to the first storage node contacts structure 250；The second storage node contacts structure 280 exists
Width direction is non-central in alignment with the first storage node contacts structure 250, and part potting and part are protruded toward side
Mode is connected to the first storage node contacts structure 250.
Here, the storage node contacts 290, which correspond to the contact hole 240 and deviate, extends to institute's bit line structures 220
In, wherein the top surface of the storage node contacts 290 flushes with the top surface of the contact seal 260 or is connect less than described
The top surface of separation layer 260 is touched, the storage node contacts 290 extend to the bottom surface in institute's bit line structures 220 and are higher than institute's rheme
The top surface of line conductor 221.
To sum up, in the memory that the utility model embodiment provides, it is initially formed contact seal, re-forms storage
Node contact, contact seal can be good at that adjacent storage node contacts are isolated as a result, so that raising is formed by storage
The reliability of device.Further, storage node contacts correspond to contact hole and deviate and extend in bit line structure, so that storage
Node contact has larger cross-sectional width, so that storage node contacts have smaller resistance value, improves memory node
The quality of contact.Meanwhile storage node contacts correspond to contact hole and deviate and extend in bit line structure, but also be subsequently formed
Capacitor has the process window of bigger, reduces technology difficulty.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Calmly, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content, belong to right and want
Seek the protection domain of book.
Claims (6)
1. a kind of memory, which is characterized in that the memory includes：
One substrate is formed with multiple active areas in the substrate, the more positions extended in a first direction is formed on the substrate
Cable architecture and the more shielding wires extended in a second direction, adjacent institute's bit line structures and the adjacent shielding wire surround multiple connect
Touch window, and drain electrode one contact hole of alignment in the active area；
One first storage node contacts structure is filled in the contact hole over the substrate, and is electrically connected with the drain electrode；
One contact seal is located on the substrate, and part covers the first storage node contacts structure and the bit line
Structure, the region for not covering the first storage node contacts structure and institute's bit line structures in the contact seal are used for structure
At multiple openings through the contact seal, the first storage node contacts structure is accordingly locally exposed to one
In a opening；And
One second storage node contacts structure, filling in said opening, the second storage node contacts structure and described the
One storage node contacts structure is electrically connected, to constitute a storage node contacts.
2. memory as described in claim 1, which is characterized in that institute's bit line structures include bit line conductors and covering institute rheme
The bit line separation layer of line conductor, the opening, which corresponds to the first storage node contacts structure and deviates, extends to the bitline junction
In structure, make the opening with more coinciding in the part of institute's bit line structures, to be corresponding with described the simultaneously in said opening
The bit line separation layer in one storage node contacts structure and institute's bit line structures.
3. memory as claimed in claim 2, which is characterized in that the bottom of the opening extends to first memory node
In contact structures and in the bit line separation layer of institute's bit line structures.
4. memory as claimed in claim 3, which is characterized in that the second storage node contacts structure is in depth direction
Part potting and part up protrude mode and are connected to the first storage node contacts structure；It is non-central right in width direction
Standard is in the first storage node contacts structure, and the past side of part potting and part protrudes mode and is connected to first storage
Node contact structures.
5. memory as claimed in claim 3, which is characterized in that the storage node contacts correspond to the contact hole and deviate
Extend in institute's bit line structures, wherein the top surface of the storage node contacts flushed with the top surface of the contact seal or
Person is less than the top surface of the contact seal, and the storage node contacts extend to the bottom surface in institute's bit line structures higher than described
The top surface of bit line conductors.
6. such as memory according to any one of claims 1 to 5, which is characterized in that be also formed with more edges in the substrate
The wordline that the second direction extends, the shielding wire are directed at the wordline.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721420073.1U CN207719208U (en) | 2017-10-30 | 2017-10-30 | Memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721420073.1U CN207719208U (en) | 2017-10-30 | 2017-10-30 | Memory |
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| Publication Number | Publication Date |
|---|---|
| CN207719208U true CN207719208U (en) | 2018-08-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721420073.1U Active CN207719208U (en) | 2017-10-30 | 2017-10-30 | Memory |
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|---|---|
| CN (1) | CN207719208U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107845633A (en) * | 2017-10-30 | 2018-03-27 | 睿力集成电路有限公司 | Memory and its manufacture method |
| WO2023207109A1 (en) * | 2022-04-25 | 2023-11-02 | 北京超弦存储器研究院 | Dynamic memory and manufacturing method therefor, and storage device |
-
2017
- 2017-10-30 CN CN201721420073.1U patent/CN207719208U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107845633A (en) * | 2017-10-30 | 2018-03-27 | 睿力集成电路有限公司 | Memory and its manufacture method |
| CN107845633B (en) * | 2017-10-30 | 2023-05-12 | 长鑫存储技术有限公司 | Memory and manufacturing method thereof |
| WO2023207109A1 (en) * | 2022-04-25 | 2023-11-02 | 北京超弦存储器研究院 | Dynamic memory and manufacturing method therefor, and storage device |
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Effective date of registration: 20180930 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |
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| TR01 | Transfer of patent right |