CN207408737U - Mask plate and memory - Google Patents
Mask plate and memory Download PDFInfo
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- CN207408737U CN207408737U CN201721490289.5U CN201721490289U CN207408737U CN 207408737 U CN207408737 U CN 207408737U CN 201721490289 U CN201721490289 U CN 201721490289U CN 207408737 U CN207408737 U CN 207408737U
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Abstract
The utility model provides a kind of mask plate and memory, mask plate includes the first linear pattern extended along a first direction and the second linear pattern extended along second direction, thus during alignment between mask plate, can in a first direction with carry out alignment in second direction both direction, so as to improve alignment precision.Further, mask plate can be used for forming storage node contacts and capacitor, i.e. in memory manufacture, two structures being connected can be manufactured with the identical mask plate of pattern, it is possible thereby to the alignment precision of mask plate in former and later two steps is further improved, so as to also improve the q＆r of formed memory.
Description
Technical field
The utility model is related to technical field of manufacturing semiconductors, more particularly to a kind of mask plate and memory.
Background technology
In field of semiconductor manufacture, photoetching technique is used to pattern being transferred on substrate from mask plate, therein to cover
Film version (mask), also referred to as reticle, mask plate or light shield are a kind of tablets for exposure light with translucency,
It is upper to have for layout of the exposure light with light-proofness, it can be achieved that selectable block is irradiated to substrate surface photoresist
Layer either the light on mask layer and finally forms corresponding pattern on the photoresist layer or mask layer of substrate surface.
Memory manufacture is very important one piece in field of semiconductor manufacture.Capacitor and crystalline substance are generally included in memory
Body pipe, wherein, the capacitor is to store data, and the transistor is controlling to the data that are stored in the capacitor
Access.Specifically, the wordline (word line) of the memory is electrically connected to the grid of the transistor, the wordline control
The switch of the transistor；Also, the source electrode of the transistor is electrically connected to bit line structure (bit line), to form electric current biography
Defeated access；Meanwhile the drain electrode of the transistor is electrically connected to the capacitor, to achieve the purpose that data storage or output.Its
In, the drain electrode of the transistor is usually realized by storage node contacts to be electrically connected with the capacitor, the memory node
Isolated between contact by the node isolation structure being located between the storage node contacts.
In the manufacture of memory, can repeatedly use photoetching technique and mask plate, for example, formed node isolation structure and
During capacitor, photoetching technique and corresponding two mask plates will be used, there are problems that being not easy alignment between mask plate, so as to
Reduce the quality of formed memory.
Utility model content
The purpose of this utility model is to provide a kind of mask plate and memory, between solution in the prior art mask plate
Alignment is not easy, the problem of so as to reduce the quality of formed memory.
In order to solve the above technical problems, the utility model provides a kind of mask plate, the mask plate includes：
One substrate has multiple first linear patterns and multiple second linear patterns on the substrate；Wherein,
The shape of first linear pattern is in wave linear shape and extends along a first direction, the second linear pattern edge
The intersection composition crosspoint of second direction extension, second linear pattern and first linear pattern, the intersection
Peak dot or valley point of the point alignment in first linear pattern of wave linear shape, and in alignment with the peak dot in the crosspoint
Or the shape of the valley point is arc-shaped.
Optionally, in the mask plate, in the peak dot of first linear pattern of wave linear shape and described
The shape of valley point is arc-shaped, same in wave linear shape first linear pattern the peak dot in said first direction
In a linear rows arrangement and same in wave linear shape first linear pattern the valley point in said first direction
It is arranged in another linear rows.
Optionally, in the mask plate, the peak dot of multiple first linear patterns in wave linear shape exists
It is aligned in the second direction intersected with the second linear pattern described in same and is arranged in an alignment array, and multiple is in wave
The valley point of first linear pattern of shape is in the second direction intersected with the second linear pattern described in same
Alignment is arranged in another alignment array.
Optionally, in the mask plate, second linear pattern is rectilinear patterns.
Optionally, in the mask plate, the pattern of the mask plate is used to define the storage section in a memory
Point contact, wherein, the storage node contacts correspond to the crosspoint.
Optionally, in the mask plate, the pattern of the mask plate is additionally operable to define in the memory and institute
The capacitor of storage node contacts connection is stated, wherein, the capacitor corresponds to the crosspoint.
The utility model also provides a kind of memory, and the memory includes：
One substrate is formed with multiple active areas in the substrate, more is formed on the substrate and is extended in a first direction
Bit line structure and the more shielding wires extended in a second direction, institute's bit line structures include bit line conductors and the covering bit line
The bit line separation layer of conductor, institute's bit line structures and the shielding wire intersect and define multiple contact holes over the substrate,
And drain electrode one contact hole of alignment in the active area；
Multiple storage node contacts are filled the contact hole using a connecting material layer and are formed, and the memory node
Contact extends over the part of the bit line separation layer, and the connecting material layer has opening, and the opening is located at adjacent institute
Between stating storage node contacts, the opening, which is extended at the top of the connecting material layer in the bit line separation layer, also to be extended
To the shielding wire top surface so that the barbed portion of the sidewall sections of the storage node contacts, the bit line separation layer and
Shielding wire exposure in said opening, between the adjacent storage node contacts by the opening and the bit line every
Absciss layer mutually separates, the center of the corresponding contact hole of upper surface central point relative depature of the storage node contacts
Point；And
One node contact is isolated, and filling is in said opening.
Optionally, in the memory, the memory further includes：
Multiple capacitors, the capacitor are formed in the upper surface of the storage node contacts, and the bottom of the capacitor
Electrode is electrically connected with the storage node contacts, and the capacitor is in slim cylindrical.
In mask plate provided by the utility model and memory, mask plate includes the First Line extended along a first direction
Shape pattern and the second linear pattern extended along second direction, can be in first party thus during alignment between mask plate
To with carry out alignment in second direction both direction, so as to improve alignment precision.Further, mask plate can be used for being formed
In the manufacture of storage node contacts and capacitor, i.e. memory, two structures being connected can use the identical mask plate system of pattern
It makes, it is possible thereby to further improve the alignment precision of mask plate in former and later two steps, so as to also improve depositing of being formed
The q＆r of reservoir.
Description of the drawings
Fig. 1 is a kind of structure diagram for forming the mask plate of storage node contacts in memory；
Fig. 2 is the schematic top plan view using the memory after mask plate shown in FIG. 1 formation storage node contacts；
Fig. 3 is the schematic top plan view of substrate in memory shown in Fig. 2；
Fig. 4 is the diagrammatic cross-section of the substrate along AA ' in memory shown in Fig. 2；
Fig. 5 is that the structure diagram after connecting material layer is formed in structure shown in Fig. 4；
Fig. 6 is the structure diagram formed in the structure shown in Fig. 5 after the first photoresist layer；
Fig. 7 is to perform the structure diagram after photoetching process using mask plate shown in FIG. 1 to the structure shown in Fig. 6；
Fig. 8 is the structure diagram performed to structure shown in Fig. 7 after etching technics；
Fig. 9 is the structure diagram formed in structure shown in Fig. 8 after node contact isolation；
Figure 10 is a kind of structure diagram for forming the mask plate of capacitor in memory；
Figure 11 is that the structure diagram after dielectric layer and the second photoresist is formed in structure shown in Fig. 9；
Figure 12 is to perform the structure diagram after photoetching process using mask plate shown in Fig. 10 to structure shown in Fig. 9；
Figure 13 is the structure diagram performed to the structure shown in Figure 12 after etching technics；
Figure 14 is that the structure diagram after capacitor is formed in the structure shown in Figure 13；
Figure 15 is the structure diagram of the mask plate of the utility model embodiment；
Figure 16 is the schematic top plan view using the memory after the mask plate formation storage node contacts shown in Figure 15；
Figure 17 is the schematic top plan view of substrate in memory shown in Figure 16；
Figure 18 is the diagrammatic cross-section of the substrate along BB ' in memory described in Figure 16；
Figure 19 is that the structure diagram after connecting material layer is formed in the structure shown in Figure 18；
Figure 20 is the structure diagram formed in the structure shown in Figure 19 after the first photoresist layer；
Figure 21 is to perform the structure diagram after photoetching process using the mask plate shown in Figure 15 to the structure shown in Figure 20；
Figure 22 is the structure diagram performed to the structure shown in Figure 21 after etching technics；
Figure 23 is the structure diagram formed in the structure shown in Figure 22 after node contact isolation；
Figure 24 is that the structure diagram after dielectric layer and the second photoresist layer is formed in the structure shown in Figure 23；
Figure 25 is to perform the structure diagram after photoetching process using the mask plate shown in Figure 15 to the structure shown in Figure 24；
Figure 26 is the structure diagram performed to the structure shown in Figure 25 after etching technics；
Figure 27 is that the structure diagram after capacitor is formed in the structure shown in Figure 26；
Wherein,
100- mask plates；110- substrates；
120- storage node contacts patterns；200- substrates；
210- active areas；211- drains；
The active isolation structures of 212-；220- bit line structures；
221- bit line conductors；222- bit line separation layers；
230- shielding wires；240- contact holes；
250- connecting material layers；The first photoresist layers of 260-；
261- first patterns photoresist layer；270- storage node contacts；
280- first is open；290- node contacts are isolated；
300- mask plates；310- substrates；
The first capacitor patterns of 320-；The second capacitor patterns of 330-；
340- crosspoints；400- dielectric layers；
The second photoresist layers of 410-；411- second patterns photoresist layer；
420- second is open；430- capacitors；
431- hearth electrodes；432- Capacitor aparts；
433- top electrodes；500- mask plates；
510- substrates；The first linear patterns of 520-；
The second linear patterns of 530-；540- crosspoints；
600- substrates；610- active areas；
611- drains；The active isolation structures of 612-；
620- bit line structures；621- bit line conductors；
622- bit line separation layers；630- shielding wires；
640- contact holes；650- connecting material layers；
The first photoresist layers of 660-；661- first patterns photoresist layer；
The first lithographic openings of 662-；670- storage node contacts；
680- first is open；690- node contacts are isolated；
700- dielectric layers；The second photoresist layers of 710-；
711- second patterns photoresist layer；The second lithographic openings of 712-；
720- second is open；730- capacitors；
731- hearth electrodes；732- Capacitor aparts；
733- top electrodes；T1- first directions；
T2- second directions；T3- third directions.
Specific embodiment
First, please refer to Fig.1, be a kind of structure diagram for forming the mask plate of storage node contacts in memory.
As shown in Figure 1, the mask plate 100 includes：One substrate 110, the substrate 110 have multiple storage node contacts patterns 120,
The storage node contacts pattern 120 is rounded.
Then, please refer to Fig.2 to Fig. 8, wherein, after Fig. 2 forms storage node contacts using mask plate shown in FIG. 1
The schematic top plan view of memory；Fig. 3 is the schematic top plan view of substrate in memory shown in Fig. 2；Fig. 4 is storage shown in Fig. 2
In device along AA ' substrate diagrammatic cross-section；Fig. 5 is that the structure in structure shown in Fig. 4 after formation connecting material layer is shown
It is intended to；Fig. 6 is the structure diagram formed in the structure shown in Fig. 5 after the first photoresist layer；Fig. 7 is to the knot shown in Fig. 6
Structure performs the structure diagram after photoetching process using mask plate shown in FIG. 1；Fig. 8 is to perform etching to structure shown in Fig. 7
Structure diagram after technique.
As shown in Fig. 2 to Fig. 8, specifically included using the step of formation storage node contacts of mask plate 100：
First, as shown in Figures 2 to 4, a substrate 200 is provided, multiple active areas 210, institute are formed in the substrate 200
State be formed on substrate 200 more along the first direction T1 extension bit line structures 220 and more in a second direction T2 extension every
Offline 230, institute's bit line structures 220 include bit line conductors 221 and cover the bit line separation layer 222 of institute's bit line conductors 221, phase
Adjacent institute's bit line structures 220 and the adjacent shielding wire 230 surround multiple contact holes 240, and one in the active area 210
211 one contact hole 240 of alignment of drain electrode.Wherein, active isolation structure 212 can be passed through between the adjacent active area 210
Isolated.In the embodiment of the present application, the shielding wire 230 is directed at wordline (not shown).
Then, as shown in figure 5, forming a connecting material layer 250 on the substrate 200, the connecting material layer 250 is filled out
Fill the contact hole 240, and cover institute's bit line structures 220 and the shielding wire 230, the connecting material layer 250 with it is described
The electrical connection in the contact hole 240 of drain electrode 211.
As shown in fig. 6, one first photoresist layer 260 of covering is on the connecting material layer 250.
Then, as shown in fig. 7, performing photoetching process, institute to first photoresist layer 260 using the mask plate 100
It states and the part of storage node contacts pattern 120 in the mask plate 100 is corresponded in the first photoresist layer 260 is retained, it is described
Remaining part is removed in first photoresist layer 260, forms one first patterning photoresist layer 261.
Then, as shown in figure 8, being mask with the described first patterning photoresist layer 261, the connecting material layer is etched
250 and the bit line separation layer 222, etching stopping neutralized in the connecting material layer 250 in the bit line separation layer 222, with
Form multiple storage node contacts 270 and one first opening 280 between the storage node contacts 270.Then,
Remove the first patterning photoresist layer 261.
Then, Fig. 9 is refer to, is the structure diagram formed in structure shown in Fig. 8 after node contact isolation.
In the embodiment of the present application, further included in the forming process of the storage node contacts：Node contact isolation 290 is filled in described
In first opening 280.
In a kind of manufacturing method of memory, then, capacitor is formed using mask plate as shown in Figure 10.First,
0 is please referred to Fig.1, is a kind of structure diagram for forming the mask plate of capacitor in memory.As shown in Figure 10, the mask
Version 300 includes：One substrate 310, the substrate 310 have multiple first capacitor patterns 320 and multiple second capacitor patterns
330；First capacitor pattern 320 extends for rectilinear patterns and along third direction T3；Second capacitor pattern
330 extend for rectilinear patterns and along second direction T2, second capacitor pattern 330 and first capacitor pattern
320 intersection forms crosspoint 340.
Wherein, the crosspoint 340 corresponds to the storage node contacts pattern 120 in the mask plate 100.Here,
It is corresponded to when forming capacitor by the mask plate 300, it is necessary to which crosspoint 340 is aligned the storage node contacts pattern 120
Position, that is, be directed at the storage node contacts 270, and since the 120 corresponding position of storage node contacts pattern is one
A rounded point, this is extremely difficult in alignment, that is, improves the alignment difficulty of the mask plate 300, reduce institute
State the alignment precision of mask plate 300.
In addition, in the mask plate 300, first capacitor pattern 320 and second capacitor pattern 330 are equal
For rectilinear patterns, the friendship that first capacitor pattern 320 and 330 intersection of the second capacitor pattern are formed as a result,
Crunode 340 is by with very sharp shape, so as to form the storage node contacts by the crosspoint 340
270 (can cause the adjacent storage node contacts 270 to be formed easily to be connected, so as to reduce formed storage
The reliability of device).
After the node contact isolation 290 is formd, electricity is then formed as follows using mask plate 300
Container.Specifically, 1 is please referred to Fig.1 to Figure 14, wherein, Figure 11 is that dielectric layer and the second photoetching are formed in structure shown in Fig. 9
Structure diagram after glue；Figure 12 is to perform the knot after photoetching process using mask plate shown in Fig. 10 to structure shown in Fig. 9
Structure schematic diagram；Figure 13 is the structure diagram performed to the structure shown in Figure 12 after etching technics；Figure 14 is shown in Figure 13
The structure diagram after capacitor is formed in structure.
As shown in figure 11, a dielectric layer 400 is formed on the substrate 200, and the dielectric layer 400 covers the storage section
Point contact 270 and node contact isolation 290.
Then, with continued reference to Figure 11, one second photoresist layer 410 of covering is on the dielectric layer 400.
Then, as shown in figure 12, photoetching process is performed to second photoresist layer 410 using the mask plate 300, gone
Except the part in the crosspoint 340 that the mask plate 300 is corresponded in second photoresist layer 410, one second pattern is formed
Change photoresist layer 411.
As shown in figure 13, it is mask with the described second patterning photoresist layer 411, etches the dielectric layer 400 to be formed
One second opening 420, second opening 420 is through the dielectric layer 400 and exposes the storage node contacts 270.Here,
Then the second patterning photoresist layer 411 is removed.
Then, as shown in figure 14, a hearth electrode 431 is filled in the described second opening 420.With continued reference to Figure 14, successively
A Capacitor apart 432 and a top electrode 433 are formed on the hearth electrode 431, to form the capacitor 430.It is here, described
Projection parallelogram of the capacitor 430 on the substrate 200.
In above-mentioned formation storage node contacts 270 and the manufacturing process of capacitor 430, it is primarily present to form capacitor
430 mask plate 300 is difficult 100 alignment of mask plate with forming storage node contacts 270, resulting capacitor 430
Often there are certain deviation between storage node contacts 270, so as to cause the quality of finally formed memory and reliable
Property reduce.Simultaneously as the shape of storage node contacts 270 can not be too sharp, therefore it also is difficult to be formed by mask plate 300
Storage node contacts 270.That is, the mask plate 300 for forming capacitor 430 is difficult the mask plate with forming storage node contacts 270
The problem of 100 alignment, is difficult to be solved.
On this basis, the utility model provides a kind of mask plate, and the mask plate includes：
One substrate has multiple first linear patterns and multiple second linear patterns on the substrate；Wherein,
The shape of first linear pattern is in wave linear shape and extends along a first direction, the second linear pattern edge
The intersection composition crosspoint of second direction extension, second linear pattern and first linear pattern, the intersection
Peak dot or valley point of the point alignment in first linear pattern of wave linear shape, and in alignment with the peak dot in the crosspoint
Or the shape of the valley point is arc-shaped.
Correspondingly, the utility model also provides a kind of method using above-mentioned mask plate manufacture memory and corresponding gained
The memory arrived.
In the manufacturing method of mask plate provided by the utility model, memory and memory, mask plate is included along the
First linear pattern of one direction extension and the second linear pattern extended along second direction, the thus set between mask plate
On time, can in a first direction with carry out alignment in second direction both direction, so as to improve alignment precision.Further,
Mask plate can be used for forming storage node contacts and capacitor, i.e., in memory manufacture, two structures being connected can be used
The identical mask plate manufacture of pattern, it is possible thereby to the alignment precision of mask plate in former and later two steps is further improved, so as to
Also improve the q＆r of formed memory.
Subsequently, by with reference to attached drawing to the utility model proposes mask plate, memory and memory manufacturing method work
It is further described.According to following explanation and claims, will be become apparent from feature the advantages of the utility model.It needs to illustrate
, attached drawing using very simplified form and using non-accurate ratio, only to it is convenient, lucidly aid in illustrating this
The purpose of utility model embodiment.
First, 5 are please referred to Fig.1, is the structure diagram of the mask plate of the utility model embodiment.As shown in figure 15,
The mask plate 500 includes：One substrate 510 has multiple first linear patterns 520 and multiple second lines on the substrate 510
Shape pattern 530；Wherein, the shape of first linear pattern 520 is in wave linear shape and T1 extensions along a first direction, and described the
Two linear patterns 530 extend along second direction T2, the phase of second linear pattern 530 and first linear pattern 520
Crosspoint 540, peak dot or paddy of the alignment of crosspoint 540 in first linear pattern 520 of wave linear shape are formed at friendship
Point, and the peak dot in alignment with the crosspoint 540 or the shape of the valley point are arc-shaped.
Specifically, it is arc-shaped in the peak dot and the valley point of first linear pattern 520 of wave linear shape, together
One in wave linear shape first linear pattern 520 the peak dot in said first direction in a linear rows arrangement and
Same is arranged in the valley point of first linear pattern 520 of wave linear shape in another linear rows in said first direction
Row.That is, same is in the linear rows and same that the peak dot of first linear pattern 520 of wave linear shape is formed
Another linear rows formed in the valley point of first linear pattern 520 of wave linear shape are mutually parallel.Here, in ripple
The peak dot of linear first linear pattern 520 of wave and the valley point are arc-shaped, i.e., in described the of wave linear shape
The bending place of one linear pattern 520 is arc-shaped.
Further, the peak dot of multiple first linear patterns 520 in wave linear shape with described in same
Alignment is arranged in an alignment array in the intersecting second direction of second linear pattern 530, and multiple in the described of wave linear shape
The valley point of first linear pattern 520 is right in the second direction intersected with the second linear pattern 530 described in same
Standard is arranged in another alignment array.In the embodiment of the present application, the peak dot of multiple first linear patterns 520 in wave linear shape
It is in multiple parallel to alignment array arrangement and multiple first linear patterns 520 in wave linear shape in this second direction
Valley point is in this second direction in multiple parallel to alignment array arrangement.Further, second linear pattern 530 is right
One row of the standard peak dot or an one row valley point of the alignment of the second linear pattern 530.
Please continue to refer to Figure 15, in the embodiment of the present application, second linear pattern 530 is rectilinear patterns.
In the embodiment of the present application, the pattern of the mask plate 500 can be used for defining storage node contacts and capacitance
Device.Wherein, when the mask plate 500 is used for defining storage node contacts, the storage node contacts correspond to the intersection
Point；When the mask plate 500 is used for defining capacitor, the capacitor corresponds to the crosspoint.
Correspondingly, the utility model also provides a kind of manufacturing method of memory, the manufacturing method of the memory includes
Storage node contacts are formed using above-mentioned mask plate 500；Further, the manufacturing method of the memory is further included using above-mentioned
Mask plate 500 forms capacitor.
Specifically, 6 are please referred to Fig.1 to Figure 27, wherein, Figure 16 is to form memory node using the mask plate shown in Figure 15 to connect
The schematic top plan view of memory after touch；Figure 17 is the schematic top plan view of substrate in memory shown in Figure 16；Figure 18 is Figure 16
In the memory along BB ' substrate diagrammatic cross-section；Figure 19 is to form connecting material in the structure shown in Figure 18
Structure diagram after layer；Figure 20 is the structure diagram formed in the structure shown in Figure 19 after the first photoresist layer；Figure 21
It is to perform the structure diagram after photoetching process using the mask plate shown in Figure 15 to the structure shown in Figure 20；Figure 22 is to Figure 21
Shown structure performs the structure diagram after etching technics；Figure 23 is that node contact isolation is formed in the structure shown in Figure 22
Structure diagram afterwards；Figure 24 is that the structural representation after dielectric layer and the second photoresist layer is formed in the structure shown in Figure 23
Figure；Figure 25 is to perform the structure diagram after photoetching process using the mask plate shown in Figure 15 to the structure shown in Figure 24；Figure 26
It is the structure diagram performed to the structure shown in Figure 25 after etching technics；Figure 27 is to form capacitance in the structure shown in Figure 26
Structure diagram after device.
First, 6 to Figure 18 are please referred to Fig.1, a substrate 600 is provided, multiple active areas 610 are formed in the substrate 600,
The more bit line structures extended in a first direction 620 and the more isolation extended in a second direction are formed on the substrate 600
Line 630, institute's bit line structures 620 include bit line conductors 621 and cover the bit line separation layer 622 of institute's bit line conductors 621, described
Bit line structure 620 and the shielding wire 630 intersect on the substrate 600 and define multiple contact holes 640, and described active
611 one contact hole 640 of alignment of a drain electrode in area 610.Here, by active between the adjacent active area 610
Isolation structure 612 is isolated.In the embodiment of the present application, the shielding wire 630 is directed at wordline (not shown).
Then, as shown in figure 19, a connecting material layer 650 is formed on the substrate 600, the connecting material layer 650
The contact hole 640 is filled, and covers institute's bit line structures 620 and the shielding wire 630, the connecting material layer 650 and institute
State the electrical connection in the contact hole 640 of drain electrode 611.Preferably, the connecting material layer can be metal or polysilicon.
In the embodiment of the present application, chemical vapor deposition (CVD) technique can be first passed through and form a connecting material layer 650 in the substrate 600
On；Then the connecting material layer 650, then by flatening process is handled, to improve the flat of 650 surface of connecting material layer
Whole degree, wherein, the flatening process can be chemical mechanical grinding (CMP) technique or etching technics.
Then, 0 is please referred to Fig.2, one first photoresist layer 660 of covering is on the connecting material layer 650.Wherein, it is described
First photoresist layer 660 can be formed by spin coating proceeding.
Then, 1 is please referred to Fig.2, photoetching process is performed to first photoresist layer 660 using the first mask plate, it is described
First mask plate employs above-mentioned mask plate 500, retains the institute that the mask plate 500 is corresponded in first photoresist layer 660
The part in crosspoint 540 is stated, that is, removes rest part in first photoresist layer 660, to form one there is the first photoetching to open
First patterning photoresist layer 661 of mouth 662, first lithographic opening 662 expose the part connecting material layer 650,
And part, the bitline junction of projection and the contact hole 640 of first lithographic opening 662 on the substrate 600
620 part of structure and the shielding wire 630 are overlapped, i.e., projection of the described first patterning photoresist layer 661 on the substrate 600
It is Chong Die with another part and institute's 620 another part of bit line structures of the contact hole 640.I.e. described first lithographic opening 662
The part of the connecting material layer 650 is exposed, first lithographic opening 662 is against the part contact hole 640 and extends
Also extend against the shielding wire 630 against part institute bit line structures 620.
As shown in Figure 16 and Figure 22, then, it is mask with the described first patterning photoresist layer 661, etches the connection
Material layer 650 and the bit line separation layer 622, and etching stopping neutralizes the bit line separation layer in the connecting material layer 650
To the top surface of the shielding wire 630 in 622, to be formed and first lithographic opening 662 corresponding first opening 680, institute
It states the part being filled in respectively in connecting material layer 650 in the adjacent contact hole 640 and passes through the described first opening 680 and institute
Rheme line separation layer 622 mutually separates, to form the storage node contacts 670.That is, 500 shape of mask plate is utilized
Into storage node contacts 670.
Here, the storage node contacts 670 fill the contact hole 640 and extend over part institute bit line structures
620；First opening 680, which exposes the part storage node contacts 670 and extends, exposes the part bit line isolation
The also extension of layer 622 exposes the shielding wire 630.
Please continue to refer to Figure 22, in the embodiment of the present application, then, removal described first patterns photoresist layer 661.Tool
Body, the first patterning photoresist layer 661 can be removed by stripping technology.
Then, as shown in figure 23, in the embodiment of the present application, the manufacturing method of the memory further includes：One section of filling
Point contact isolation 690 is in the described first opening 680.Wherein, node contact isolation 690 specifically can shape as follows
Into：A spacer material layer is formed on the substrate 600, the spacer material layer fills first opening 680 and covers institute
State storage node contacts 670；Then, consumed by grinding or etching technics described in the thickness to exposing of the spacer material layer
Storage node contacts 670, so as to form the node contact isolation 690 in the described first opening 680.
In the embodiment of the present application, the manufacturing method of the memory further comprises forming capacitance using mask plate 500
Device, the capacitor are electrically connected with the storage node contacts 670.
Specifically, please referring to Fig.2 4, then, a dielectric layer 700 is formed on the substrate 600, the dielectric layer 700 covers
Cover the storage node contacts 670 and node contact isolation 690.Wherein, the material of the dielectric layer 700 can be nitridation
Silicon, silica or silicon oxynitride etc..
Please continue to refer to Figure 24, further, one second photoresist layer 710 of covering is on the dielectric layer 700.Described
Two photoresist layers 710 can specifically be formed by spin coating proceeding.
Then, as shown in figure 25, photoetching process is performed to second photoresist layer 710 using the second mask plate, it is described
Second mask plate employs above-mentioned mask plate 500, removes the institute that the mask plate 500 is corresponded in second photoresist layer 710
The part in crosspoint 540 is stated, there is the second patterning photoresist layer 711 of multiple second lithographic openings 712 to form one, it is described
Second lithographic opening 712 exposes the part dielectric layer 700, and second lithographic opening 712 is directed at the storage section
Point contact 670.
Here, due to exposing the second mask plate used in second photoresist layer 710 with forming the memory node
First reticle pattern used in contact 670 is identical, i.e., identical with the mask plate 500, is utilizing the mask as a result,
When 500 pairs of second photoresist layers 710 of version perform exposure technology, the mask plate 500 can easily with it is preceding together with expose
Light technique alignment, so as to improve the precision of current exposure technique.Particularly, the mask plate 500 is included along first party
The first linear pattern 510 to extension and the second linear pattern 520 along second direction extension, thus between mask plate
During alignment, can in a first direction with carry out alignment in second direction both direction, so as to improve alignment precision.
Then, as shown in figure 26, with described second patterning photoresist layer 711 be mask, etch the dielectric layer 700 with
One second opening 720 is formed, second opening 720 is through the dielectric layer 700 and exposes the storage node contacts 670.
As shown in figure 27, then, a hearth electrode 731 is filled in the described second opening 720.Specifically, the hearth electrode
731 can be realized by following processing step：A conductive layer is formed on the substrate 200, the conductive layer fills described second
Opening 720 simultaneously covers the dielectric layer 700；Then, the conductive layer can be removed by etching technics and is located at the dielectric layer 700
On part, so as to described second opening 720 in formed hearth electrodes 731.The hearth electrode 731 is formed in the memory node
The upper surface of contact 670, and be electrically connected with the storage node contacts 670.
Please continue to refer to Figure 27, then, a Capacitor apart 732 and a top electrode 733 are sequentially formed in the hearth electrode 731
On, to form the capacitor 730.In the embodiment of the present application, the Capacitor apart 732 fills second opening 720 simultaneously
The dielectric layer 700 is covered, the top electrode 733 covers the Capacitor apart 732.In the other embodiment of the application, institute
Second opening 732 can be only filled with by stating Capacitor apart 732, and the top electrode 733 covers the Capacitor apart 732.It is here, sharp
The capacitor 730 is formed with the mask plate 500 identical with forming the storage node contacts 670, so as to improve
The alignment precision of front and rear twice photoetching process.
Correspondingly, the utility model also provides a kind of memory, specifically, please continue to refer to Figure 27.
As shown in figure 27, the memory includes：
One substrate 600 is formed with multiple active areas 610 in the substrate 600, more edges is formed on the substrate 600
The bit line structure 620 of first direction T1 extensions and the more shielding wires 630 that T2 extends in a second direction, institute's bit line structures 620
Bit line separation layer 622 including bit line conductors 621 and covering institute bit line conductors 621, institute's bit line structures 620 and the isolation
Line 630 intersects on the substrate 600 and defines multiple contact holes 640, and a drain electrode 611 in the active area 610
It is directed at a contact hole 640；
Multiple storage node contacts 670 are filled the contact hole 640 using a connecting material layer and are formed, and described deposit
Storage node contact 670 extends over the part of the bit line separation layer 622, and the connecting material layer has opening 680 (i.e. first
680), for first opening 680 positioned at the adjacent storage node contacts 670 between, described first is open 680 from institute to opening
The top surface for being extended at the top of connecting material layer in the bit line separation layer 622 and also extending to the shielding wire 630 is stated, so that institute
The sidewall sections of storage node contacts 670, the barbed portion of the bit line separation layer 622 and the shielding wire 630 is stated to be exposed to
In first opening 680, pass through the described first opening 680 and the bit line between the adjacent storage node contacts 670
Separation layer 622 mutually separates, the corresponding contact of upper surface central point relative depature of the storage node contacts 670
The central point of window 640；And
One node contact isolation 690 is filled in first opening 680.
The resulting storage node contacts 670 have smooth border, thus the adjacent memory node
Contact 670 can be good at being isolated, so as to improve the reliability of formed memory.
Further, the memory further includes：Multiple capacitors 730, the capacitor 730 are formed in the storage section
The upper surface of point contact 670, and the hearth electrode 731 of the capacitor 730 is electrically connected with the storage node contacts 670, it is described
Capacitor 730 is in slim cylindrical.Here, a pair of of the border of the capacitor 730 in this second direction is arc-shaped, the electricity
A pair of of the border of container 730 in said first direction is linear.
To sum up, in the manufacturing method of mask plate provided by the utility model, memory and memory, mask plate bag
The first linear pattern extended along a first direction and the second linear pattern extended along second direction are included, thus in mask plate
Between alignment when, can in a first direction with carry out alignment in second direction both direction, so as to improve alignment precision.Into
One step, mask plate can be used for forming storage node contacts and capacitor, i.e., in memory manufacture, two structures being connected
It can be manufactured with the identical mask plate of pattern, it is possible thereby to further improve the alignment essence of mask plate in former and later two steps
Degree, so as to also improve the q＆r of formed memory.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Calmly, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content, belonging to right will
Seek the protection domain of book.
Claims (8)
1. a kind of mask plate, which is characterized in that the mask plate includes：
One substrate has multiple first linear patterns and multiple second linear patterns on the substrate；Wherein,
The shape of first linear pattern in wave linear shape and extending along a first direction, and second linear pattern is along the
Two directions extend, and the intersection of second linear pattern and first linear pattern forms crosspoint, the crosspoint pair
Peak dot or valley point of the standard in first linear pattern of wave linear shape, and the peak dot in alignment with the crosspoint or institute
The shape for stating valley point is arc-shaped.
2. mask plate as described in claim 1, which is characterized in that in the peak of first linear pattern of wave linear shape
The shape of point and the valley point is arc-shaped, and same is in the peak dot of first linear pattern of wave linear shape described the
On one direction in linear rows arrangement and same in the valley point of first linear pattern of wave linear shape described the
It is arranged on one direction in another linear rows.
3. mask plate as claimed in claim 2, which is characterized in that the institute of multiple first linear patterns in wave linear shape
It is in that an alignment array arranges to state peak dot and be aligned in the second direction intersected with the second linear pattern described in same, and multiple
In wave linear shape first linear pattern the valley point in described intersected with the second linear pattern described in same
Alignment is arranged in another alignment array on two directions.
4. mask plate as described in claim 1, which is characterized in that second linear pattern is rectilinear patterns.
5. such as mask plate according to any one of claims 1 to 4, which is characterized in that the pattern of the mask plate is used to define
Go out the storage node contacts in a memory, wherein, the storage node contacts correspond to the crosspoint.
6. mask plate as claimed in claim 5, which is characterized in that the pattern of the mask plate is additionally operable to define the storage
The capacitor being connected in device with the storage node contacts, wherein, the capacitor corresponds to the crosspoint.
7. a kind of memory, which is characterized in that the memory includes：
One substrate is formed with multiple active areas in the substrate, the more positions extended in a first direction is formed on the substrate
Cable architecture and the more shielding wires extended in a second direction, institute's bit line structures include bit line conductors and covering institute bit line conductors
Bit line separation layer, institute's bit line structures and the shielding wire intersect and define multiple contact holes, and institute over the substrate
State drain electrode one contact hole of alignment in active area；
Multiple storage node contacts are filled the contact hole using a connecting material layer and are formed, and the storage node contacts
Extend over the part of the bit line separation layer, the connecting material layer has an opening, and the opening is located at adjacent described deposit
Between storing up node contact, the opening, which is extended at the top of the connecting material layer in the bit line separation layer, also extends to institute
The top surface of shielding wire is stated, so that the barbed portion of the sidewall sections of the storage node contacts, the bit line separation layer and described
Shielding wire exposes in said opening, passes through the opening and the bit line separation layer between the adjacent storage node contacts
Mutually separate, the central point of the corresponding contact hole of upper surface central point relative depature of the storage node contacts；
And
One node contact is isolated, and filling is in said opening.
8. memory as claimed in claim 7, which is characterized in that the memory further includes：
Multiple capacitors, the capacitor are formed in the upper surface of the storage node contacts, and the hearth electrode of the capacitor
It is electrically connected with the storage node contacts, the capacitor is in slim cylindrical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721490289.5U CN207408737U (en) | 2017-11-09 | 2017-11-09 | Mask plate and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721490289.5U CN207408737U (en) | 2017-11-09 | 2017-11-09 | Mask plate and memory |
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| Publication Number | Publication Date |
|---|---|
| CN207408737U true CN207408737U (en) | 2018-05-25 |
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ID=62318531
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721490289.5U Active CN207408737U (en) | 2017-11-09 | 2017-11-09 | Mask plate and memory |
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| CN (1) | CN207408737U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022077959A1 (en) * | 2020-10-15 | 2022-04-21 | 长鑫存储技术有限公司 | Memory and manufacturing method therefor |
| CN114815490A (en) * | 2021-01-27 | 2022-07-29 | 中芯国际集成电路制造(上海)有限公司 | Mask layout, memory cell structure and memory |
-
2017
- 2017-11-09 CN CN201721490289.5U patent/CN207408737U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022077959A1 (en) * | 2020-10-15 | 2022-04-21 | 长鑫存储技术有限公司 | Memory and manufacturing method therefor |
| CN114815490A (en) * | 2021-01-27 | 2022-07-29 | 中芯国际集成电路制造(上海)有限公司 | Mask layout, memory cell structure and memory |
| CN114815490B (en) * | 2021-01-27 | 2024-03-08 | 中芯国际集成电路制造(上海)有限公司 | Mask layout, memory cell structure and memory |
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Effective date of registration: 20181017 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |
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