CN107845633B - Memory and manufacturing method thereof - Google Patents
Memory and manufacturing method thereof Download PDFInfo
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- CN107845633B CN107845633B CN201711038988.0A CN201711038988A CN107845633B CN 107845633 B CN107845633 B CN 107845633B CN 201711038988 A CN201711038988 A CN 201711038988A CN 107845633 B CN107845633 B CN 107845633B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
The invention provides a memory and a manufacturing method thereof, wherein a contact isolation layer is formed firstly, and then a storage node contact is formed, so that the contact isolation layer can well isolate adjacent storage node contacts, and the reliability of the formed memory is improved. Further, the storage node contacts correspond to the contact windows and extend into the bit line structure in an offset manner, so that the storage node contacts have a larger section width, the storage node contacts have a smaller resistance value, and the quality of the storage node contacts is improved. Meanwhile, the storage node contacts the corresponding contact window and extends to the bit line structure in an offset manner, so that a capacitor formed subsequently has a larger process window, and the process difficulty is reduced.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a memory and a manufacturing method thereof.
Background
A memory typically includes a capacitor to store data and a transistor to control access to the data stored in the capacitor. Specifically, a word line (word line) of the memory is electrically connected to the gate of the transistor, the word line controlling the switching of the transistor; and, the source of the transistor is electrically connected to a bit line structure (bit line) to form a current transmission path; meanwhile, the drain electrode of the transistor is electrically connected to the capacitor so as to achieve the purpose of data storage or output. Wherein the drain of the transistor is typically electrically connected to the capacitor through a storage node contact, the quality of the storage node contact, e.g. the resistance of the storage node contact, will greatly affect the quality of the formed memory.
Therefore, how to form high quality storage node contacts is a very important issue in the art.
Disclosure of Invention
An object of the present invention is to provide a memory and a method of manufacturing the same, the method of manufacturing the memory including:
providing a substrate, wherein a plurality of active areas are formed in the substrate, a plurality of bit line structures extending along a first direction and a plurality of isolation lines extending along a second direction are formed on the substrate, a plurality of contact windows are formed by surrounding adjacent bit line structures and adjacent isolation lines, and one drain electrode in the active areas is aligned to one contact window;
aligning and filling a first storage node contact structure in the contact window on the substrate, wherein the first storage node contact structure is electrically connected with the drain electrode;
forming a contact isolation layer on the substrate, wherein the contact isolation layer covers the first storage node contact structure, the bit line structure and the isolation line;
etching a part of the contact isolation layer which is positioned above the first storage node contact structures to form a plurality of openings, wherein the openings penetrate through the contact isolation layer to expose the first storage node contact structures, and each first storage node contact structure corresponds to one opening; a kind of electronic device with high-pressure air-conditioning system
And filling a second storage node contact structure in the opening, wherein the second storage node contact structure is electrically connected with the first storage node contact structure to form a storage node contact.
Optionally, in the method for manufacturing a memory, the bit line structure includes a bit line conductor and a bit line isolation layer covering the bit line conductor, and the method for forming the opening includes:
and etching a part of the contact isolation layer above the first storage node contact structure and a part of the contact isolation layer above the bit line structure to form the opening, wherein the opening corresponds to the first storage node contact and extends into the bit line structure in an offset manner, so that the opening is further provided with a part overlapped with the bit line structure to simultaneously expose the first storage node contact and the bit line isolation layer in the bit line structure.
Optionally, in the method for manufacturing a memory, in the step of forming the opening, the method further includes:
after etching the contact isolation layer to expose the first storage node contact structure and the bit line structure, then etching the bit line isolation layer in the first storage node contact structure and the bit line structure to partially remove the first storage node contact structure and the bit line isolation layer, and etching stopping in the first storage node contact structure and the bit line isolation layer.
Optionally, in the method for manufacturing a memory, the second storage node contact structure is partially embedded in a depth direction and is partially connected to the first storage node contact structure in an upward protruding manner; the first storage node contact structure is aligned non-centrally in the width direction, and is partially embedded and partially laterally connected to the first storage node contact structure in a protruding manner.
Optionally, in the method for manufacturing the memory, the storage node contact corresponds to the contact window and extends into the bit line structure in an offset manner, wherein a top surface of the storage node contact is flush with or lower than a top surface of the contact isolation layer, and a bottom surface of the storage node contact extends into the bit line structure higher than a top surface of the bit line conductor.
Optionally, in the method for manufacturing a memory, a plurality of word lines extending in the second direction are further formed in the substrate, and the isolation lines are aligned with the word lines.
Optionally, in the method for manufacturing a memory, the step of forming the first storage node contact structure includes:
forming a first connecting material layer on the substrate, wherein the first connecting material layer covers the contact window, the bit line structure and the isolation line;
the thickness of the first connection material layer is consumed in one selected from grinding, etching and a combination of the two to expose the bit line structure and the isolation line so as to form the first storage node contact structure.
Optionally, in the method for manufacturing a memory, the first storage node contact structure is a single-layer structure or a multi-layer stacked structure, and a material of each layer in the first storage node contact structure is selected from one of polysilicon and metal.
Optionally, in the method for manufacturing a memory, the step of forming the second storage node contact structure includes:
forming a second connecting material layer on the substrate, wherein the second connecting material layer fills the opening and covers the contact isolation layer;
and consuming the thickness of the second connecting material layer in a grinding manner until the contact isolation layer is exposed so as to form the second storage node contact structure.
Optionally, in the method for manufacturing a memory, the material of the second storage node contact structure is metal.
The present invention also provides a memory comprising:
the semiconductor device comprises a substrate, a plurality of active regions, a plurality of isolation lines, a plurality of first drain electrodes and a plurality of first source electrodes, wherein the substrate is internally provided with a plurality of active regions, a plurality of bit line structures extending along a first direction and a plurality of isolation lines extending along a second direction are formed on the substrate, a plurality of contact windows are formed by surrounding adjacent bit line structures and adjacent isolation lines, and one drain electrode of the active regions is aligned with one contact window;
a first storage node contact structure filled in the contact window on the substrate and electrically connected with the drain electrode;
a contact isolation layer on the substrate and partially covering the first storage node contact structure and the bit line structure, wherein the area of the contact isolation layer not covered by the first storage node contact and the bit line structure is used for forming a plurality of openings penetrating the contact isolation layer, and one first storage node contact structure is correspondingly and locally exposed in one opening; a kind of electronic device with high-pressure air-conditioning system
And a second storage node contact structure filled in the opening, the second storage node contact structure being electrically connected with the first storage node contact structure to form a storage node contact.
Optionally, in the memory, the opening is contacted with the first storage node and extends into the bit line structure in a layer offset manner, so that the opening is further provided with a part overlapped with the bit line structure, and the first storage node is contacted with the bit line isolation layer in the bit line structure at the same time.
Optionally, in the memory, a bottom of the opening extends into the first storage node contact structure and into the bit line isolation layer of the bit line structure.
Optionally, in the memory, the second storage node contact structure is partially embedded in a depth direction and is partially connected to the first storage node contact structure in an upward protruding manner; the first storage node contact structure is aligned non-centrally in the width direction, and is partially embedded and partially laterally connected to the first storage node contact structure in a protruding manner.
Optionally, in the memory, the storage node contact corresponds to the contact window and extends into the bit line structure in an offset manner, wherein a top surface of the storage node contact is flush with or lower than a top surface of the contact isolation layer, and a bottom surface of the storage node contact extends into the bit line structure higher than a top surface of the bit line conductor.
Optionally, in the memory, a plurality of word lines extending along the second direction are further formed in the substrate, and the isolation lines are aligned with the word lines.
In the memory and the manufacturing method thereof provided by the invention, the contact isolation layer is formed firstly and then the memory node contact is formed, so that the contact isolation layer can well isolate the adjacent memory node contact, and the reliability of the formed memory is improved. Further, the storage node contacts correspond to the contact windows and extend into the bit line structure in an offset manner, so that the storage node contacts have a larger section width, the storage node contacts have a smaller resistance value, and the quality of the storage node contacts is improved. Meanwhile, the storage node contacts the corresponding contact window and extends to the bit line structure in an offset manner, so that a capacitor formed subsequently has a larger process window, and the process difficulty is reduced.
Drawings
FIG. 1 is a flow chart of a method of manufacturing a memory;
FIG. 2 is a schematic top view of a memory;
FIG. 3 is a schematic cross-sectional view of the memory shown in FIG. 2 along the line AA' of the substrate;
FIG. 4 is a schematic cross-sectional view of a layer of bonding material formed on the substrate shown in FIG. 3;
FIG. 5 is a schematic cross-sectional view of the structure of FIG. 4 after performing a patterned etch process thereon;
FIG. 6 is a schematic cross-sectional view of the structure depicted in FIG. 5 after forming a contact spacer thereon;
FIG. 7 is a flow chart of a memory manufacturing method according to an embodiment of the invention;
FIG. 8 is a schematic top view of a memory according to an embodiment of the invention;
FIG. 9 is a schematic top view of an embodiment of the invention without isolation lines formed on the substrate;
FIG. 10 is a schematic top view of an isolation line formed on a substrate in accordance with an embodiment of the present invention;
FIG. 11 is a schematic cross-sectional view of the substrate along BB' of the substrate shown in FIG. 10;
FIG. 12 is a schematic cross-sectional view of the substrate shown in FIG. 11 after forming a first storage node contact structure thereon;
FIG. 13 is a schematic cross-sectional view of the substrate shown in FIG. 11 after forming a first layer of a first connecting material thereon;
FIG. 14 is a schematic cross-sectional view of the structure of FIG. 13 after performing a patterned etch process thereon;
FIG. 15 is a schematic cross-sectional view of the structure of FIG. 14 after forming a second layer of first bonding material thereon;
FIG. 16 is a schematic cross-sectional view of the structure shown in FIG. 12 after forming a contact spacer thereon;
FIG. 17 is a schematic cross-sectional view of the structure of FIG. 16 after performing a patterned etch process thereon;
FIG. 18 is a schematic cross-sectional view of the structure shown in FIG. 17 after forming a second storage node contact structure thereon;
FIG. 19 is a schematic cross-sectional view of the structure of FIG. 17 after forming a second layer of bonding material thereon;
wherein, the liquid crystal display device comprises a liquid crystal display device,
100-a substrate;
110-an active region;
a 111-drain;
112-active isolation structures;
a 120-bit line structure;
121-bit line conductors;
122-bit line isolation layer;
130-isolating lines;
140-contact window;
150-a layer of connection material;
160-storage node contacts;
170-opening;
180-contact isolation layer;
200-substrate;
210-an active region;
211-drain electrode;
212-word line;
213-active isolation structures;
220-bit line structure;
221-bit line conductors;
222-bit line isolation layer;
230-isolating line;
240-contact window;
250-a first storage node contact structure;
251-first tier first storage node contact structure;
252-second level first storage node contact structure;
251 a-a first layer of a first connecting material;
252 a-a second layer of first connecting material;
260-contact isolation layer;
270-opening;
280-a second storage node contact structure;
280 a-a second layer of connection material;
290-storage node contacts.
Detailed Description
Referring to fig. 1 to 6, fig. 1 is a flow chart of a memory manufacturing method; FIG. 2 is a schematic top view of a memory; FIG. 3 is a schematic cross-sectional view of the memory shown in FIG. 2 along the line AA' of the substrate; FIG. 4 is a schematic cross-sectional view of a layer of bonding material formed on the substrate shown in FIG. 3; FIG. 5 is a schematic cross-sectional view of the structure of FIG. 4 after performing a patterned etch process thereon; fig. 6 is a schematic cross-sectional view of the structure depicted in fig. 5 after forming a contact spacer. As shown in fig. 1 to 6, the manufacturing method of the memory includes:
step S10: providing a substrate 100, wherein a plurality of active regions 110 are formed in the substrate 100, a plurality of bit line structures 120 extending along a first direction and a plurality of isolation lines 130 extending along a second direction are formed on the substrate 100, the bit line structures 120 comprise bit line conductors 121 and bit line isolation layers 122 covering the bit line conductors 121, a plurality of contact windows 140 are defined by adjacent bit line structures 120 and adjacent isolation lines 130, and one drain 111 in the active regions 110 is aligned to the contact windows 140, wherein adjacent active regions 110 can be isolated by an active isolation structure 112;
step S11: forming a connection material layer 150 on the substrate 100, wherein the connection material layer 150 covers the contact window 140, the bit line structure 120 and the isolation line 130, and the connection material layer 150 is electrically connected to the drain 111;
step S12: patterning the connection material layer 150 and the bit line structure 120, and etching the bit line isolation layer stopping in the connection material layer 150 and the bit line structure 120 to form a plurality of storage node contacts 160 and an opening 170 adjacent to the storage node contacts 160; a kind of electronic device with high-pressure air-conditioning system
Step S13: a contact spacer 180 is formed on the substrate 100, the contact spacer 180 filling the opening 170.
With continued reference to fig. 6, the opening 170 is formed by etching the connection material layer 150 and the bit line structure 120 in a patterned manner and stopping etching in the connection material layer 150 and in the bit line isolation layer of the bit line structure 120, the contact isolation layer 180 is located in the opening 170, i.e. the contact isolation layer 180 is deeply buried between adjacent storage node contacts 160, and the bottom surface of the contact isolation layer 180 is lower than the top surface of the bit line isolation layer 122, whereby the cross-sectional width (i.e. the width along the second direction here) of the storage node contacts 160 isolated from the adjacent storage node contacts 160 by the bit line isolation layer 122 and the contact isolation layer 180 is relatively small, resulting in a relatively high resistance value of the storage node contacts 160.
With continued reference to fig. 6, the resistance of the storage node contact 160 formed by the above-described process is mainly limited by the cross-sectional width h1 of the portion of the storage node contact 160 between the bit line isolation layer 122 and the contact isolation layer 180.
On this basis, the present invention provides another method for manufacturing a memory, and in particular, please refer to fig. 7, which is a flow chart of a method for manufacturing a memory according to an embodiment of the present invention. As shown in fig. 7, the method for manufacturing the memory includes:
step S20: providing a substrate, wherein a plurality of active areas are formed in the substrate, a plurality of bit line structures extending along a first direction and a plurality of isolation lines extending along a second direction are formed on the substrate, a plurality of contact windows are formed by surrounding adjacent bit line structures and adjacent isolation lines, and one drain electrode in the active areas is aligned to one contact window;
step S21: aligning and filling a first storage node contact structure in the contact window on the substrate, wherein the first storage node contact structure is electrically connected with the drain electrode;
step S22: forming a contact isolation layer on the substrate, wherein the contact isolation layer covers the first storage node contact structure, the bit line structure and the isolation line;
step S23: etching a part of the contact isolation layer which is positioned above the first storage node contact structures to form a plurality of openings, wherein the openings penetrate through the contact isolation layer to expose the first storage node contact structures, and each first storage node contact structure corresponds to one opening; a kind of electronic device with high-pressure air-conditioning system
Step S24: and filling a second storage node contact structure in the opening, wherein the second storage node contact structure is electrically connected with the first storage node contact structure to form a storage node contact.
Correspondingly, the invention further provides a memory, which comprises:
the semiconductor device comprises a substrate, a plurality of active regions, a plurality of isolation lines, a plurality of first drain electrodes and a plurality of first source electrodes, wherein the substrate is internally provided with a plurality of active regions, a plurality of bit line structures extending along a first direction and a plurality of isolation lines extending along a second direction are formed on the substrate, a plurality of contact windows are formed by surrounding adjacent bit line structures and adjacent isolation lines, and one drain electrode of the active regions is aligned with one contact window;
a first storage node contact structure filled in the contact window on the substrate and electrically connected with the drain electrode;
a contact isolation layer on the substrate and partially covering the first storage node contact structure and the bit line structure, wherein the area of the contact isolation layer not covered by the first storage node contact and the bit line structure is used for forming a plurality of openings penetrating the contact isolation layer, and one first storage node contact structure is correspondingly and locally exposed in one opening; a kind of electronic device with high-pressure air-conditioning system
And a second storage node contact structure filled in the opening, the second storage node contact structure being electrically connected with the first storage node contact structure to form a storage node contact.
Next, the memory and the manufacturing method thereof according to the present invention will be described in further detail with reference to the accompanying drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Specifically, please refer to fig. 8-19, wherein fig. 8 is a top view of the memory according to an embodiment of the present invention; FIG. 9 is a schematic top view of an embodiment of the invention without isolation lines formed on the substrate; FIG. 10 is a schematic top view of an isolation line formed on a substrate in accordance with an embodiment of the present invention; FIG. 11 is a schematic cross-sectional view of the substrate along BB' of the substrate shown in FIG. 10; FIG. 12 is a schematic cross-sectional view of the substrate shown in FIG. 11 after forming a first storage node contact structure thereon; FIG. 13 is a schematic cross-sectional view of the substrate shown in FIG. 11 after forming a first layer of a first connecting material thereon; FIG. 14 is a schematic cross-sectional view of the structure of FIG. 13 after performing a patterned etch process thereon; FIG. 15 is a schematic cross-sectional view of the structure of FIG. 14 after forming a second layer of first bonding material thereon; FIG. 16 is a schematic cross-sectional view of the structure shown in FIG. 12 after forming a contact spacer thereon; FIG. 17 is a schematic cross-sectional view of the structure of FIG. 16 after performing a patterned etch process thereon; FIG. 18 is a schematic cross-sectional view of the structure shown in FIG. 17 after forming a second storage node contact structure thereon; fig. 19 is a schematic cross-sectional view of the structure of fig. 17 after forming a second layer of connecting material thereon.
As shown in fig. 9, 10 and 11, first, a substrate 200 is provided, in which a plurality of active regions 210 are formed in the substrate 200, a plurality of bit line structures 220 extending along a first direction and a plurality of isolation lines 230 extending along a second direction are formed on the substrate 200, a plurality of contact windows 240 are defined by adjacent bit line structures 220 and adjacent isolation lines 230, and one drain 211 in the active regions 210 is aligned with the contact windows 240.
In this embodiment, a plurality of word lines 212 extending along the second direction are also formed in the substrate 200, and the isolation lines 230 are aligned with the word lines 212.
The bit line structure 220 includes a bit line conductor 221 and a bit line isolation layer 222 covering the bit line conductor 221, wherein the bit line isolation layer 222 covers the side and top surfaces of the bit line conductor 221.
In this embodiment, the first direction and the second direction are perpendicular. Further, the active region 210 extends along a third direction, and the third direction obliquely intersects the first direction and the second direction. In this embodiment, the active regions 210 are arranged in a plurality of rows, and two adjacent rows of the active regions 210 are staggered. Here, the active regions 210 respectively located in two adjacent rows are different (including completely different and partially identical) with respect to the word lines 212, for example, a first one of the active regions 210 in a first row corresponds to a first one of the word lines 212 and a second one of the active regions 210 in a second row corresponds to the first one of the active regions 210 in the first row only on the corresponding first one of the word lines 212, and a second one of the active regions 210 in the second row corresponds to the first one of the active regions 210 in the first row only on the corresponding second one of the word lines 212. In the embodiment of the present application, the adjacent active regions 210 may be isolated by an active isolation structure 213.
As shown in fig. 12, a first storage node contact structure 250 is aligned and filled in the contact window 240 on the substrate 200, and the first storage node contact structure 250 is electrically connected with the drain electrode 211. That is, the first storage node contact structure 250 covers the contact 240 and exposes the top surface of the bit line structure 220 (i.e., the top surface of the bit line isolation layer 222).
The first storage node contact structure 250 may have a single-layer structure or a multi-layer stacked structure, and the material of each layer in the first storage node contact structure 250 is selected from one of polysilicon and metal.
In this embodiment, the first storage node contact structure 250 is a dual-layer stacked structure, which includes a first layer of first storage node contact structure 251 formed on the substrate 200 and a second layer of first storage node contact structure 252 formed on the first layer of first storage node contact structure 251.
Specifically, the first storage node contact structure 250 may be formed by the following process steps:
forming a first connection material layer on the substrate 200, wherein the first connection material layer covers the contact window 240, the bit line structure 220 and the isolation line 230;
the thickness of the first connection material layer is consumed in one selected from grinding, etching, and a combination thereof to expose the bit line structure 220 and the isolation line 230 to form the first storage node contact structure 250.
The first connecting material layer may have a single-layer structure or a multi-layer laminated structure.
Referring to fig. 12 to 15, in the embodiment of the present application, the first storage node contact structure 250 is specifically formed by the following process:
as shown in fig. 13, a first connection material layer 251a is formed on the substrate 200, and the first connection material layer 251a covers the contact window 240, the bit line structure 220 and the isolation line 230. Here, the material of the first connection material layer 251a is polysilicon, and the first connection material layer 251a may be formed by a chemical vapor deposition process or a physical vapor deposition process.
Next, as shown in fig. 14, the first connection material layer 251a may be patterned and etched, and portions of the bit line structure 220 and the isolation line 230 are removed to form a first storage node contact structure 251, wherein the first storage node contact structure 251 covers the contact window 240 and exposes the bit line structure 220 and the isolation line 230.
Next, as shown in fig. 15, a second layer of first connection material 252a is formed on the substrate 200, the second layer of first connection material 252a covering the first layer of first storage node contact structures 251, the bit line structures 220 and the isolation lines 230. Here, the material of the second first connection material layer 252a is metal, and the second first connection material layer 252a may be formed by a chemical vapor deposition process or a physical vapor deposition process.
As shown in fig. 12, in the embodiment of the present application, the thickness of the second first connection material layer 252a is then reduced by a grinding process until the bit line structure 220 and the isolation line 230 are exposed, so as to obtain a second first storage node contact structure 252, thereby forming a first storage node contact structure 250.
In other embodiments of the present application, a first connection material layer 251a may be formed on the substrate 200 and covers the contact window 240, the bit line structure 220 and the isolation line 230; forming a second first connection material layer 252a on the substrate 200, wherein the second first connection material layer 252a covers the first connection material layer 251a; next, the first and second first connection material layers 251a and 252a may be thinned by only one etching process or one grinding process or a combination of etching and grinding processes to expose the bit line structures 220 and the isolation lines 230, to obtain the first storage node contact structures 250.
In the embodiment of the present application, the first storage node contact structure 250 is formed as a dual-layer stacked structure, and in other embodiments of the present application, the first storage node contact structure 250 may also be a single-layer structure, for example, the first storage node contact structure 250 may be a single-layer polysilicon layer, or the first storage node contact structure 250 may also be a three-layer stacked structure, or the like.
Next, referring to fig. 16, a contact isolation layer 260 is formed on the substrate 200, wherein the contact isolation layer 260 covers the first storage node contact structure 250, the bit line structure 220 (i.e. the contact isolation layer 260 covers the top surface of the bit line isolation layer 222), and the isolation line 230. That is, in the present embodiment, the bottom surface of the contact isolation layer 260 is higher than the top surface of the bit line structure 220 (i.e., here, the bottom surface of the contact isolation layer 260 is higher than the top surface of the bit line isolation layer 222). The material of the contact isolation layer 260 may be an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, etc. The contact isolation layer 260 may be formed by a chemical vapor deposition process.
Referring to fig. 17, in the embodiment of the present application, portions of the contact isolation layer 260 partially located above the first storage node contact structures 250 are etched to form a plurality of openings 270, wherein the openings 270 penetrate through the contact isolation layer 260 to expose the first storage node contact structures 250, and each of the openings 270 corresponds to one of the first storage node contact structures 250. Here, the contact isolation layer 260 also covers a portion of the first storage node contact structure 250. That is, in the embodiment of the present application, a patterned etching process is performed on the contact isolation layer 260.
In the present embodiment, the opening 270 extends into the bit line structure 220 and into the first storage node contact structure 250. The method for forming the opening 270 specifically includes:
the portion of the contact isolation layer 260 above the first storage node contact structure 250 and the portion above the bit line structure 220 are etched to form the opening 270, the opening 270 corresponding to the first storage node contact 250 and extending offset into the bit line structure 220 such that the opening 270 further has a portion overlying the bit line structure 220 to expose both the first storage node contact 250 and the bit line isolation layer 222 in the bit line structure 220. Here, the contact isolation layer 260 exposes a portion of the first storage node contact 250 and a portion of the bit line isolation layer 222 in the bit line structure 220, and at the same time, the contact isolation layer 260 covers the portion of the first storage node contact 250 and the portion of the bit line isolation layer 222 in the bit line structure 220.
Further, after etching the contact isolation layer 260 to expose the first storage node contact structure 250 and the bit line structure 220, the bit line isolation layer 222 in the first storage node contact structure 250 and the bit line structure 220 is then etched to partially remove the first storage node contact structure 250 and the bit line isolation layer 222, and etching is stopped in the first storage node contact structure 250 and in the bit line isolation layer 222.
In the embodiment of the present application, the contact isolation layer 260, the first storage node contact structure 250, and the bit line isolation layer 222 enclose the opening 270. The bottom surface of the opening 270 is higher than the top surface of the bit line conductor 221. That is, in the embodiment of the present application, the opening 270 extends from the surface of the contact isolation layer 260 into the first storage node contact structure 250 and the bit line isolation layer 222, and there is a portion of the thickness of the bit line isolation layer 222 and the first storage node contact structure 250 between the bottom surface of the opening 270 and the top surface of the substrate 200.
The opening 270 may be formed by a one-step etching process or a multi-step etching process, so as to improve etching accuracy. For example, a portion of the contact isolation layer 260 may be removed by a one-step patterning etch process to expose a portion of the first storage node contact structure 250 and a portion of the bit line isolation layer 222; the exposed first storage node contact structure 250 and the exposed bit line isolation layer 222 are then removed by a (further) one-step patterning etch process, thereby forming the opening 270.
Referring to fig. 8 and 18, in the embodiment of the present application, a second storage node contact structure 280 is filled in the opening 270, and the second storage node contact structure 280 and the first storage node contact structure 250 are electrically connected to form a storage node contact 290.
Wherein after the second storage node contact structure 280 is filled in the opening 270, a top surface of the second storage node contact structure 280 may be flush with a top surface of the contact isolation layer 260, and a top surface of the second storage node contact structure 280 may be lower than a top surface of the contact isolation layer 260.
In this embodiment, the second storage node contact structure 280 is partially embedded in the depth direction and partially protrudes upwards to be connected to the first storage node contact structure 250; the second storage node contact structure 280 is non-centrally aligned with the first storage node contact structure 250 in the width direction, and is partially embedded and partially laterally protruded to be connected to the first storage node contact structure 250.
Here, the storage node contact 290 includes the first storage node contact structure 250 and the second storage node contact structure 280 electrically connected to the first storage node contact structure 250. Adjacent two of the storage node contacts 290 are isolated by the contact isolation layer 260 and the bit line isolation layer 222. The storage node contact 290 corresponds to the contact window 240 and extends offset into the bit line structure 220, wherein a top surface of the storage node contact 290 is flush with a top surface of the contact isolation layer 260 or below a top surface of the contact isolation layer 260, and the storage node contact 290 extends to a bottom surface in the bit line structure 220 that is higher than a top surface of the bit line conductor 221.
In the embodiment of the present application, the second storage node contact structure 280 may be specifically formed by the following process steps:
as shown in fig. 19, a second connection material layer 280a is formed on the substrate 200, and the second connection material layer 280a fills the opening 270 and covers the contact isolation layer 260. Here, the material of the second connection material layer 280a is metal.
Next, as shown in fig. 18, the thickness of the second connection material layer 280a is consumed in a grinding manner until the contact isolation layer 260 is exposed, so as to form the second storage node contact structure 280. Wherein the material of the second storage node contact structure 280 is metal.
With continued reference to fig. 18, in the embodiment of the present application, the resistance of the storage node contact 290 formed by the above-described process is mainly limited by the cross-sectional width h2 between the bit line isolation layer 222 and the contact isolation layer 260 on opposite sides of the storage node contact 290. Comparing the cross-sectional width h2 in fig. 18 with the cross-sectional width h1 in fig. 6, it can be seen that the cross-sectional width h2 in the storage node contact 290 formed by an embodiment of the present invention is larger, whereby the storage node contact 290 will have a lower resistance value relative to the storage node contact 160.
In summary, in the method for manufacturing the memory provided by the embodiment of the invention, the contact isolation layer is formed first, and then the memory node contact is formed, so that the contact isolation layer can well isolate the adjacent memory node contact, and the reliability of the formed memory is improved. Further, the storage node contacts correspond to the contact windows and extend into the bit line structure in an offset manner, so that the storage node contacts have a larger section width, the storage node contacts have a smaller resistance value, and the quality of the storage node contacts is improved. Meanwhile, the storage node contacts the corresponding contact window and extends to the bit line structure in an offset manner, so that a capacitor formed subsequently has a larger process window, and the process difficulty is reduced.
Accordingly, an embodiment of the present invention further provides a memory, please continue to refer to fig. 18, the memory includes:
a substrate 200, in which a plurality of active regions 210 are formed in the substrate 200, a plurality of bit line structures 220 extending along a first direction and a plurality of isolation lines 230 extending along a second direction are formed on the substrate 200, a plurality of contact windows 240 are defined by adjacent bit line structures 220 and adjacent isolation lines 230, and one drain electrode 211 in the active regions 210 is aligned to the contact windows 240;
a first storage node contact structure 250 filled in the contact window 240 on the substrate 200 and electrically connected to the drain electrode 211;
a contact isolation layer 260 disposed on the substrate 200 and partially covering the first storage node contact structure 250 and the bit line structure 220, wherein a region of the contact isolation layer 260 not covering the first storage node contact 250 and the bit line structure 220 is used to form a plurality of openings 270 penetrating the contact isolation layer 260, and one of the first storage node contact structures 250 is correspondingly partially exposed in one of the openings 270; a kind of electronic device with high-pressure air-conditioning system
A second storage node contact structure 280 fills the opening 270, the second storage node contact structure 280 being electrically connected to the first storage node contact structure 250 to form a storage node contact 290.
In this embodiment, a plurality of word lines 212 extending along the second direction are also formed in the substrate 200, and the isolation lines 230 are aligned with the word lines 212. The bit line structure 220 includes a bit line conductor 221 and a bit line isolation layer 222 covering the bit line conductor 221, the bit line isolation layer 222 covering the side and top surfaces of the bit line conductor 221.
Further, the opening 270 corresponds to the first storage node contact structure 250 and extends into the bit line structure 220 in an offset manner, such that the opening 270 further has a portion overlying the bit line structure 220 to simultaneously correspond to the first storage node contact structure 250 and the bit line isolation layer 222 in the bit line structure 220 in the opening 270. The bottom of the opening 270 extends into the first storage node contact structure 250 and into the bit line isolation layer 222 of the bit line structure 220.
In this embodiment, the second storage node contact structure 280 is partially embedded in the depth direction and partially protrudes upwards to be connected to the first storage node contact structure 250; the second storage node contact structure 280 is non-centrally aligned with the first storage node contact structure 250 in the width direction, and is partially embedded and partially laterally protruded to be connected to the first storage node contact structure 250.
Here, the storage node contact 290 corresponds to the contact window 240 and extends offset into the bit line structure 220, wherein a top surface of the storage node contact 290 is flush with a top surface of the contact isolation layer 260 or below a top surface of the contact isolation layer 260, and the storage node contact 290 extends to a bottom surface in the bit line structure 220 that is higher than a top surface of the bit line conductor 221.
In summary, in the memory provided by the embodiment of the invention, the contact isolation layer is formed first, and then the memory node contact is formed, so that the contact isolation layer can well isolate the adjacent memory node contact, and the reliability of the formed memory is improved. Further, the storage node contacts correspond to the contact windows and extend into the bit line structure in an offset manner, so that the storage node contacts have a larger section width, the storage node contacts have a smaller resistance value, and the quality of the storage node contacts is improved. Meanwhile, the storage node contacts the corresponding contact window and extends to the bit line structure in an offset manner, so that a capacitor formed subsequently has a larger process window, and the process difficulty is reduced.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (14)
1. A method of manufacturing a memory, the method comprising:
providing a substrate, wherein a plurality of active areas are formed in the substrate, a plurality of bit line structures extending along a first direction and a plurality of isolation lines extending along a second direction are formed on the substrate, a plurality of contact windows are formed by surrounding adjacent bit line structures and adjacent isolation lines, and one drain electrode in the active areas is aligned to one contact window;
aligning and filling a first storage node contact structure in the contact window on the substrate, wherein the first storage node contact structure is electrically connected with the drain electrode;
forming a contact isolation layer on the substrate, wherein the contact isolation layer covers the first storage node contact structure, the bit line structure and the isolation line;
etching a part of the contact isolation layer which is positioned above the first storage node contact structures to form a plurality of openings, wherein the openings penetrate through the contact isolation layer to expose the first storage node contact structures, and each first storage node contact structure corresponds to one opening; a kind of electronic device with high-pressure air-conditioning system
Filling a second storage node contact structure in the opening, wherein the second storage node contact structure is electrically connected with the first storage node contact structure to form a storage node contact;
the bit line structure comprises a bit line conductor and a bit line isolation layer covering the bit line conductor, and the forming method of the opening comprises the following steps:
and etching a part of the contact isolation layer above the first storage node contact structure and a part of the contact isolation layer above the bit line structure to form the opening, wherein the opening corresponds to the first storage node contact and extends into the bit line structure in an offset manner, so that the opening is further provided with a part overlapped with the bit line structure to simultaneously expose the first storage node contact and the bit line isolation layer in the bit line structure.
2. The method of manufacturing a memory according to claim 1, wherein in the step of forming the opening, further comprising:
after etching the contact isolation layer to expose the first storage node contact structure and the bit line structure, then etching the bit line isolation layer in the first storage node contact structure and the bit line structure to partially remove the first storage node contact structure and the bit line isolation layer, and etching stopping in the first storage node contact structure and the bit line isolation layer.
3. The method of manufacturing a memory device according to claim 2, wherein the second storage node contact structure is partially embedded in a depth direction and partially protrudes upward to be connected to the first storage node contact structure; the first storage node contact structure is aligned non-centrally in the width direction, and is partially embedded and partially laterally connected to the first storage node contact structure in a protruding manner.
4. The method of manufacturing a memory of claim 2, wherein the storage node contacts correspond to the contact windows and extend offset into the bit line structure, wherein a top surface of the storage node contacts is flush with or below a top surface of the contact isolation layer, and wherein a bottom surface of the storage node contacts extends into the bit line structure higher than a top surface of the bit line conductor.
5. The method of manufacturing a memory device according to claim 1, wherein a plurality of word lines extending in the second direction are further formed in the substrate, and the isolation lines are aligned with the word lines.
6. The method of manufacturing a memory according to any one of claims 1 to 5, wherein the step of forming the first storage node contact structure includes:
forming a first connecting material layer on the substrate, wherein the first connecting material layer covers the contact window, the bit line structure and the isolation line;
the thickness of the first connection material layer is consumed in one selected from grinding, etching and a combination of the two to expose the bit line structure and the isolation line so as to form the first storage node contact structure.
7. The method of manufacturing a memory device according to any one of claims 1 to 5, wherein the first storage node contact structure is a single-layer structure or a multi-layer stacked structure, and a material of each layer in the first storage node contact structure is selected from one of polysilicon and metal.
8. The method of manufacturing a memory according to any one of claims 1 to 5, wherein the step of forming the second storage node contact structure includes:
forming a second connecting material layer on the substrate, wherein the second connecting material layer fills the opening and covers the contact isolation layer;
and consuming the thickness of the second connecting material layer in a grinding manner until the contact isolation layer is exposed so as to form the second storage node contact structure.
9. The method of manufacturing a memory device according to any one of claims 1 to 5, wherein a material of the second storage node contact structure is a metal.
10. A memory, the memory comprising:
the semiconductor device comprises a substrate, a plurality of active regions, a plurality of isolation lines, a plurality of first drain electrodes and a plurality of first source electrodes, wherein the substrate is internally provided with a plurality of active regions, a plurality of bit line structures extending along a first direction and a plurality of isolation lines extending along a second direction are formed on the substrate, a plurality of contact windows are formed by surrounding adjacent bit line structures and adjacent isolation lines, and one drain electrode of the active regions is aligned with one contact window;
the first storage node contact structure is filled in the contact window on the substrate and is electrically connected with the drain electrode, the first storage node contact structure is of a single-layer structure or a multi-layer laminated structure, and the material of each layer in the first storage node contact structure is selected from one of polysilicon and metal;
a contact isolation layer on the substrate and partially covering the first storage node contact structure and the bit line structure, wherein the area of the contact isolation layer which is not covered by the first storage node contact and the bit line structure is used for forming a plurality of openings penetrating through the contact isolation layer, one first storage node contact structure is correspondingly and partially exposed in one opening, the opening is correspondingly contacted with the first storage node and is offset to extend into the bit line structure, and the opening is further provided with a part overlapped with the bit line structure so as to simultaneously correspond to the first storage node contact structure and the bit line isolation layer in the bit line structure in the opening; a kind of electronic device with high-pressure air-conditioning system
And a second storage node contact structure filled in the opening, the second storage node contact structure being electrically connected with the first storage node contact structure to form a storage node contact.
11. The memory of claim 10, wherein a bottom of the opening extends into the first storage node contact structure and into the bit line isolation layer of the bit line structure.
12. The memory of claim 11 wherein the second storage node contact structure is partially embedded in the depth direction and partially protruding upward to connect to the first storage node contact structure; the first storage node contact structure is aligned non-centrally in the width direction, and is partially embedded and partially laterally connected to the first storage node contact structure in a protruding manner.
13. The memory of claim 11, wherein the storage node contact corresponds to the contact window and extends offset into the bit line structure, wherein a top surface of the storage node contact is flush with or below a top surface of the contact isolation layer, and wherein a bottom surface of the storage node contact extends into the bit line structure higher than a top surface of the bit line conductor.
14. The memory of any of claims 10-13, wherein a plurality of word lines extending in the second direction are also formed in the substrate, the isolation lines being aligned with the word lines.
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| CN114050156A (en) * | 2020-01-21 | 2022-02-15 | 福建省晋华集成电路有限公司 | Memory device |
| CN111463208B (en) * | 2020-04-29 | 2021-10-26 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN111710679B (en) * | 2020-06-24 | 2022-04-22 | 福建省晋华集成电路有限公司 | Memory and forming method thereof |
| CN114068544A (en) * | 2020-08-04 | 2022-02-18 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| US11856757B2 (en) | 2020-08-04 | 2023-12-26 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor structure with capacitor wires |
| CN114256154A (en) * | 2020-09-24 | 2022-03-29 | 长鑫存储技术有限公司 | Memory manufacturing method and memory |
| CN116507113A (en) * | 2022-01-18 | 2023-07-28 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
| CN117500269B (en) * | 2023-12-28 | 2024-04-19 | 长鑫集电(北京)存储技术有限公司 | Semiconductor structure, manufacturing method thereof and storage device |
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