WO2023029563A1

WO2023029563A1 - Memory device and manufacturing method therefor

Info

Publication number: WO2023029563A1
Application number: PCT/CN2022/091926
Authority: WO
Inventors: 王晓光; 曾定桂; 李辉辉; 曹堪宇
Original assignee: 长鑫存储技术有限公司; 北京超弦存储器研究院
Priority date: 2021-08-30
Filing date: 2022-05-10
Publication date: 2023-03-09
Also published as: CN115942754A

Abstract

The present disclosure relates to a memory device and a manufacturing method therefor. The memory device comprises: a substrate, a common source line, a plurality of gate word lines, a plurality of columnar structures, and a gate dielectric layer. The common source line is arranged on the substrate. The plurality of gate word lines are arranged above the common source line in parallel at intervals, and the gate word lines extend in a first direction. The plurality of columnar structures are arranged on the common source line in an array shape, and pass through the gate word lines. Columnar structures of adjacent rows are staggered in the row direction, and columnar structures of adjacent columns are staggered in the column direction. The gate dielectric layer is positioned between the columnar structures and the gate word lines. The present memory device and the manufacturing method therefor can further improve the memory integration density of the memory device, and have good and stable memory performance.

Description

Memory device and method of manufacturing the same

Cross References to Related Applications

This disclosure claims the priority of the Chinese patent with the application number 202111006767.1 and the title of the invention "storage device and its preparation method" submitted to the China Patent Office on August 30, 2021. The entire content of the patent application is incorporated herein by reference. In public.

technical field

The present disclosure relates to the technical field of manufacturing semiconductor integrated circuits, in particular to a storage device and a manufacturing method thereof.

Background technique

Magnetic random access memory (Magnetoresistive Random Access Memory, referred to as MRAM), as a non-volatile (Non-Volatile) memory, not only can have high-speed read and write of static random access memory (Static Random-Access Memory, referred to as SRAM) Capability, also can have the high-density integration capability of dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM).

However, although the high-density integration capability of MRAM is conducive to reducing its production cost, it can also be used as one of the core competitiveness of MRAM compared with other traditional non-flash memories. However, how to further improve the high-density integration capability of MRAM has become an urgent problem to be solved in related technologies.

Contents of the invention

According to various embodiments of the present disclosure, a memory device and a method of fabricating the same are provided.

According to some embodiments, an aspect of the present disclosure provides a memory device. The storage device includes: a substrate, a common source line, a plurality of gate word lines, a plurality of columnar structures and a gate dielectric layer. The common source line is disposed on the substrate. A plurality of gate word lines are arranged in parallel and spaced above the common source line, and the gate word lines extend along a first direction. A plurality of columnar structures are arranged in an array on the common source line and run through the gate word line. The columnar structures of adjacent rows are misaligned along the row direction, and the columnar structures of adjacent columns are misaligned along the column direction. The gate dielectric layer is located between the column structure and the gate word line.

According to some embodiments, the memory device further includes a plurality of memory modules. The storage module is correspondingly arranged above the columnar structure and connected with the columnar structure.

According to some embodiments, the memory device also includes a plurality of bit lines. A plurality of bit lines are arranged in parallel and spaced above the memory module. The bit lines extend along the second direction and are correspondingly connected with the memory modules. The second direction intersects the first direction.

According to some embodiments, the memory device further includes: a plurality of storage node contact structures. The storage node contact structure is located on the storage module and at least partially covers the storage module. The bit line is correspondingly connected to the memory module through the storage node contact structure.

According to some embodiments, a memory module includes a magnetic tunnel junction.

According to some embodiments, the common source line includes doped silicon. The columnar structure includes single crystal silicon.

According to some embodiments, the distance between two adjacent columnar structures in any row is the first distance. The misalignment distance of the columnar structures in adjacent columns along the column direction is less than the first distance.

According to some embodiments, the misalignment distance of the columnar structures in adjacent columns along the column direction is less than or equal to the second distance; the second distance is greater than 0.5 times the first distance and smaller than the first distance.

According to some embodiments, the misalignment distance of the columnar structures of adjacent rows along the row direction is less than or equal to 0.5 times the first distance.

According to some embodiments, another aspect of the present disclosure provides a method for manufacturing a storage device, which is used to prepare the storage device as described in some embodiments above. The preparation method of the storage device includes the following steps.

A substrate is provided, and a common source line is formed on the substrate.

A plurality of columnar structures arranged in an array are formed on the common source line, wherein the columnar structures of adjacent rows are misaligned along the row direction, and the columnar structures of adjacent columns are misaligned along the column direction.

A gate dielectric layer is formed on the sidewall of the column structure.

A first dielectric layer penetrated by the column structure and the gate dielectric layer is formed on the common source line.

A plurality of gate word lines arranged in parallel at intervals are formed on the first dielectric layer, wherein the columnar structures arranged along the first direction and the gate dielectric layer on the outside thereof penetrate the same gate word line.

A second dielectric layer is formed on the first dielectric layer covering the gate word line and penetrated by the columnar structure and the gate dielectric layer.

According to some embodiments, the manufacturing method of the storage device further includes: forming a storage module on the columnar structure, and the storage module is correspondingly connected to the columnar structure.

According to some embodiments, the manufacturing method of the memory device further includes: forming a plurality of bit lines arranged in parallel and at intervals above the memory module. The bit lines extend along the second direction and are correspondingly connected with the memory modules. The second direction intersects the first direction.

According to some embodiments, before forming a plurality of bit lines arranged in parallel and at intervals above the memory module, the manufacturing method of the memory device further includes: forming a storage node contact structure on the memory module, the storage node contact structure at least partially covering the memory module.

Correspondingly, forming a plurality of bit lines arranged in parallel and spaced above the memory module includes: forming a plurality of bit lines arranged in parallel and spaced above the storage node contact structure, so that the bit lines correspond to the memory module through the storage node contact structure connect.

According to some embodiments, a memory module includes magnetic tunnel junctions arranged in columns.

According to some embodiments, the surface of the column structure facing away from the substrate is higher than the surface of the gate dielectric layer facing away from the substrate. Forming the storage module above the columnar structure includes the following steps.

A third dielectric layer penetrated by the columnar structure is formed on the second dielectric layer and the gate dielectric layer, and the surface of the third dielectric layer away from the substrate is flush with the surface of the columnar structure away from the substrate.

A storage module material layer is formed on the third dielectric layer and the columnar structure, and the storage module material layer is patterned to obtain a storage module in one-to-one contact with the columnar structure.

According to some embodiments, forming a common source line on the substrate, forming a plurality of columnar structures arranged in an array on the common source line includes: sequentially growing a silicon doped layer and a single crystal silicon layer on the substrate, and the silicon The doped layer constitutes a common source line; the monocrystalline silicon layer is patterned to obtain multiple columnar structures.

According to some embodiments, the surface of the second dielectric layer facing away from the substrate is flush with the surface of the gate dielectric layer facing away from the substrate.

Embodiments of the present disclosure may/at least have the following advantages:

In the storage device and the manufacturing method thereof provided by the embodiments of the present disclosure, the columnar structures of adjacent rows are dislocated along the row direction, and the columnar structures of adjacent columns are dislocated along the column direction, so that the columnar structures of adjacent columns are dislocated along the column direction The distance is less than the first distance. In this way, the storage modules are correspondingly arranged above the columnar structure, and the size of the planar area required by each storage module can be reasonably reduced under the premise of meeting the process capability, so as to ensure that the storage device has a higher storage integration density.

Moreover, in the embodiments of the present disclosure, the bit lines are arranged above the memory modules, so that when the memory modules have a relatively high distribution density, the bit lines can be designed to have a larger line width, so as to effectively reduce the connection between the bit lines and the memory modules. The contact resistance between the modules avoids the high resistance of the bit line caused by the embedded setting, so as to ensure that the storage device has good and stable storage performance while having high-density integration capabilities.

In addition, in the embodiment of the present disclosure, doped silicon is used for the common source line, and single crystal silicon is used for the columnar structure. The fabrication process of the structure.

To sum up, the storage device and the manufacturing method thereof provided by the embodiments of the present disclosure can further increase the storage integration density of the storage device, and effectively reduce the contact resistance between the storage module and the bit line, so as to ensure that the storage device has high-density integration. It also has good and stable storage performance.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For Those of ordinary skill in the art can also obtain the drawings of other embodiments according to these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a storage device provided in an embodiment;

FIG. 2 is a schematic cross-sectional view of a storage unit provided in an embodiment;

Figure 3 is a schematic diagram of the distribution of a columnar structure provided in an embodiment;

Fig. 4 is a schematic distribution diagram of another columnar structure provided in an embodiment;

FIG. 5 is a schematic diagram of the distribution of a memory cell, a storage node contact structure, and a bit line provided in an embodiment;

FIG. 6 is a schematic flowchart of a method for manufacturing a storage device provided in an embodiment;

FIG. 7 is a schematic structural diagram of the substrate in step S11 provided in an embodiment;

Figure 8 and Figure 9 are schematic structural views of the structure obtained after forming the columnar structure provided in an embodiment;

FIG. 10 is a schematic structural view of the structure obtained in step S13 provided in an embodiment;

FIG. 11 is a schematic structural diagram of the structure obtained in step S14 provided in an embodiment;

FIG. 12 and FIG. 13 are schematic structural diagrams of the structure obtained in step S15 provided in an embodiment;

FIG. 14 is a schematic structural diagram of the structure obtained in step S14 provided in an embodiment;

Fig. 15, Fig. 16 and Fig. 17 are schematic structural diagrams of the structure obtained in step S15 provided in an embodiment;

FIG. 18 and FIG. 19 are schematic structural diagrams of the structure obtained in step S16 provided in an embodiment.

Detailed ways

In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the related drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the description of the present disclosure are for the purpose of describing specific embodiments only, and are not intended to limit the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer. or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not indicative of the actual shape of a region of a device and are not intended to limit the scope of the disclosure.

In the field of semiconductor integrated circuit manufacturing technology, the integration density of various electronic devices can be continuously increased by, for example, reducing the minimum component size and/or arranging electronic devices close to each other, so as to integrate various electronic devices into a specific area. Various electronic devices include: transistors, diodes, resistors or capacitors, etc.

At present, the high-density integration capability of MRAM can increase the storage range of MRAM from Mb to Gb. However, how to further increase the storage range of MRAM from 1Gb to 8Gb or higher still needs to be solved urgently.

Based on this, referring to FIG. 1 and FIG. 2 , some embodiments of the present disclosure provide a storage device 100 . The storage device 100 includes: a substrate 1 and a plurality of storage units 2 arranged on the substrate in an array. The storage unit 2 includes: a Gate All Around transistor (GAA transistor for short) 21 and a storage module 22 .

In some examples, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Optionally, the substrate 1 is a sapphire substrate, a silicon substrate or a silicon carbide substrate.

In some examples, the wraparound gate transistor 21 includes: a columnar structure 211 , a gate dielectric layer 212 , a source 213 and a drain 214 . Wherein, the gate dielectric layer 212 covers part of the columnar structure 211 . The source 213 and the drain 214 may be formed by a partial area of the columnar structure 211 , so that the part of the columnar structure 211 between the source 213 and the drain 214 is a conductive channel. For example, the source 213 is located at the bottom of the columnar structure 211 , and the drain 214 is located at the top of the columnar structure 211 .

The embodiment of the present disclosure adopts the above-mentioned surrounding gate transistor, that is, the vertical surrounding gate transistor, which can have more integration freedom in the vertical direction, thereby effectively reducing the area of the plane occupied by the transistor and making it easier to The vertical stacking of multi-layer devices is realized, and the integration density of transistors is further increased through a new wiring method, so as to effectively increase the storage integration density of the storage device 100 .

In some examples, the gate dielectric layer 212 may be formed using a material with a high-k dielectric constant. For example, the material of the gate dielectric layer 212 includes: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide substance (SrTiO3).

In some examples, the memory module 22 is correspondingly disposed above the columnar structure 211 , for example, contacts the top of the columnar structure 211 (ie, the drain).

Optionally, the storage module 22 is a magnetic random access storage module. For example, the storage module 22 is a magnetic tunnel junction (Magnetic Tunnel Junction, MTJ for short) arranged in a columnar shape. Optionally, the MTJ includes a free layer (free layer), a fixed layer (fixed layer) and an oxide layer (Tunneling oxide) stacked in a direction away from the substrate. But not limited thereto, other types of storage modules are also applicable.

Please continue to refer to FIG. 1 and FIG. 2 , the storage device 100 further includes: a common source line 3 . The common source line 3 is disposed on the substrate 1 , for example, the entire layer of the common source line 3 covers the substrate 1 . A plurality of columnar structures 211 are arranged in an array on the common source line 3 , and the bottoms of the columnar structures 211 (ie, the source 213 ) are in contact with the common source line 3 .

In one example, the common source line 3 is made of a silicon doped layer epitaxially grown on the substrate 1 , that is, the common source line 3 is doped silicon. The columnar structure 211 can be formed by patterning a single crystal silicon layer epitaxially grown on the common source line 3 , that is, the columnar structure 211 is a single crystal silicon. In this way, the manufacturing process of the storage device 100 can be greatly simplified.

Please continue to refer to FIG. 1 and FIG. 2 , the storage device 100 further includes: a plurality of gate word lines 4 arranged in parallel and spaced above the common source line 3 . The gate word lines 4 extend along the first direction. Moreover, the columnar structure 211 arranged along the first direction and the gate dielectric layer 212 outside it penetrate the same gate word line 4 . The gate dielectric layer 212 is located between the column structure 211 and the gate word line 4 . Here, the first direction may be the row direction, or may be a direction that forms an angle with the row direction.

It can be understood that the gate word line 4 is located above the common source line 3 , and the gate word line 4 is insulated from the common source line 3 . For example, please continue to refer to FIG. 1 and FIG. 2 , a first dielectric layer 30 is provided between the gate word line 4 and the common source line 3 . Optionally, the first dielectric layer 30 is an oxide layer, such as a silicon oxide layer.

In addition, in some examples, referring to FIG. 1 and FIG. 2 , the storage device 100 further includes: a second dielectric layer 40 covering the gate word line 4 . The second dielectric layer 40 is used to insulate the adjacent gate word lines 4 and to planarize the surface of the structure obtained after the gate word lines 4 are formed, so as to facilitate subsequent fabrication processes. Optionally, the material of the second dielectric layer 40 is the same as that of the first dielectric layer 30 , and the second dielectric layer 40 is an oxide layer, such as a silicon oxide layer. Alternatively, the second dielectric layer 40 is an organic insulating layer.

What needs to be supplemented is that, please refer to FIG. 1 and FIG. 2 to understand that in some embodiments, with the upper surface of the substrate 1 as a reference plane, the surface of the columnar structure 211 facing away from the substrate 1 is higher than the surface of the gate dielectric layer 212 facing away from the substrate. Bottom 1 surface. The surface of the gate dielectric layer 212 facing away from the substrate 1 is flush with the surface of the second dielectric layer 40 facing away from the substrate 1, or the surface of the gate dielectric layer 212 facing away from the substrate 1 is higher than the backing of the second dielectric layer 40 Bottom 1 surface.

Based on this, the storage device 100 further includes: a third dielectric layer 50 covering the surface of the second dielectric layer 40 and the gate dielectric layer 212 facing away from the substrate 1 . The surface of the third dielectric layer 50 away from the substrate 1 is flush with the surface of the columnar structure 211 away from the substrate, which is beneficial to simplify the process of forming the storage module 22 on the columnar structure 211, and ensures that the storage module 22 can be aligned with the columnar structure 211. good contact. Optionally, the third dielectric layer 50 is an oxide layer, such as a silicon oxide layer. Alternatively, the third dielectric layer 50 is an organic insulating layer.

In some of the above embodiments, the memory modules 22 are arranged on the columnar structure 211 in a one-to-one correspondence, so that the memory modules 22 and the surrounding gate transistors 21 have the same scale, thereby ensuring that the memory device 100 has higher density integration capability. That is to say, the location of the columnar structure 211 will determine the location of the storage module 22 , and the distribution density of the columnar structure 211 will determine the distribution density of the storage module 22 .

Referring to FIG. 3 , in some embodiments, the columnar structures 211 in adjacent rows are misaligned along the row direction, and the distance D ₁ between two adjacent columnar structures 211 in any row is a first distance. The columnar structures 211 in adjacent columns are misaligned along the column direction, and the distance D ₂ of the misalignment is smaller than the first distance. That is, D ₂ is smaller than D ₁ .

Here, the first distance may be twice the minimum process dimension F. The minimum process size F refers to the minimum size that the process can process, also known as the critical size, which can be used as a standard to define the manufacturing process level.

In the embodiment of the present disclosure, the dislocation distance D ₂ of the columnar structures 211 in adjacent columns along the column direction refers to the distance component along the column direction between the columnar structures 211 of the same serial number in adjacent columns. For example, as shown in (a) of FIG. 3 , the serial numbers of columns are arranged from left to right (for example, L1 to L8 ), and the serial numbers of columnar structures 211 in the same column are arranged from bottom to top. In this way, the dislocation distance _D2 of the columnar structures 211 in adjacent columns along the column direction can be: the distance component along the column direction between the first columnar structure 211 in the first column L1 and the first columnar structure 211 in the second column L2 .

Similarly, the displacement distance _D3 of columnar structures 211 in adjacent rows along the row direction refers to the distance component along the row direction between columnar structures 211 of the same serial number in adjacent rows. For example, as shown in (b) of FIG. 3 , the row numbers are arranged from bottom to top (for example, R1 to R4 ), and the numbers of the columnar structures 211 in the same row are arranged from left to right. In this way, the dislocation distance _D3 of the columnar structures 211 in adjacent rows along the row direction can be: the distance component along the row direction between the second columnar structure 211 in the first row R1 and the second columnar structure 211 in the second row R2 .

Based on this, please understand in conjunction with FIG. 3 and FIG. 4 that when the columnar structures 211 in adjacent rows are misaligned along the row direction and the columnar structures 211 in adjacent columns are misaligned in the column direction, the The minimum distance D ₄ between the two columnar structures 211 may be 2F according to the manufacturing process level. In this way, the dislocation distance D ₂ of the columnar structures 211 in adjacent columns along the column direction can be determined according to the columnar structure 211 of adjacent rows dislocation distance D ₃ along the row direction. Correspondingly, the distance D ₅ between two adjacent columnar structures 211 in any column is twice D ₂ .

That is to say, in the embodiment of the present disclosure, the columnar structures 211 of adjacent rows are misaligned along the row direction, the columnar structures 211 of adjacent columns are misaligned along the column direction, and the columnar structures 211 of adjacent columns are misaligned along the column direction by a distance less than The first distance can reasonably reduce the size of the planar area that each storage unit 2 needs to occupy under the premise of meeting the processing capability of the process, so as to ensure a higher distribution density of the plurality of storage units 2 .

For example, referring to FIG. 3 , the columnar structures 211 in adjacent columns are misaligned by a distance D ₂ less than or equal to the second distance along the column direction. The second distance is greater than 0.5 times the first distance and smaller than the first distance. For example, F< _D2 <2F.

Optionally, please refer to FIG. 4 , the columnar structures 211 in adjacent columns are misaligned along the column direction by a distance _D2 equal to

But it doesn't stop there.

In this way, the size of the planar area that each storage unit 2 can occupy is

Approximately equal to 3.46F ² . Compared with the limit planar area size 4F ² that can be achieved in the related art, the embodiments of the present disclosure effectively increase the integration density of the memory cells 2 in the memory device 100 .

For example, please refer to FIG. 3 , the columnar structures 211 in adjacent rows are misaligned along the row direction by a distance D ₃ that is less than or equal to 0.5 times the first distance. For example, D ₃ ≦F.

Optionally, please refer to FIG. 4 , the columnar structures 211 in adjacent rows are misaligned along the row direction by D ₃ =F; correspondingly, the columnar structures 211 in adjacent columns are misaligned along the column direction.

In this way, in any row, the distance _D1 between two adjacent columnar structures 211 can be 2F, and the distance _D4 between two columnar structures 211 of the same serial number corresponding to the dislocation in an adjacent row is, for example, 2F, According to the size of the dislocation distance D ₃ of the columnar structures 211 in adjacent rows along the row direction, the dislocation distance D ₂ of the columnar structures 211 in adjacent columns along the column direction can be correspondingly determined. Therefore, it is convenient to design the distance between adjacent columnar structures 211 along the row direction to achieve the purpose of determining the distance between adjacent columnar structures 211 along the column direction.

Referring to FIG. 1 and FIG. 5 , in some embodiments, the storage device 100 further includes a plurality of storage node contact structures 5 (Storage Node Contact, SNC for short). The storage node contact structure 5 is located on the storage module 22 and at least partially covers the storage module 22 .

Exemplarily, the storage node contact structure 5 is formed on the upper surface of the memory module 22 , that is, the surface of the memory module 22 facing away from the substrate 1 , and is in contact with the memory module 22 . The structure of the storage node contact structure 5 can be selected and set according to actual requirements. Optionally, the storage node contact structure 5 is a metal pad, such as a tungsten pad. Therefore, it can be ensured that the storage node contact structure 5 has a lower resistance value and higher stability.

Exemplarily, the shape of the orthographic projection of the storage node contact structure 5 on the substrate 1 includes a rectangle. In this way, when the storage module 22 is a columnar MTJ, the storage node contact structure 5 adopts a rectangular structure, and the storage node contact structure 5 at least partially covers the MTJ, so that it is easy for the storage node contact structures 5 in adjacent columns to exist in the same column. A straight line or part of an area lying alongside the same straight line.

Please continue to refer to FIG. 1 and FIG. 5 , in some embodiments, the storage device 100 further includes: a plurality of bit lines 6 arranged in parallel at intervals and extending along the second direction. The bit line 6 is located on the corresponding storage node contact structure 5 and correspondingly connected to the storage unit 2 through the storage node contact structure 5 . The second direction intersects the first direction, eg, is perpendicular.

Here, the second direction is, for example, a row direction, and may also be a direction that forms an angle with the row direction.

Optionally, the bit lines 6 extend along the column direction, and one bit line 6 is correspondingly connected to the storage node contact structures 5 on the memory modules 22 of two adjacent columns. The bit line 6 may be a metal line, and may be formed of a metal material with good conductivity. Embodiments of the present disclosure do not limit this.

In the embodiment of the present disclosure, the bit lines 6 are located above the memory modules 22 , and one bit line 6 is correspondingly connected to two adjacent columns of the memory modules 22 . In this way, when the memory module 22 has a relatively high distribution density, the bit line 6 can be designed to have a larger line width size, so as to effectively reduce the contact resistance between the bit line 6 and the memory module 22, and avoid the occurrence of a fault in the bit line 6. The high resistance caused by the embedded arrangement can ensure that the storage device 100 has high-density integration capability and also has good and stable storage performance.

Please refer to FIG. 6 , some embodiments of the present disclosure also provide a method for manufacturing a storage device, which is used to prepare the storage device in some embodiments above. The preparation method of the storage device includes steps as follows.

S11, providing a substrate, and forming a common source line on the substrate.

S12 , forming a plurality of columnar structures arranged in an array on the common source line, wherein the columnar structures in adjacent rows are displaced along the row direction, and the columnar structures in adjacent columns are displaced along the column direction.

S13, forming a gate dielectric layer on the sidewall of the columnar structure.

S14, forming a first dielectric layer penetrated by the columnar structure and the gate dielectric layer on the common source line.

S15 , forming a plurality of gate word lines arranged in parallel and at intervals on the first dielectric layer, wherein the columnar structures arranged along the first direction and the gate dielectric layer outside thereof penetrate the same gate word line.

S16 , forming a second dielectric layer covering the gate word line on the first dielectric layer and being penetrated by the columnar structure and the gate dielectric layer.

S17, forming a storage module above the columnar structure.

S18, forming a plurality of parallel and spaced bit lines above the memory module. The bit lines extend along the second direction and are correspondingly connected with the memory modules. The second direction intersects the first direction.

In step S11 , referring to FIG. 7 , a substrate 1 is provided.

Exemplarily, the substrate 1 includes but not limited to a silicon substrate or a silicon-based substrate.

For example, referring to FIG. 8 , forming the common source line 3 on the substrate 1 includes: epitaxially growing a silicon doped layer on the substrate 1 , so as to form the common source line 3 with the silicon doped layer.

In step S12 , referring to FIG. 8 and FIG. 9 , a plurality of columnar structures 211 arranged in an array are formed on the common source line 3 , and the steps are as follows.

For example, referring to FIG. 8 , a single crystal silicon layer 110 is epitaxially grown on the common source line 3 (ie, the silicon doped layer).

Referring to FIG. 9 , the monocrystalline silicon layer 110 is patterned to obtain a plurality of columnar structures 211 , and the columnar structures in adjacent rows are displaced along the row direction, and the columnar structures in adjacent columns are displaced along the column direction.

Here, the patterning of the single crystal silicon layer 110 can be realized by a photolithography process.

Based on the purpose of forming the columnar structure 211 , the columnar structure 211 is used to form a surrounding gate transistor. Moreover, in the embodiment of the present disclosure, the storage modules 22 are located on the columnar structures 211 in one-to-one correspondence, therefore, the dislocation distance between the columnar structures 211 will determine the dislocation distance between the storage modules 22 . The schematic distribution of the columnar structures 211 can be understood in conjunction with the schematic distribution of the columnar structures 211 in some of the foregoing embodiments (such as shown in FIG. 3 and FIG. 4 ), and will not be described in detail in the embodiments of the present disclosure.

Optionally, the distance between two adjacent columnar structures 211 in any row is the first distance, and the columnar structures 211 in adjacent columns are misaligned along the column direction by a distance less than the first distance.

Optionally, the misalignment distance of the columnar structures 211 in adjacent columns along the column direction is less than or equal to the second distance. The second distance is greater than 0.5 times the first distance and smaller than the first distance. For example, the columnar structures 211 of adjacent columns are misaligned along the column direction by a distance equal to

Optionally, the value range of the misalignment distance of the columnar structures 211 in adjacent rows along the row direction includes: a closed interval of 0.5 times the first distance to 0.7 times the first distance. For example, the dislocation distance of columnar structures 211 in adjacent rows along the row direction is D ₃ =F; correspondingly, the dislocation distance of columnar structures 211 in adjacent columns along the column direction

In the embodiment of the present disclosure, columnar structures 211 in adjacent rows are displaced along the row direction, columnar structures 211 in adjacent columns are displaced along the column direction, and the columnar structures 211 in adjacent columns are displaced along the column direction by a distance less than the first distance, which can be On the premise of conforming to the processing capability of the process, the size of the planar area required to be occupied by each memory unit 2 is reasonably reduced, so as to ensure that the memory device has a higher memory integration density.

In step S13 , referring to FIG. 10 , a gate dielectric layer 212 is formed on the sidewall of the columnar structure 211 .

Optionally, the gate dielectric layer 212 is formed using a material with a high-k dielectric constant. For example, the material of the gate dielectric layer 212 includes: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide substance (SrTiO3).

In addition, optionally, taking the upper surface of the substrate 1 as a reference plane, the surface of the columnar structure 211 facing away from the substrate 1 is higher than the surface of the gate dielectric layer 212 facing away from the substrate 1 .

In step S14 , referring to FIG. 11 , the first dielectric layer 30 penetrated by the columnar structure 211 and the gate dielectric layer 212 is formed on the common source line 3 .

Optionally, the first dielectric layer 30 is formed of an oxide material, for example, a silicon oxide material.

Optionally, the first dielectric layer 30 is formed by a deposition process. The deposition process includes but is not limited to physical vapor deposition (Physical Vapor Deposition, referred to as PVD), chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD).

In step S15 , referring to FIG. 12 and FIG. 13 , a plurality of gate word lines 4 arranged in parallel and spaced apart are formed on the first dielectric layer 30 , including the following steps.

For example, referring to FIG. 12 , a metal material layer 41 is formed on the first dielectric layer 30 .

Optionally, the metal material layer 41 is formed by depositing a metal material with good conductivity, such as molybdenum (Mo), titanium (Ti), aluminum (Al) or tungsten (W).

Referring to FIG. 13 , the metal material layer 41 is patterned to form a plurality of gate word lines 4 arranged in parallel and at intervals.

Optionally, the patterning of the metal material layer 41 is realized by using a self-aligned double patterning (Self-Aligned Double Patterning, referred to as SADP) process or a self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, referred to as SAQP) process .

Here, the gate word lines 4 extend along a first direction, and the first direction may be the row direction in the foregoing embodiments, or may be a direction that forms an included angle with the row direction. The columnar structures 211 arranged along the first direction and the gate dielectric layer 212 on the outside thereof run through the same gate word line 4 .

Please understand with reference to FIG. 2 and FIG. 13 , in this step, the gate dielectric layer 212 is located between the columnar structure 211 and the gate word line 4 , and the gate dielectric layer 212 covers part of the columnar structure 211 . The source 213 is located at the bottom of the columnar structure 211 and is in contact with the common source line 3 . The drain 214 is located on the top of the pillar structure 211 for contacting the memory module 22 . The drain 214 is the top of the column structure 211 higher than the upper surface of the gate dielectric layer 212 .

Here, the source 213 and the drain 214 may be formed by a partial region of the columnar structure 211 , so that the portion of the columnar structure 211 between the source 213 and the drain 214 is a conductive channel. In this way, the gate dielectric layer 212 at least covers the conductive channel. The gate word line 4 is located on the periphery of the gate dielectric layer 212 .

From the above, the columnar structure 211, the gate dielectric layer 212, the source 213, the drain 214 and the part of the gate word line 4 can jointly form the surrounding gate transistor 21, and the part of the gate word line 4 is the surrounding gate transistor. The gate of transistor 21.

In step S16 , referring to FIG. 14 , a second dielectric layer 40 is formed on the first dielectric layer 30 covering the gate word line 4 and penetrated by the columnar structure 211 and the gate dielectric layer 212 .

Here, the second dielectric layer 40 is used to insulate adjacent gate word lines 4, and to planarize the surface of the structure obtained after forming the gate word lines 4, so as to facilitate the subsequent preparation process. The second dielectric layer 40 can be formed using oxide material or organic insulating material, for example, silicon oxide material.

In addition, optionally, the upper surface of the gate dielectric layer 212 (ie its surface facing away from the substrate 1 ) is higher than the upper surface of the second dielectric layer 40 , or is flush with the upper surface of the second dielectric layer 40 .

Based on this, in step S17 , referring to FIG. 15 , FIG. 16 and FIG. 17 , the storage module 22 is formed on the columnar structure 211 , including the following steps.

For example, referring to FIG. 15 , a third dielectric layer 50 penetrated by a columnar structure 211 is formed on the second dielectric layer 40 and the gate dielectric layer 212 . Moreover, the surface of the third dielectric layer 50 facing away from the substrate 1 is flush with the surface of the columnar structure 211 facing away from the substrate 1 . The surface of the columnar structure 211 facing away from the substrate 1 is exposed.

Here, the surface of the third dielectric layer 50 facing away from the substrate 1 is flush with the surface of the columnar structure 211 facing away from the substrate 1, which can be achieved by chemical mechanical polishing, so as to facilitate subsequent formation of storage node contacts on the columnar structure 211 structure 5 and ensure good electrical contact between the columnar structure 211 and the storage node contact structure 5 .

Referring to FIG. 16 , a memory module material layer 220 is formed on the third dielectric layer 50 and the columnar structure 211 .

Exemplarily, the memory module material layer 220 is a magnetic random access memory module material layer. For example, the memory module material layer 220 includes: a free material film, a fixed material film and an oxide material film formed by lamination. But it doesn't stop there.

Referring to FIG. 17 , the memory module material layer 220 is patterned to obtain a memory module 22 in one-to-one contact with the columnar structures 211 .

Exemplarily, the patterning of the memory module material layer 220 may adopt a self-aligned double patterning (Self-Aligned Double Patterning, referred to as SADP) process or a self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, referred to as SAQP) process accomplish.

Exemplarily, the storage module 22 is a magnetic random access storage module. For example, the storage module 22 is a magnetic tunnel junction (Magnetic Tunnel Junction, MTJ for short) arranged in a columnar shape. Optionally, the MTJ includes a free layer (free layer), a fixed layer (fixed layer) and an oxide layer (Tunneling oxide) stacked in a direction away from the substrate. But not limited thereto, other types of storage modules are also applicable.

It can be seen from the foregoing embodiments that the storage module 22 has the same size as the columnar structure 211 , that is to say, one storage module 22 is correspondingly disposed on one columnar structure 211 (that is, on the drain 214 of the surrounding gate transistor 21 ). In this way, it is beneficial to ensure that the memory device 100 has higher density integration capability.

In step S18 , referring to FIG. 18 and FIG. 19 , a plurality of bit lines 6 arranged in parallel and spaced apart are formed above the memory module 22 , including the following steps.

For example, referring to FIG. 18 , a storage node contact structure 5 is formed on the storage module 22 , and the storage node contact structure 5 at least partially covers the storage module 22 .

Optionally, the shape of the orthographic projection of the storage node contact structure 5 on the substrate 1 includes a rectangle. In this way, when the storage module 22 is a columnar MTJ, the storage node contact structure 5 adopts a rectangular structure, and the storage node contact structure 5 at least partially covers the MTJ, so that it is easy for the storage node contact structures 5 in adjacent columns to exist in the same column. A straight line or part of an area lying alongside the same straight line.

Optionally, the storage node contact structure 5 is a metal pad, which may be a tungsten pad. Therefore, it can be ensured that the storage node contact structure 5 has a lower resistance value and higher stability.

Referring to FIG. 19 , a plurality of bit lines 6 arranged in parallel and spaced apart are formed above the storage node contact structure 5 . The bit lines 6 extend along a second direction which intersects the first direction, for example perpendicularly. The bit line 6 is correspondingly connected to the storage module 22 through the storage node contact structure 5 .

Here, the second direction may be the column direction, or may be a direction that forms an angle with the column direction.

In addition, the bit line 6 can be formed by first forming a metal material layer and then patterning the metal material layer. The patterning of the metal material layer can be realized by using a Self-Aligned Double Patterning (SADP for short) process or a Self-Aligned Quadruple Patterning (SAQP for short) process.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present disclosure, and the description thereof is relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the scope of protection of the disclosed patent should be based on the appended claims.

Claims

A memory device comprising:

Substrate;

a common source line arranged on the substrate;

A plurality of gate word lines are arranged in parallel and spaced above the common source line; the gate word lines extend along a first direction;

A plurality of columnar structures are arranged in an array on the common source line and run through the gate word line; the columnar structures in adjacent rows are misaligned along the row direction, and the columnar structures in adjacent columns are displaced along the column direction dislocation;

And, the gate dielectric layer is located between the column structure and the gate word line.
The storage device according to claim 1, wherein the storage device further comprises: a plurality of storage modules; the storage modules are correspondingly disposed above the columnar structure and connected to the columnar structure.
The storage device according to claim 2, wherein the storage device further comprises:

A plurality of bit lines are arranged in parallel and spaced above the memory module; the bit lines extend along a second direction and are correspondingly connected to the memory module; the second direction intersects the first direction.
The storage device according to claim 3, wherein the storage device further comprises: a plurality of storage node contact structures; the storage node contact structures are located on the storage module and at least partially cover the storage module;

The bit line is correspondingly connected to the storage module through the storage node contact structure.
The memory device of claim 2, wherein the memory module includes a magnetic tunnel junction.
The memory device according to claim 1, wherein,

The common source line includes doped silicon;

The columnar structure includes single crystal silicon.
The storage device according to any one of claims 1 to 6, wherein,

The distance between two adjacent columnar structures in any row is the first distance;

The misalignment distance of the columnar structures in adjacent columns along the column direction is smaller than the first distance.
The method for manufacturing a storage device according to claim 7, wherein the dislocation distance of the columnar structures in adjacent columns along the column direction is less than or equal to a second distance; the second distance is greater than 0.5 times the first distance , and is smaller than the first distance.
The memory device according to claim 7, wherein a distance of misalignment of the columnar structures in adjacent rows along the row direction is less than or equal to 0.5 times the first distance.
A method of manufacturing a memory device, comprising:

providing a substrate on which a common source line is formed;

A plurality of columnar structures arranged in an array are formed on the common source line, wherein the columnar structures in adjacent rows are displaced along the row direction, and the columnar structures in adjacent columns are displaced along the column direction;

forming a gate dielectric layer on the sidewall of the columnar structure;

forming a first dielectric layer penetrated by the columnar structure and the gate dielectric layer on the common source line;

A plurality of gate word lines arranged in parallel at intervals are formed on the first dielectric layer, wherein the columnar structure arranged along the first direction and the gate dielectric layer outside it penetrate the same gate word line ;

A second dielectric layer covering the gate word line and penetrating through the columnar structure and the gate dielectric layer is formed on the first dielectric layer.
The method for manufacturing a storage device according to claim 10, wherein the method of manufacturing further comprises:

A storage module is formed above the columnar structure, and the storage module is correspondingly connected to the columnar structure.
The method for manufacturing a storage device according to claim 11, wherein the method of manufacturing further comprises:

A plurality of bit lines arranged in parallel and at intervals are formed above the memory module; the bit lines extend along a second direction and are correspondingly connected to the memory module; the second direction intersects the first direction.
The method for manufacturing a storage device according to claim 12, wherein,

Before forming a plurality of bit lines arranged in parallel and at intervals above the memory module, the manufacturing method further includes: forming a storage node contact structure on the memory module, the storage node contact structure at least partially covering the memory module ;

The forming a plurality of bit lines arranged in parallel and at intervals above the memory module includes: forming a plurality of bit lines arranged in parallel and at intervals above the storage node contact structure, so that the bit lines pass through the The storage node contact structure is correspondingly connected to the storage module.
The method for fabricating a memory device according to claim 11, wherein the memory module includes a columnar magnetic tunnel junction.
The method for fabricating a storage device according to claim 11, wherein the surface of the columnar structure facing away from the substrate is higher than the surface of the gate dielectric layer facing away from the substrate;

The storage module formed above the columnar structure includes:

A third dielectric layer penetrated by the columnar structure is formed on the second dielectric layer and the gate dielectric layer, the surface of the third dielectric layer facing away from the substrate and the surface of the columnar structure away from the The surface of the substrate is even;

A storage module material layer is formed on the third medium layer and the columnar structure, and the storage module material layer is patterned to obtain a storage module in one-to-one contact with the columnar structure.
The method for manufacturing a storage device according to claim 10, wherein the forming a common source line on the substrate, and forming a plurality of columnar structures arranged in an array on the common source line, comprises:

epitaxially growing a silicon-doped layer and a single-crystal silicon layer on the substrate in sequence, the silicon-doped layer forming the common source line;

The single crystal silicon layer is patterned to obtain a plurality of columnar structures.
The method for fabricating a storage device according to claim 10, wherein a surface of the second dielectric layer facing away from the substrate is flush with a surface of the gate dielectric layer facing away from the substrate.
The method for manufacturing a storage device according to any one of claims 10 to 17, wherein,

The distance between two adjacent columnar structures in any row is the first distance;

The misalignment distance of the columnar structures in adjacent columns along the column direction is smaller than the first distance.
The method for manufacturing a memory device according to claim 18, wherein the dislocation distance of the columnar structures in adjacent columns along the column direction is less than or equal to a second distance; the second distance is greater than 0.5 times the first distance , and is smaller than the first distance.
The method for fabricating a memory device according to claim 18, wherein the columnar structures in adjacent rows are misaligned along a row direction by a distance less than or equal to 0.5 times the first distance.