WO2024046019A1

WO2024046019A1 - Manufacturing method for semiconductor structure, and structure

Info

Publication number: WO2024046019A1
Application number: PCT/CN2023/110792
Authority: WO
Inventors: 唐怡
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-29
Filing date: 2023-08-02
Publication date: 2024-03-07
Also published as: CN115458483A

Abstract

Provided in the embodiments of the present disclosure are a manufacturing method for a semiconductor structure, and the structure. The manufacturing method for a semiconductor structure comprises: providing a substrate; forming, on a surface of the substrate, stacked structures arranged at intervals in a first direction, and first isolation layers located between adjacent stacked structures; etching part of each of initial active layers to form a first trench; forming a first metal conductive layer in the first trench; etching part of each of first interlayer dielectric layers and part of each of second interlayer dielectric layers to form second trenches; forming second metal conductive layers in the second trenches, wherein the second metal conductive layers cover side walls of the second trenches and are in contact connection with the first metal conductive layers; and etching part of each of the first metal conductive layers and part of each of the second metal conductive layers, so as to form lower electrode structures arranged in an array in the first direction and a second direction.

Description

Semiconductor structure manufacturing method and structure

cross reference

This disclosure claims priority to the Chinese patent application titled "Production Method and Structure of Semiconductor Structure" and application number 202211043536.2, which was submitted on August 29, 2022, which is fully incorporated by reference into this disclosure.

Technical field

Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor manufacturing method and its structure.

Background technique

With the continuous development of semiconductor structures, its critical dimensions continue to decrease. However, due to the limitations of photolithography machines, there is a limit to the reduction of its critical dimensions. Therefore, how to make a higher storage density chip on a wafer is a matter of many scientific researches. Research directions for workers and semiconductor practitioners. In two-dimensional or planar semiconductor devices, the memory cells are arranged in the horizontal direction. Therefore, the integration density of the two-dimensional or planar semiconductor device can be determined by the area occupied by the unit memory unit. The integration density of the two-dimensional or planar semiconductor device is extremely high. The earth is affected by the technology of forming fine patterns, so that there is a limit to the continued increase in the integration density of two-dimensional or planar semiconductor devices. Therefore, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

However, in three-dimensional semiconductor devices, there is still a continuous pursuit of better performance.

Contents of the invention

Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and its structure, which can at least improve the performance of the semiconductor structure.

According to some embodiments of the present disclosure, on the one hand, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which includes: providing a substrate; forming stacked structures spaced apart along a first direction on the surface of the substrate and adjacent to the stacked structures. A first isolation layer between structures, the stacked structure includes a first interlayer dielectric layer, an initial active layer and a second interlayer dielectric layer; etching part of the initial active layer to form a first trench; Form a first metal conductive layer in the first trench, the first metal conductive layer fills the first trench and is in contact with the remaining initial active layer; etching part of the first metal conductive layer an interlayer dielectric layer and the second interlayer dielectric layer to form a second trench; a second metal conductive layer is formed in the second trench, and the second metal conductive layer covers the second trench The sidewalls are in contact with the first metal conductive layer; etching part of the first metal conductive layer and the second metal conductive layer to form an array arranged along the first direction and the second direction. Lower electrode structure; the first direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface.

In some embodiments, after forming the lower electrode structure, it further includes: forming a capacitive dielectric layer covering the surfaces of the first metal conductive layer and the second metal conductive layer; forming an upper electrode structure, The upper electrode structure is located on the surface of the capacitive dielectric layer and fills the second trench. The lower electrode structure, the capacitive dielectric layer and the upper electrode structure constitute the capacitor.

In some embodiments, before forming the capacitive dielectric layer, the method further includes: forming a filling layer that fills the second trench and exposes the first metal conductive layer and the second metal conductive layer. sidewalls; etching the sidewalls of the first metal conductive layer and the second metal conductive layer to form the lower electrode structure; and removing the filling layer to expose the surface of the lower electrode structure.

In some embodiments, the step of forming the capacitive dielectric layer includes: forming the capacitive dielectric layer covering the sidewalls of the first isolation layer to form all the capacitive dielectric layers sharing the capacitive dielectric layer in the first direction. Describe the capacitor.

In some embodiments, the method further includes: etching the remainder of the initial active layer to form a third trench; An oxide semiconductor layer is formed, the oxide semiconductor layer is located in the third trench, and the oxide semiconductor layer is in contact with the first metal conductive layer.

In some embodiments, after forming the oxide semiconductor layer, the manufacturing method of the semiconductor structure includes: etching the oxide semiconductor layer and the remaining first metal conductive layer to form a fourth trench and The oxide semiconductor layer is spaced apart and the first metal conductive layer is spaced apart, and the fourth trench separates the stacked structure along the second direction; the remaining oxide semiconductor layer constitutes an active structure .

In some embodiments, after etching part of the oxide semiconductor layer, the manufacturing method of the semiconductor structure further includes: forming a second isolation layer, the second isolation layer being located in a phase arranged along the second direction. The second isolation layer is between the adjacent oxide semiconductor layers and fills the fourth trench.

In some embodiments, the material of the oxide semiconductor layer includes: indium gallium zinc oxide or zinc tin oxide.

In some embodiments, forming the oxide semiconductor layer further includes: forming a word line, the word line surrounds the surface of the oxide semiconductor layer, and the word line is along the first direction or the third direction. Extending in one of the two directions; forming a bit line, the bit line surrounds the surface of the oxide semiconductor layer, the bit line is spaced from the word line, and the bit line is along the first direction or the extends in the other of the second directions.

According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor structure, including: a substrate; active structures located on the surface of the substrate and arranged at intervals along the first direction and the second direction; and the The active structure corresponds to the electrically connected lower electrode structure one by one, the first direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface; a first isolation layer, the first isolation layer is located on between the adjacent active structures in the first direction, and between the lower electrode structures adjacent in the first direction; the lower electrode structure includes: a first metal conductive layer and a second metal conductive layer layer, the second metal conductive layer includes a first side, the first side is in contact with the first metal conductive layer, and a second side, the second side is directly opposite to the first side and is connected to the first side. The first isolation layer is in contact with the third side, and the third side is connected with the first side and the second side.

In some embodiments, it also includes: a capacitive dielectric layer covering the surface of the second metal conductive layer and the sidewall of the first metal layer; an upper electrode structure covering all The surface of the capacitive dielectric layer, the lower electrode structure, the capacitive dielectric layer and the upper electrode structure constitute a capacitor.

In some embodiments, the capacitive dielectric layer also covers sidewalls of the first isolation layer to form the capacitor sharing the capacitive dielectric layer along the first direction.

In some embodiments, the projection of the upper electrode structure on the substrate is within the projection of the lower electrode structure within the substrate.

In some embodiments, the material of the active structure is an oxide semiconductor.

In some embodiments, further comprising: a word line surrounding a surface of the active structure and extending along one of the first direction or the second direction; a bit line , the bit line surrounds the surface of the oxide semiconductor layer, the bit line is spaced apart from the word line, and the bit line extends along the other one of the first direction or the second direction.

Description of drawings

One or more embodiments are exemplified by the pictures in the corresponding drawings. These illustrative illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a limitation on proportions; in order to To more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

1 to 25 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by embodiments of the present disclosure.

Detailed ways

It can be seen from the background technology that as the integration level continues to shrink, three-dimensional semiconductor devices are still pursuing higher storage density, faster speed and lower power consumption.

The present disclosure provides a method for manufacturing a semiconductor structure by forming a first isolation layer between stacked structures spaced along a first direction on a surface of a substrate, and then etching the initial active layer to form a first isolation layer. trench, and form a first metal conductive layer in the first trench, etch part of the first interlayer dielectric layer and the second interlayer dielectric layer to form a second trench, and form a second trench in the second trench. A metal conductive layer, and etching the first metal conductive layer and the second metal conductive layer to form a lower electrode structure arranged in an array. The lower electrode structure formed by the first metal conductive layer and the second metal conductive layer can increase the capacity of the capacitor. This can improve the performance of semiconductor structures.

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to allow the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present disclosure can also be implemented.

Referring to FIGS. 1 to 25 , FIGS. 1 to 25 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

Specifically, refer to FIGS. 1 and 2 , wherein FIG. 1 is a top view of the semiconductor structure, and FIG. 2 is a cross-sectional view along the direction AA in FIG. 1 .

Specifically, a substrate 100 is provided, and stacked structures 110 arranged at intervals along the first direction 130. Initial active layer 140 and second interlayer dielectric layer 150.

In some embodiments, the substrate 100 is a semiconductor material, and the semiconductor material includes but is not limited to any one of a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon carbide substrate. The substrate 100 can also be an ion-doped substrate. The doping ions are N-type ions or P-type ions. The N-type ions can be phosphorus ions, arsenic ions or antimony ions, and the P-type ions can be boron ions, indium ions or antimony ions. Boron fluoride ion.

In some examples, the material of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 can be the same, and both can be insulating materials such as silicon oxide. By forming the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 , The dielectric layer 150 can provide a basis for subsequent formation of bit lines, and can also isolate the initial active layers 140 arranged at intervals in the first direction X by the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 .

The material of the initial active layer 140 may be silicon carbide or polysilicon semiconductor material. The formation of the initial active layer 140 may provide a process basis for the subsequent formation of an active structure arranged in an array.

Referring to FIG. 3 , a portion of the initial active layer 140 is etched to form a first trench 160 . The formation of the first trench 160 can provide a process basis for subsequent formation of an oxide semiconductor layer.

In some embodiments, the method of etching part of the initial active layer 140 may be by using wet etching to etch the initial active layer 140 through the sidewalls of the stacked structure 110 .

Referring to FIG. 4 , a first metal conductive layer 170 is formed in the first trench 160 . The first metal conductive layer 170 fills the first trench 160 and is in contact with the remaining initial active layer 140 . The first metal conductive layer 170 may serve as part of the lower electrode structure of the capacitor.

In some embodiments, the material of the first metal conductive layer 170 may be titanium, titanium nitride, cobalt, nickel, or the like.

In some embodiments, the material of the first metal conductive layer 170 can also be a metal semiconductor material, in which case part of the first metal conductive layer 170 can also serve as the drain of the active structure.

Referring to FIG. 5 , parts of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 are etched to form a second trench 180 . The formation of the second trench 180 can provide a process basis for the subsequent formation of a second metal conductive layer. .

In some embodiments, when etching the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150, only a portion of the surface of the first metal conductive layer 170 is exposed. That is to say, in the third direction Z, etching first layer of erosion The lengths of the interlayer dielectric layer 130 and the second interlayer dielectric layer 150 are less than the length of the first metal conductive layer 170 . Therefore, the length of the subsequently formed second metal conductive layer can be controlled, and the second metal conductive layer can be prevented from contacting the gate electrode or word line of the active structure, thereby improving the reliability of the semiconductor structure. In other embodiments, the lengths of the etched first interlayer dielectric layer and the second interlayer dielectric layer can also be equal to the length of the first metal conductive layer, thereby increasing the length of the second metal conductive layer, thereby increasing the length of the second metal conductive layer. The length of the lower electrode structure of the semiconductor structure can thereby improve the performance of the semiconductor structure.

Referring to FIG. 6 , a second metal conductive layer 190 is formed in the second trench 180 . The second metal conductive layer 190 covers the sidewalls of the second trench 180 and is in contact with the first metal conductive layer 170 . By forming the second metal conductive layer 190 , the second metal conductive layer 190 is formed in the second trench 180 . The conductive layer 190 can increase the facing area between the lower electrode structure and the subsequently formed upper electrode structure, thereby increasing the capacitance of the capacitor, thereby improving the performance of the semiconductor structure.

Referring to FIGS. 7 to 10 , parts of the first metal conductive layer 170 and the second metal conductive layer 190 are etched to form a lower electrode structure 200 arranged in an array along the first direction X and the second direction Y; the first direction X is vertical. On the surface of the substrate 100 , the second direction Y is parallel to the surface of the substrate 100 . The spaced lower electrode structure 200 can be formed by etching the first metal conductive layer 170 and the second metal conductive layer 190, thereby providing a process basis for subsequent formation of spaced capacitors.

In some embodiments, before forming the capacitive dielectric layer, the process further includes: forming a filling layer 210 that fills the second trench 180 and exposes the sidewalls of the first metal conductive layer 170 and the second metal conductive layer 190; and etching. The sidewalls of the first metal conductive layer 170 and the second metal conductive layer 190 are etched to form the lower electrode structure 200; the filling layer 210 is removed to expose the surface of the lower electrode structure 200. It can be understood that during the process of forming the second metal conductive layer 190, part of the second metal conductive layer 190 also covers part of the first metal conductive layer 170 and the sidewalls of the first isolation layer 120, and subsequent steps can be performed by forming the filling layer 210. During etching, the first metal conductive layer 170 and the second metal conductive layer 190 located on the inner wall of the second trench 180 are protected, and the first metal conductive layer 170 and the second metal conductive layer 190 exposed by the etching filling layer 210 are at The side walls in the three directions Z, that is, partition the second metal conductive layer 190 connected in the first direction Structure 200 in series. By exposing the sidewalls of the first metal conductive layer 170 and the second metal conductive layer 190 through the filling layer 210, the unnecessary portion of the second metal conductive layer 190 can be simultaneously etched during the etching process. Referring to FIG. 8 , lower electrode structures 200 spaced in the second direction are formed by etching part of the stack structure to form trenches extending along the third direction Z and penetrating the stack structure 110 in the first direction X. Next, referring to FIG. 10. Removing the filling layer provides a process basis for the subsequent formation of the dielectric layer and upper electrode structure.

Referring to Figures 11 and 12, forming the lower electrode structure also includes: forming a capacitive dielectric layer 220 covering the surfaces of the first metal conductive layer 170 and the second metal conductive layer 190; forming an upper electrode structure 230, the upper electrode The structure 230 is located on the surface of the capacitive dielectric layer 220 and fills the second trench 180 . The lower electrode structure 200 , the capacitive dielectric layer 220 and the upper electrode structure 230 form the capacitor 240 . By forming the capacitor 240 and utilizing different states of the capacitor 240, the '0' state or the '1' state of the semiconductor structure can be represented to achieve data storage, where the '0' state can represent a low level and a '1' state. Can represent high level.

In some embodiments, the step of forming the capacitive dielectric layer 220 includes forming the capacitive dielectric layer 220 covering the sidewalls of the first isolation layer 120 to form the capacitor 240 sharing the capacitive dielectric layer 220 in the first direction X. The steps of forming the capacitor 240 can be reduced by forming the capacitor 240 that shares the capacitive dielectric layer 220 in the first direction

In some embodiments, as shown in FIG. 9 , forming the lower electrode structure 200 arranged in an array further includes forming a third isolation layer 250 . The third isolation layer 250 can be used to isolate adjacent capacitors 240 . The third isolation layer 250 is filled in the trench extending along the third direction Z and penetrating the stacked structure 110 in the first direction X to isolate the adjacent lower electrode structure 200 in the second direction Y.

In some embodiments, the process of removing the filling layer 210 also includes: removing the third isolation layer 250 in the same process step, and then forming the capacitive dielectric layer 220 and the upper electrode structure 230 after removing the third isolation layer 250, so , the capacitors 240 arranged along the second direction Y also share the capacitive dielectric layer 220 and the upper electrode structure 230. That is to say, the capacitors 240 arranged along the first direction X and the second direction Y share the capacitive dielectric layer 220 and the upper electrode. Structure 230.

In some embodiments, the material of the third isolation layer 250 can be the same as the material of the filling layer 210 , and both can be insulating materials such as silicon oxide or silicon nitride. In other embodiments, the material of the third isolation layer 250 can also be The material of the filling layer 210 may be different.

The material of the lower electrode structure 200 may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper or tungsten; the material of the capacitor dielectric layer 220 may include: ZrO, AlO, ZrNbO, ZrHfO, ZrAlO Any one or any combination thereof; the material of the upper electrode structure 230 includes a compound formed of one or two of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, silicon nitride Titanium or other conductive materials, or the material of the upper electrode structure 230 can also be conductive semiconductor materials, such as polysilicon, silicon germanium, etc.

It can be understood that the relative area between the lower electrode structure 200 and the upper electrode structure 230 of the capacitor 260, the distance between the lower electrode structure 200 and the upper electrode structure 230, and the material of the capacitor dielectric layer 220 may affect the capacity of the capacitor 260. The relative area between the lower electrode structure 200 and the upper electrode structure 230 of the capacitor 260, the distance between the lower electrode structure 200 and the upper electrode structure 230, and the material of the capacitor dielectric layer 220 can be set according to actual needs.

Referring to FIGS. 13 and 14 , the manufacturing method of the semiconductor structure further includes: etching the remaining initial active layer 140 to form a third trench 270 ; forming an oxide semiconductor layer 280 located in the third trench 270 Inside, the oxide semiconductor layer 280 is in contact with the first metal conductive layer 170 . The formation of the oxide semiconductor layer 280 can provide a process basis for forming the active structure, and the subsequent formation of the active structure through the oxide semiconductor layer 280 can improve the carrier transmission rate of the active structure.

In some embodiments, the material of the oxide semiconductor layer 280 may include: indium gallium zinc oxide or zinc tin oxide. By setting the material of the oxide semiconductor layer to be indium gallium zinc oxide or zinc tin oxide, the performance of the oxide semiconductor can be improved. The ion mobility of the layer 280 can thereby improve the performance of the subsequent oxide semiconductor layer 280 as a channel region. The material of the oxide semiconductor layer 280 may also be indium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, magnesium zinc oxide, zirconium indium zinc oxide, hafnium Indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide and other similar materials Or multiple.

Referring to FIG. 15 , in some embodiments, after forming the oxide semiconductor layer 280 , the fabrication method of the semiconductor structure further includes: etching the oxide semiconductor layer 280 and the remaining first metal conductive layer 170 to form a fourth trench 290 As well as the spaced oxide semiconductor layer 280 and the spaced first metal conductive layer 170, the fourth trench 290 separates the stacked structure 110 along the second direction Y, and the remaining oxide semiconductor layer 280 constitutes an active structure. By forming the fourth trench 290, the oxide semiconductor layer 280 and the first metal conductive layer 170 can be cut off, that is to say, the active structure and the capacitor 260 spaced along the second direction Y can be formed. It can be understood that in the previous In this step, only part of the first metal conductive layer 170 is etched. That is, the capacitors 260 arranged along the second direction Y are still connected through the first metal conductive layer 170. The capacitors 260 can be arranged along the second direction Y by forming the fourth trench 290. Y interval.

Referring to FIG. 16 , in some embodiments, after etching part of the oxide semiconductor layer 280 , the manufacturing method of the semiconductor structure further includes: forming a second isolation layer 310 , the second isolation layer 310 is located in a phase arranged along the second direction Y. The second isolation layer 310 fills the fourth trench 290 between adjacent oxide semiconductor layers 280 . By forming the second isolation layer 310, the insulation of adjacent active structures can be improved, thereby improving the reliability of the semiconductor structure.

Referring to FIGS. 17 to 25 , in some embodiments, forming the oxide semiconductor layer 280 further includes: forming a word line 320 , the word line 320 surrounds the surface of the oxide semiconductor layer 280 , and the word line 320 is along the first direction X or One of the second directions Y extends; a bit line 350 is formed, the bit line 350 surrounds the surface of the oxide semiconductor layer 280, the bit line 350 is spaced from the word line 320, and the bit line 350 is along the first direction X or the second direction Y extension of the other.

Specifically, referring to FIG. 17 , in some embodiments, after forming the second isolation layer 310 , the method further includes: etching part of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 to expose part of the active structure 300 . surface, thereby providing a process basis for later forming word lines.

In some embodiments, forming the word line 320 further includes forming a gate dielectric layer 340 , and the gate dielectric layer 340 is located on the surface of the active structure 300 . By forming the gate dielectric layer 340, the word line 320 can be prevented from interacting with the active The structures 300 are in direct contact, thereby avoiding semiconductor structural anomalies.

In some embodiments, the material of the gate dielectric layer 340 may be an insulating material such as silicon oxide, silicon nitride, or hafnium oxide. The material of the gate dielectric layer 340 may be selected according to the required dielectric constant of the gate dielectric layer 340 . .

In some embodiments, the thickness of the gate dielectric layer 340 may be 8-20 nm. It can be understood that, under other conditions being equal, the thinner the thickness of the gate dielectric layer 340, the better the performance of the semiconductor structure. , but the reliability of the semiconductor structure is lower, and the current tunneling effect is more likely to occur. The corresponding thickness of the gate dielectric layer 340 is thicker, and the reliability of the semiconductor structure is higher, but the performance of the semiconductor structure will decrease. By setting the thickness of the gate dielectric layer 340 to 8 to 20 nm, a certain degree of reliability can be ensured while improving the performance of the semiconductor structure.

Forming the gate dielectric layer 340 and the first isolation layer 120 can also help the oxide semiconductor layer 280 of the active structure 300 to isolate oxygen and water vapor in the air, thereby improving the reliability of the semiconductor structure.

Referring to FIGS. 18 to 23 , a word line 320 is formed. In some embodiments, the word line 320 includes: a first word line 321 and a second word line 322 . The first word line 321 is arranged around the active structure 300 , and the second word line 320 is formed. Line 322 covers the sidewall of first word line 321. By forming the first word line 321 surrounding the active structure 300, the contact area between the word line 320 and the active structure 300 can be increased, and by forming the second word line 322, a contact basis can be provided for the subsequent formation of conductive pillars corresponding to the word line 320. . In other embodiments, the first word line may only cover part of the surface of the active structure. Taking the shape of the active structure as a rectangular parallelepiped as an example, the first word line may only cover the top and bottom surfaces of the active structure, or may be covered with The top and bottom surfaces of the source structure and one of the side surfaces connected to the top and bottom surfaces.

Referring to FIG. 18 , in some embodiments, a first word line 321 is formed, and the first word line 321 is located on the surface of the gate dielectric layer 340 .

Referring to FIG. 19 , FIG. 19 is a cross-sectional view along the BB direction in the direction of FIG. 1 . It can be understood that FIG. 19 does not include any process steps based on FIG. 18 , but is only a cross-sectional view of the semiconductor structure from different perspectives.

Referring to FIG. 20 , the stacked structure 110 is etched along the second direction Y to form a fifth trench 330 . The fifth trench 330 exposes the sidewalls of the first word line 321 . By forming the fifth trench 330 , the second word line 330 can be formed. Line 322 provides the process foundation.

Referring to FIG. 21 , a second initial word line 323 is formed, and the second initial word line 323 fills the fifth trench 330 .

Referring to Figure 22, the second initial word line 323 and the first isolation layer 120 are etched, and the remaining second initial word line 323 serves as the second word line 322. In some embodiments, the second words arranged along the first direction The length of the line 322 in the second direction Y decreases sequentially. That is to say, the length of the second word line 322 decreases sequentially from the direction approaching the substrate 100 to the direction away from the substrate 100 . Taking the three second word lines 322 in the figure as an example, the second word line 322 closest to the substrate 100 is called a first sub-word line, and the second word line 322 located in the middle is called a second sub-word line. 100 The farthest second word line 322 becomes the third sub-word line, wherein, along the second direction, the length of the first sub-word line, the length of the second sub-word line, and the length of the third sub-word line decrease in sequence. , so that conductive pillars can be subsequently formed on the part of the first sub-word line that is longer than the second sub-word line, and conductive pillars can be formed on the part of the second sub-word line that is longer than the third sub-word line, so that different word lines 320 can be combined. Signals are brought out, or corresponding electrical signals are provided to different word lines 320 .

Referring to FIG. 23 , part of the first word line 321 and the gate dielectric layer 340 are etched to expose part of the surface of part of the active structure 300 , thereby providing a process basis for subsequent formation of bit lines.

Referring to FIG. 24 , a bit line 350 is formed. In some embodiments, taking the bit line 350 extending along the first direction X as an example, the bit line 350 may be in contact with a plurality of active structures 300 arranged along the first direction. The connection, that is, the bit line 350 can transmit signals to a plurality of active structures 300 arranged along the first direction X, thereby increasing the stacking density of the semiconductor structure and improving the space utilization of the semiconductor structure.

However, it can be understood that the extending direction of the bit line 350 intersects the extending direction of the word line 320, and there is only one intersection point between the bit line 350 and a word line 320, that is, through a word line 320 and a bit line 350 may select an active structure 300.

In some embodiments, forming the bit line 350 further includes: forming a fourth isolation layer 360, the fourth isolation layer 360 covers part of the surface of the active structure 300, and the fourth isolation layer 360 and the word line 320 are along the third direction Z. The sidewalls of the arrangement are contacted and connected; a bit line 350 is formed, and the bit line 350 covers and is arranged in the third direction Z with the fourth isolation layer 360 The sidewall contacts are connected, and the bit line 350 covers the active structure 300 . By forming the fourth isolation layer 360, the bit line 350 can be isolated from the first word line 321, thereby avoiding electrical connection between the bit line 350 and the word line 320, thereby improving the reliability of the semiconductor structure. By forming the bit line 350 Provides the basis for reading data and writing data into semiconductor structures.

In some embodiments, forming the fourth isolation layer 360 may include: forming a fourth initial isolation layer located between the first isolation layer 120 and the active structure 300; etching the fourth initial isolation layer , the remaining fourth initial isolation layer serves as the fourth isolation layer 360 .

In some embodiments, etching the fourth initial isolation layer also includes: etching the first isolation layer 120 . In the process of forming the bit line 350 , the formed bit line 350 may also cover the sidewall of the first isolation layer 120 .

Referring to Figures 1 and 25, the manufacturing method of the semiconductor structure also includes: forming a conductive pillar 370, a conductive pillar 370 is connected to a word line 320, and the word line 320 can be controlled by providing an electrical signal to the conductive pillar 370 through the conductive pillar 370. By providing signals to different conductive pillars 370, electrical signals are provided to the word lines 320 connected to the conductive pillars 370. That is to say, different word lines can be controlled by controlling different conductive pillars 370. 320.

The embodiment of the present disclosure forms the first isolation layer 120 between adjacent stack structures 110 spaced along the first direction X on the surface of the substrate 100, and then etches the initial active layer 140 to form the first trench 160. , and form the first metal conductive layer 170 in the first trench 160, and etch parts of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 to form the second trench 180. In the second trench 180 A second metal conductive layer 190 is formed inside, and the first metal conductive layer 170 and the second metal conductive layer 190 are etched to form an array-arranged lower electrode structure 200. Through the first metal conductive layer 170 and the second metal conductive layer 190 Forming the lower electrode structure 200 can increase the capacity of the capacitor 240, thereby improving the performance of the semiconductor structure.

Embodiments of the present disclosure also provide a semiconductor structure, which can be formed through some or all steps of the above-mentioned method for manufacturing a semiconductor structure. The same or corresponding parts can be referred to the above-mentioned embodiments, which will not be described in detail below. The present invention will be described below with reference to the accompanying drawings. The semiconductor structure provided in the disclosed embodiment will be described.

Referring to Figures 1, 22, 24 and 25, the semiconductor structure may include: a substrate 100; active structures 300 located on the surface of the substrate 100 and arranged at intervals along the first direction X and the second direction Y; and the active structures 300 For the lower electrode structure 200 that is electrically connected in a one-to-one correspondence, the first direction between adjacent active structures 300 and between adjacent lower electrode structures 200 in the first direction X; the lower electrode structure 200 includes: a first metal conductive layer 170 and a second metal conductive layer 190. The conductive layer 190 includes a first side that is in contact with the first metal conductive layer 170 , a second side that is directly opposite to the first side and in contact with the first isolation layer 120 , a third side that is in contact with the first isolation layer 120 . The side surface is connected to the first side surface and the second side surface.

The second metal conductive layer 190 is provided with three sides, wherein the first side is in contact with the first metal conductive layer 170 and the second side is directly opposite to the first side and in contact with the first isolation layer 120 , the third side, the third side is connected to the first side and the second side, so that the facing area between the lower electrode structure 200 of the capacitor and the capacitor dielectric layer and the upper electrode structure can be increased, so that the capacitance of the capacitor can be increased, and the capacitance of the capacitor can be increased. Properties of Semiconductor Structures.

In some embodiments, the semiconductor structure may further include: a capacitive dielectric layer 220 covering the surface of the second metal conductive layer 190 and the sidewalls of the first metal conductive layer 170; an upper electrode structure 230, an upper electrode structure 230 Covering the surface of the capacitive dielectric layer 220 , the lower electrode structure 200 , the capacitive dielectric layer 220 and the upper electrode structure 230 form a capacitor 240 . The distance between the lower electrode structure 200 and the upper electrode structure 230 of the capacitor 240 and the material of the capacitor dielectric layer 220 may affect the capacity of the capacitor 240. Therefore, the lower electrode structure 200 and the upper electrode of the capacitor 240 can be set according to actual needs. The spacing between the structures 230, the facing area between the lower electrode structure 200 and the upper electrode structure 230, and the material of the capacitive dielectric layer 220.

In some embodiments, the capacitive dielectric layer 220 may also cover the sidewalls of the first isolation layer 120 to form a capacitor 240 that shares the capacitive dielectric layer 220 along the first direction X. By disposing the capacitive dielectric layer 220 to cover the first barrier The sidewalls of the separation layer 120 can reduce the process steps of the semiconductor structure, and the space utilization of the semiconductor structure can also be improved by arranging the capacitor 240 sharing the capacitive dielectric layer 220 .

In some embodiments, the projection of the upper electrode structure 230 on the substrate 100 is within the projection of the lower electrode structure 200 within the substrate 100 . In other words, in the third direction Z, the length of the upper electrode structure 230 is shorter than the length of the lower electrode structure 200 . By setting the length of the upper electrode structure 230 to be shorter than the length of the lower electrode structure 200 , the manufacturing difficulty of the semiconductor structure can be reduced, and Exposure of the second metal conductive layer 190 during the formation of the word line 320 can be avoided, thereby improving the reliability of the semiconductor structure.

In some embodiments, the material of the active structure 300 may be an oxide semiconductor, and the active structure 300 is in contact with the first metal conductive layer 170 . By setting the material of the active structure 300 to be an oxide semiconductor, the activity of carriers in the active structure 300 can be increased, thereby increasing the carrier mobility in the active structure 300 .

In some embodiments, it may also include: a word line 320 surrounding the surface of the active structure 300 and extending along one of the first direction X or the second direction Y; a bit line 350. Lines 350 surround the surface of active structure 300, bit lines 350 are spaced apart from word lines 320, and bit lines 350 extend along the other of the first direction X or the second direction Y. By arranging the word line 320 to surround the surface of the active structure 300, the conduction of the active structure 300 can be controlled. By arranging the bit line 350 to surround the surface of the active structure 300, the semiconductor structure can be read and written through the bit line 350.

In some embodiments, the semiconductor structure further includes: a gate dielectric layer 340 located on the surface of the active structure 300 . By forming the gate dielectric layer 340, direct contact between the word line 320 and the active structure 300 can be avoided, thereby avoiding semiconductor structural abnormalities.

In some embodiments, the word line 320 includes: a first word line 321 and a second word line 322, the first word line 321 is arranged around the active structure 300, and the second word line 322 covers the sidewall of the first word line 321. By forming the first word line 321 surrounding the active structure 300, the contact area between the word line 320 and the active structure 300 can be increased, and by forming the second word line 322, a contact basis can be provided for the subsequent formation of conductive pillars corresponding to the word line 320. .

In some embodiments, the first word line 321 surrounds the surface of the gate dielectric layer 340 .

In some embodiments, the semiconductor structure further includes: a first interlayer dielectric layer 130 and a second interlayer dielectric layer 150. By providing the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150, the capacitance 240 and the word value can be improved. The insulation of the wire 320 can also support the semiconductor structure, thereby avoiding deformation of the semiconductor structure and improving the reliability of the semiconductor structure.

In some embodiments, the semiconductor structure may further include: a second isolation layer 310. The second isolation layer 310 is located between adjacent active structures 300 arranged along the second direction Y. The second isolation layer 310 can improve The insulation of adjacent active structures 300 can improve the reliability of the semiconductor structure.

In some embodiments, the semiconductor structure may further include: a fourth isolation layer 360, the fourth isolation layer 360 covers part of the surface of the active structure 300, and the fourth isolation layer 360 and the word lines 320 are arranged along the third direction Z. The sidewall contact connection can isolate the bit line 350 from the word line 320 through the fourth isolation layer 360, thereby avoiding electrical connection between the bit line 350 and the word line 320, thereby improving the reliability of the semiconductor structure.

In some embodiments, the semiconductor structure may also include: a conductive pillar 370. A conductive pillar 370 is correspondingly connected to a word line 320. The conductive pillar 370 can control the conduction and conduction of the word line 320 by providing an electrical signal to the conductive pillar 370. When disconnected, signals are provided to different conductive pillars 370, thereby providing electrical signals to the word lines 320 connected to the conductive pillars 370. That is to say, different word lines 320 can be controlled by controlling different conductive pillars 370.

The embodiment of the present disclosure disposes an active structure 300 on the surface of the substrate 100 and a lower electrode structure 200 electrically connected to the active structure in one-to-one correspondence. The lower electrode structure 200 includes a first metal conductive layer 170 and a second metal conductive layer. 190, and the second metal conductive layer 190 includes a first side, the first side is in contact with the first metal conductive layer 170, and a second side, the second side is directly opposite to the first side and in contact with the first isolation layer 120, The third side is connected to the first side and the second side. By increasing the surface area of the second metal conductive layer 190, the facing area between the lower electrode structure 200 and the upper electrode structure 230 in the capacitor 240 can be increased. The capacitance of the capacitor 240 is increased, thereby improving the performance of the semiconductor structure.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the scope of the embodiments of the present disclosure. spirit and scope. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the disclosed embodiments. Therefore, the protection scope of the disclosed embodiments should be subject to the scope defined by the claims.

Claims

A method of manufacturing a semiconductor structure, including:

provideBase(100);

Stacked structures (110) spaced apart along the first direction (X) and first isolation layers (120) located between adjacent stacked structures (110) are formed on the surface of the substrate (100). The structure (110) includes a first interlayer dielectric layer (130), an initial active layer (140), and a second interlayer dielectric layer (150);

Etching part of the initial active layer (140) to form a first trench (160);

A first metal conductive layer (170) is formed in the first trench (160). The first metal conductive layer (170) fills the first trench (160) and is in contact with the remaining initial conductive layer. Source layer (140) contact connection;

Etching part of the first interlayer dielectric layer (130) and the second interlayer dielectric layer (150) to form a second trench (180);

A second metal conductive layer (190) is formed in the second trench (180). The second metal conductive layer (190) covers the sidewall of the second trench (180) and is in contact with the first The metal conductive layer (170) is in contact connection;

Etching part of the first metal conductive layer (170) and the second metal conductive layer (190) to form a lower electrode structure arranged in an array along the first direction (X) and the second direction (Y) (200); the first direction (X) is perpendicular to the surface of the substrate (100), and the second direction (Y) is parallel to the surface of the substrate (100).
The method of manufacturing a semiconductor structure according to claim 1, wherein after forming the lower electrode structure (200), it further includes:

Form a capacitive dielectric layer (220), which covers the surfaces of the first metal conductive layer (170) and the second metal conductive layer (190);

An upper electrode structure (230) is formed. The upper electrode structure (230) is located on the surface of the capacitive dielectric layer (220) and fills the second trench (180). The lower electrode structure (200), The capacitor dielectric layer (220) and the upper electrode structure (230) constitute the capacitor (240).
The method of manufacturing a semiconductor structure according to claim 1 or 2, wherein before forming the capacitive dielectric layer (220), it further includes: forming a filling layer (210), the filling layer (210) filling the second trench (180), and expose the sidewalls of the first metal conductive layer (170) and the second metal conductive layer (190);

Etching the sidewalls of the first metal conductive layer (170) and the second metal conductive layer (190) to form the lower electrode structure (200);

The filling layer (210) is removed to expose the surface of the lower electrode structure (200).
The method for manufacturing a semiconductor structure according to claim 1 or 2, wherein the step of forming the capacitor dielectric layer (220) includes: forming the capacitor covering the sidewalls of the first isolation layer (120). A dielectric layer (220) to form the capacitor (240) sharing the capacitive dielectric layer (220) in the first direction (X).
The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, further comprising:

Etch the remaining initial active layer (140) to form a third trench (270);

Form an oxide semiconductor layer (280), the oxide semiconductor layer (280) is located in the third trench (270), the oxide semiconductor layer (280) and the first metal conductive layer (170) Contact connection.
The method of manufacturing a semiconductor structure according to claim 5, wherein after forming the oxide semiconductor layer (280), the method of manufacturing a semiconductor structure includes:

Etch the oxide semiconductor layer (280) and the remaining first metal conductive layer (170) to form a fourth trench (290) and the spaced oxide semiconductor layer (280) and all spaced parts. the first metal conductive layer (170), the fourth trench (290) spacing the stacked structure (110) along the second direction (Y);

The remaining oxide semiconductor layer (280) constitutes an active structure.
The method of manufacturing a semiconductor structure according to claim 6, wherein after etching part of the oxide semiconductor layer (280), the method of manufacturing a semiconductor structure further includes: forming a second isolation layer (310), A second isolation layer (310) is located between the adjacent oxide semiconductor layers (280) arranged along the second direction (Y), and the second isolation layer (310) is filled with the fourth Trench(290).
The method of manufacturing a semiconductor structure according to any one of claims 5 to 7, wherein the material of the oxide semiconductor layer (280) includes: indium gallium zinc oxide or zinc tin oxide.
The method for manufacturing a semiconductor structure according to any one of claims 5 to 7, wherein after forming the oxide semiconductor layer (280), it further includes: forming a word line (320) surrounding the The surface of the oxide semiconductor layer (280), and the word line (320) extends along one of the first direction (X) or the second direction (Y);

A bit line (350) is formed, the bit line (350) surrounds the surface of the oxide semiconductor layer (280), the bit line (350) is spaced from the word line (320), and the bit line (350) is formed 350) extends along the other of the first direction (X) or the second direction (Y).
A semiconductor structure including:

base(100);

Active structures located on the surface of the substrate (100) and arranged at intervals along the first direction (X) and the second direction (Y);

The lower electrode structure (200) is electrically connected to the active structure in one-to-one correspondence, the first direction (X) is perpendicular to the surface of the substrate (100), and the second direction (Y) is parallel to the substrate (100) Surface;

A first isolation layer (120) located between the active structures adjacent in the first direction (X) and located in the first direction (X) between adjacent lower electrode structures (200);

The lower electrode structure (200) includes: a first metal conductive layer (170) and a second metal conductive layer (190). The second metal conductive layer (190) includes a first side, and the first side is connected to the first side. The first metal conductive layer (170) is in contact with the second side, the second side is directly opposite to the first side and is in contact with the first isolation layer (120), and the third side is in contact with the first isolation layer (120). Three side surfaces are connected to the first side surface and the second side surface.
The semiconductor structure of claim 10, further comprising:

Capacitive dielectric layer (220), the capacitive dielectric layer (220) covers the surface of the second metal conductive layer (190) and the sidewall of the first metal conductive layer (170);

Upper electrode structure (230), the upper electrode structure (230) covers the surface of the capacitive dielectric layer (220), the lower electrode structure (200), the capacitive dielectric layer (220) and the upper electrode structure (230) constitutes capacitor (240).
The semiconductor structure according to claim 11, wherein the capacitive dielectric layer (220) also covers sidewalls of the first isolation layer (120) to form a shared capacitor along the first direction (X). The capacitance (240) of the dielectric layer (220).
The semiconductor structure according to claim 11 or 12, wherein the projection of the upper electrode structure (230) on the substrate (100) is located at a position of the lower electrode structure (200) within the substrate (100). within the projection.
The semiconductor structure according to any one of claims 10 to 13, wherein the material of the active structure is an oxide semiconductor.
The semiconductor structure of claim 14, further comprising: a word line (320) surrounding a surface of the active structure, and the word line (320) extends along the first extending in one of the directions (X) or said second direction (Y);

Bit lines (350) surrounding the surface of the active structure, the bit lines (350) being spaced from the word lines (320) and along the The first direction (X) or the other of said second direction (Y) extends.