CN114551450A

CN114551450A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN114551450A
Application number: CN202210174057.8A
Authority: CN
Inventors: 邵光速; 吴敏敏
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-02-24
Filing date: 2022-02-24
Publication date: 2022-05-27

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate; the first electrode is positioned on the substrate and surrounds a through hole extending towards the direction far away from the substrate; the second electrode is at least positioned in the through hole; the capacitor dielectric layer is positioned between the first electrode and the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure; the transistor is positioned on the capacitor structure and comprises a first doping area and a second doping area which are arranged at intervals along the direction vertical to the surface of the substrate, the first doping area is electrically connected with the second electrode, the doping type of the first doping area and the doping type of the second doping area are one of N type or P type, and the doping types of the first doping area and the second doping area are the same; and the bit line is positioned on the transistor and is electrically connected with the second doped region. The embodiment of the disclosure is at least beneficial to improving the performance of the semiconductor device and reducing the difficulty of the manufacturing process.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background

With the development of semiconductor technology, the manufacture of semiconductor devices with better performance and higher integration level has become a major direction in the pursuit of semiconductor processing.

However, the manufacturing process of the semiconductor device having a smaller size is complicated, the performance requirement for the processing equipment is extremely high, and the difficulty in achieving the improvement of the processing accuracy by improving the performance of the processing equipment is large.

Therefore, the improvement of the layout and the forming mode of the semiconductor device structure is an effective mode for enabling the semiconductor device to meet the requirements of better performance and smaller size and simultaneously reducing the processing difficulty of the semiconductor device.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof, which are at least beneficial to improving the performance of a semiconductor device and reducing the difficulty of the manufacturing process.

An aspect of an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; the first electrode is positioned on the substrate and surrounds a through hole extending towards the direction far away from the substrate; the second electrode is at least positioned in the through hole; the capacitor dielectric layer is positioned between the first electrode and the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure; the transistor is positioned on the capacitor structure and comprises a first doping area and a second doping area which are arranged at intervals along the direction vertical to the surface of the substrate, the first doping area is electrically connected with the second electrode, the doping type of the first doping area and the doping type of the second doping area are one of N type or P type, and the doping types of the first doping area and the second doping area are the same; and the bit line is positioned on the transistor and is electrically connected with the second doped region.

In some embodiments, further comprising: the capacitor structure is positioned in the insulating layer, and the insulating layer is exposed out of the top surface of the second electrode; the outer side wall of the through hole, which is far away from the second electrode, is in contact with the insulating layer; the through hole is filled with the second electrode and the capacitor dielectric layer together, and the top surface of the second electrode is flush with the top surface of the capacitor dielectric layer.

In some embodiments, the capacitor dielectric layer is further disposed on the top surface of the first electrode and the top surface of the insulating layer, and the top surface of the second electrode is flush with the top surface of the capacitor dielectric layer.

In some embodiments, the second electrode is further located on an outer sidewall of the via and a top surface of the first electrode, and the second electrode includes: the first main body part is positioned in the through hole; the second main body part is positioned on the outer side wall of the through hole, the material of the second main body part is the same as that of the first main body part, and in the direction parallel to the surface of the substrate, the thickness of the first main body part is larger than that of the second main body part; and the electric connection part spans the first main body part and the second main body part and is in contact with the top surface of the first main body part and the top surface of the second main body part.

In some embodiments, the second electrode is an integrally formed structure for the same capacitor structure.

In some embodiments, the first electrode comprises: a side edge portion which is a side wall portion of the through hole; the bottom connecting part is a bottom surface part of the through hole parallel to the substrate; the semiconductor structure further includes: and the electric connection layer is positioned on the substrate and electrically connected with the adjacent bottom connection parts.

In some embodiments, the electrical connection layer and the bottom connection portion are integrally formed, and the capacitor dielectric layer is further located on the surface of the electrical connection layer.

In some embodiments, the side edge portion and the bottom connection portion are integrally formed as a film layer, and the electrical connection layer is further located between the bottom connection portion and the substrate.

In some embodiments, the transistor further comprises: the channel region is positioned between the first doping region and the second doping region, and the materials of the channel region, the first doping region and the second doping region at least comprise one or more of IGZO, IWO or ITO; the gate dielectric layer is arranged around the channel region and is positioned on the surface of the side wall of the channel region; and the gate conducting layer is arranged around the channel region and is positioned on the surface of the side wall of the gate dielectric layer corresponding to the channel region.

Another aspect of the embodiments of the present disclosure also provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a first electrode on a substrate, wherein the first electrode encloses a through hole extending in a direction away from the substrate; forming a second electrode, wherein the second electrode is at least positioned in the through hole; forming a capacitor dielectric layer, wherein the capacitor dielectric layer is positioned between the first electrode and the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure; forming a transistor, wherein the transistor is positioned on the capacitor structure and comprises a first doping area and a second doping area which are arranged at intervals along the direction vertical to the surface of the substrate, the first doping area is electrically connected with the second electrode, the doping type of the first doping area and the doping type of the second doping area are one of N type or P type, and the doping types of the first doping area and the second doping area are the same; and forming a bit line, wherein the bit line is positioned on the transistor and is electrically connected with the second doped region.

In some embodiments, the step of forming the first electrode comprises: forming an insulating film on the substrate, wherein the insulating film is internally provided with a groove penetrating through the thickness of the insulating film; and forming a first electrode, wherein the first electrode is positioned at the bottom and the side wall of the groove.

In some embodiments, the remaining insulating film serves as an insulating layer; the step of forming the capacitor dielectric layer and the second electrode comprises the following steps: forming a capacitor dielectric layer, wherein the capacitor dielectric layer is positioned at the bottom and the side wall of the through hole; and forming a second electrode layer which is positioned on the surface of the capacitance dielectric layer and fills the through hole.

In some embodiments, the step of forming the capacitor dielectric layer and the second electrode comprises: removing the residual insulating film to expose the outer side wall of the through hole; forming a capacitor dielectric layer, wherein the capacitor dielectric layer is positioned at the bottom, the inner side wall and the outer side wall of the through hole; and forming a second electrode, wherein the second electrode is positioned on the surface of the capacitor dielectric layer, and is also positioned in the through hole and on the outer side wall of the through hole.

In some embodiments, further comprising: forming an insulating layer on the substrate; the process steps for forming the insulating layer and the second electrode include: forming a first main body part and a second main body part, wherein the first main body part is positioned in the through hole, the second main body part is positioned on the outer side wall of the through hole, and the material of the second main body part is the same as that of the first main body part; forming an insulating layer on the substrate, wherein the insulating layer is positioned on the side wall of the second main body part; and forming an electric connection part, wherein the electric connection part crosses the first main body part and the second main body part and is in contact with the top surface of the first main body part and the top surface of the second main body part, and the electric connection part, the first main body part and the second main body part jointly form a second electrode.

In some embodiments, before forming the first electrode, further comprising: and forming an electric connection layer on the substrate, wherein the electric connection layer is electrically connected with the first electrode.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the capacitor structure of the semiconductor structure is located below the transistor, and the arrangement mode has the following two advantages: on one hand, after the transistor is formed, the bit line structure can be directly formed on the exposed second doping region, and compared with the traditional embedded bit line, the process for forming the bit line is simpler; on the other hand, the capacitor structure of the arrangement mode overcomes the limitation of a manufacturing line on a subsequent process, so that the multilayer stacking of the capacitor structure and the crystal structure can be realized, the storage capacity is increased, in addition, under the condition of multilayer stacking, the requirement of reducing the size of the single-layer structure is reduced, the size of the single-layer structure can be properly increased, and the process difficulty is reduced. In addition, the capacitor structure is a columnar capacitor, and in a limited space, the relative area of the first electrode and the second electrode is larger, so that the storage capacity is increased.

Drawings

One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, the drawings are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 is a schematic vertical cross-sectional structure diagram of a semiconductor structure according to an embodiment of the disclosure;

FIG. 2 is a cross-sectional view of the capacitor structure of the embodiment shown in FIG. 1;

fig. 3 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure;

fig. 4 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure;

fig. 6 is a schematic vertical cross-sectional structure diagram of a semiconductor structure according to another embodiment of the present disclosure;

fig. 7 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure;

FIG. 8 is a cross-sectional view of the transistor of the embodiment of FIG. 7 in a horizontal direction;

FIG. 9 is a top view of the embodiment of FIG. 7 without the isolation layer;

fig. 10 to 25 are schematic structural diagrams corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

It is known from the background art that the method for improving the processing precision by improving the performance of the processing equipment is difficult to realize, and the layout and the forming mode of the semiconductor device structure are improved, so that the method is an effective method for reducing the size integration while ensuring that the performance of the semiconductor device is better.

In order to solve the above problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which enable a processing process of a bit line of the semiconductor structure to be simpler by adjusting a positional relationship between a capacitor structure and a transistor, and are beneficial to implementing 3D (3D) stacking of a memory, thereby increasing an integration density of the semiconductor structure. In addition, the capacitance capacity is increased by increasing the relative area of the first electrode and the second electrode, and the storage capacity is increased.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the embodiments of the disclosure. However, the claimed embodiments of the present disclosure may be practiced without these specific details or with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic diagram of a vertical cross-sectional structure of a semiconductor structure according to an embodiment of the present disclosure; FIG. 2 is a cross-sectional view of the capacitor structure of the embodiment shown in FIG. 1; fig. 3 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure; fig. 4 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure; fig. 5 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure; fig. 6 is a schematic vertical cross-sectional structure diagram of a semiconductor structure according to another embodiment of the present disclosure; fig. 7 is a schematic diagram illustrating a vertical cross-sectional structure of a semiconductor structure according to another embodiment of the present disclosure; FIG. 8 is a cross-sectional view of the transistor of the embodiment of FIG. 7 in a horizontal direction; fig. 9 is a top view of the embodiment of fig. 7 without the spacer layer.

Referring to fig. 1 to 9, the semiconductor structure includes: a substrate 100; a first electrode 102, the first electrode 102 being located on the substrate 100, the first electrode 102 enclosing a through hole extending away from the substrate 100; a second electrode 104, the second electrode 104 being at least located within the via; a capacitor dielectric layer 103, wherein the capacitor dielectric layer 103 is located between the first electrode 102 and the second electrode 104, the capacitor dielectric layer 103 and the first electrode 102 form a capacitor structure 110; the transistor 111 is located on the capacitor structure 110, the transistor 111 includes a first doped region I and a second doped region III arranged at intervals along a direction perpendicular to the surface of the substrate 100, the first doped region I is electrically connected to the second electrode 104, the doping types of the first doped region I and the second doped region III are either N-type or P-type, and the doping types of the first doped region I and the second doped region III are the same; and a bit line 112, wherein the bit line 112 is located on the transistor 111 and electrically connected to the second doped region III.

Since the semiconductor structure includes a vertical Gate-All-Around transistor 111, and the temperature of the manufacturing process of the transistor 111 is compatible with the conductive material in the capacitor structure 110 and the conductive material of the bit line 112, so that the transistor 111 can be stacked on the capacitor structure 110 or the bit line 112, a 3D stacked memory device can be formed, which is beneficial to improving the integration density of the semiconductor structure. In addition, on the basis of 3D stacking, the size of a single-layer memory device is increased properly, and manufacturing difficulty is reduced. The bit line 112 is located on the transistor 111, and thus, the formation of the bit line 112 superimposed on the transistor 111 is simpler in this embodiment than the formation of the buried bit line 112. Moreover, since the second electrode 104 is located in the through hole surrounded by the first electrode 102, compared with a planar capacitor, the relative area between the outer sidewall surface of the second electrode 104 facing the inner wall of the through hole and the inner sidewall of the through hole of the first electrode 102 is larger, and the capacitance is larger.

Referring to fig. 1, in the present embodiment, since the first electrode 102 on the substrate 100 is in contact with the substrate 100, in order to improve the potential stability of the first electrode 102, the substrate 100 may be an insulating material, such as silicon dioxide, silicon oxynitride, etc., and a conductive layer (not shown) may be disposed in the substrate 100. The conductive layer is electrically connected to the first electrode 102 for leading out the first electrode 102, and the plurality of first electrodes 102 can be electrically connected to the same conductive layer, which is beneficial to saving the wiring space and reducing the size of the semiconductor structure.

In some embodiments, the substrate 100 may also be a stacked structure of a first substrate layer 114 and a second substrate layer 115, taking the substrate 100 in contact with the first electrode 102 as the second substrate layer 115 as an example, and the second substrate layer 115 may be an insulating material, for example, silicon oxide. And the second base layer 115 may have therein a conductive layer (not shown) for leading out the first electrode 102. The first substrate layer 114 is a material that can be directly used in the fabrication process to produce semiconductor devices, for example, the first substrate layer 114 may be Silicon (SOI), silicon, germanium, silicon carbide, gallium arsenide, sapphire, or the like on an insulating substrate.

Referring to fig. 1 and fig. 2, in some embodiments, the through hole surrounded by the first electrode 102 of the capacitor structure 110 on the substrate 100 is a cylindrical through hole, that is, the capacitor structure 110 is a cylindrical capacitor, and such a capacitor structure 110 has smooth side surfaces, which is beneficial to avoiding the tip discharge phenomenon. The capacitor dielectric layer 103 is located on the inner side surface and the bottom of the through hole of the first electrode 102, i.e. the capacitor dielectric layer 103 also encloses the through hole extending away from the substrate 100. The second electrode 104 fills the through hole surrounded by the capacitor dielectric layer 103, and the second electrode 104 is close to the lower surface of the substrate 100 and contacts with the capacitor dielectric layer 103. In other embodiments, the through hole surrounded by the first electrode 102 may be a square through hole or a columnar hole with other shapes, and also has a larger opposite area of the plate compared to a planar capacitor, so as to increase the capacitance of the capacitor.

In some embodiments, the first electrode 102 and the second electrode 104 are conductive materials, such as titanium nitride. In other embodiments, the material of the first electrode 102 and the second electrode 104 may also be at least one of conductive materials such as platinum nickel, titanium, tantalum, cobalt, copper, tungsten, tantalum nitride, and the like. The capacitor dielectric layer 103 is an insulating dielectric material, for example, the material of the capacitor dielectric layer 103 is at least one of high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

In addition, the semiconductor structure includes a plurality of capacitor structures 110 arranged at intervals along a direction parallel to the top surface of the substrate 100, and different capacitor structures 110 are separated from each other.

With continued reference to fig. 1, in some embodiments, the semiconductor structure may further include: the insulating layer 101, the capacitor structure 110 is located in the insulating layer 101, and the insulating layer 101 exposes the top surface of the second electrode 104; the outer side wall of the through hole, which is far away from the second electrode 104, is in contact with the insulating layer 101; the through hole is filled by the second electrode 104 and the capacitance medium layer 103 together, and the top surface of the second electrode 104 is flush with the top surface of the capacitance medium layer 103.

The insulating layer 101 is disposed between the capacitor structures 110, and is used for supporting the capacitor structures 110 and isolating the second electrodes 102 of the adjacent capacitor structures 110. The material of the insulating layer 101 includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. In some embodiments, the insulating layer 101 may also be a stacked film structure, as long as the insulating layer 101 is ensured to be capable of serving as a support and isolation purpose, and the structure of the insulating layer 101 is not particularly limited by the embodiments of the present disclosure.

In some embodiments, the capacitor dielectric layer 103 may also be located on the top surface of the first electrode 102, so that only the second electrode 104 is exposed on the top surface of the insulating layer 101, which is beneficial to avoiding the situation that the first electrode 102 is electrically connected to the first doped region I of the transistor 111 due to a subsequent process error. In addition, the top surface of the second electrode 104 is flush with the top surface of the capacitor dielectric layer 103, so that the relative area between the first electrode 102 and the second electrode 104 is ensured to be larger, and the capacitance capacity is increased. It is understood that in other embodiments, the top surface of the first electrode 102 may be higher than the top surface of the capacitor dielectric layer 103.

Referring to fig. 3, in some embodiments, the capacitor dielectric layer 103 is also located on the top surface of the first electrode 102 and the top surface of the insulating layer 101, and the top surface of the second electrode 104 is flush with the top surface of the capacitor dielectric layer 103.

Specifically, the capacitor dielectric layer 103 on the top surface of the first electrode 102 and the top surface of the insulating layer 101 may serve as a planarization stop layer for the second electrode 104, and the second electrode 104 is only located in the through hole of the capacitor dielectric layer 103 and is flush with the top surface of the capacitor dielectric layer 103, which is not only beneficial to simplifying the processing process, but also ensures that the capacitor structure 110 has a large capacitance.

Referring to fig. 4, in some embodiments, the second electrode 104 is also located on the outer sidewall of the via and the top surface of the first electrode 102, and the second electrode 104 includes: a first body portion 120, the first body portion 120 being located within the through hole; the second body part 121, the second body part 121 is located on the outer side wall of the through hole, the material of the second body part 121 is the same as that of the first body part 120, and in the direction parallel to the surface of the substrate 100, the thickness of the first body part 120 is greater than that of the second body part 121; and the electrical connection part 122 spans the first main body part 120 and the second main body part 121, and the electrical connection part 122 is in contact with the top surface of the first main body part 120 and the top surface of the second main body part 121. The electrical connection portion 122 is used to electrically connect the first body portion 120 of the inner sidewall of the through hole and the second body portion 121 of the outer sidewall of the through hole, so that the second electrode 104 is shared among the single capacitors. In addition, the outer side wall and the inner side wall of the through hole are both provided with the second electrodes 104 which are opposite to each other, compared with a planar capacitor, the capacitance capacity can be greatly increased by arranging the first main body part 120 and the second main body part 121, and the performance of the semiconductor structure is effectively improved.

Specifically, the outer sidewall of the second electrode 104 is also provided with an insulating layer 101, which serves to isolate the second electrode 104 from the supporting capacitor structure 110, so that the capacitors are independent from each other, and each capacitor is correspondingly connected to one transistor 111. The first and

second body portions

120 and 121 are formed simultaneously, that is, the first and

second body portions

120 and 121 are made of the same conductive material. Also, the thickness of the first body portion 120 refers to the maximum thickness of the first body portion 120 in a direction parallel to the surface of the substrate 100. In addition, the capacitor dielectric layer 103 is also located on the surface of the substrate 100, and the capacitor dielectric layer 103 may be selectively removed or retained, for example, by retaining the capacitor dielectric layer 103, the process duration of the whole semiconductor manufacturing process may be reduced by retaining the capacitor dielectric layer 103, and the manufacturing efficiency of the semiconductor structure may be improved. It is understood that in other embodiments, the capacitance medium layer 103 may be only located on the surface of the first electrode 102, and the first electrode 102 and the second electrode 104 may be isolated from each other.

With continued reference to fig. 4, in some embodiments, the second electrode 104 is an integrally formed structure for the same capacitor structure 110. That is, the electrical connection portion 122 is formed of the same material as the first and second

main body portions

120 and 121, and the integral molding structure simplifies the processing of the second electrode 104. It is understood that in other embodiments, the materials of the electrical connection portion 122 and the first and

second body portions

120 and 121 may be different.

Referring to fig. 5 and 6, in some embodiments, the first electrode 102 may include: a side part 123, the side part 123 being a side wall part of the through-hole; a bottom connection part 124, the bottom connection part 124 being a through hole parallel to the bottom surface portion of the substrate 100; the semiconductor structure may further include: and the electrical connection layer 108, wherein the electrical connection layer 108 is positioned on the substrate 100 and electrically connects the adjacent bottom connection parts 124.

It should be noted that, because the substrate 100 has the electrical connection layer 108, the substrate 100 may not include a conductive layer therein. The electrical connection layer 108 electrically connects the first electrode 102 of each capacitive structure 110 with the electrical connection layer 108. The semiconductor structure with the electric connection layer 108 not only ensures mutual independence of each capacitor structure 110, but also enables the first electrode 102 to be electrically connected to an external circuit through the electric connection layer 108, so that the capacitor structures 110 of the semiconductor structure are provided with the common first electrode 102, the process is simplified, and the space waste caused by increasing the conductive layer is favorably improved.

In some embodiments, the material of the electrical connection layer 108 is the same as the material of the first electrode 102 layer, which is beneficial to avoiding interface state defects and improving the electrical conduction effect. It is understood that in other embodiments, the material of the electrical connection layer 108 may be different from the material of the first electrode 102, so long as electrical connection with the first electrode 102 is ensured.

Referring to fig. 5 and 6, in some embodiments, the electrical connection layer 108 and the bottom connection portion 124 may be an integrally formed film layer, and the capacitor dielectric layer 103 is further located on the surface of the electrical connection layer 108.

Specifically, the electrical connection layer 108 at the bottom of the through hole directly serves as the bottom connection portion 124 of the first electrode 102, which is beneficial to simplifying the processing process of the first electrode 102. Moreover, the capacitor dielectric layer 103 on the surface of the electrical connection layer 108 prevents the second electrode 104 from contacting the electrical connection layer 108.

Referring to fig. 7, in some embodiments, the side portions 123 and the bottom connection portion 124 may be an integrally formed film, and the electrical connection layer 108 is further located between the bottom connection portion 124 and the substrate 100.

Specifically, the electrical connection layer 108 and the bottom connection portion 124 have different structures, and a part of the surface of the electrical connection layer 108 away from the substrate 100 is in contact with the bottom connection portion 124 of the first electrode 102, so that the first electrode 102 is directly led out through the electrical connection layer 108, and the first electrode 103 is prevented from being led out by adding other electrical connection structures, thereby avoiding the waste of space caused by adding other electrical connection structures.

Referring to fig. 7 and 8, the top of the second electrode 104 of each capacitor structure 110 of the semiconductor structure is in contact with the first doped region I of one transistor 111. The first doped region I constitutes one of a source or a drain of the transistor 111, and the second doped region III constitutes the other of the source or the drain of the transistor 111. The first doped region I and the second doped region III may be N-type doped regions or P-type doped regions, ions of the N-type doped regions include arsenic ions, phosphorus ions, antimony ions, and the like, and ions of the P-type doped regions include boron ions, aluminum ions, gallium ions, and the like.

In some embodiments, the transistor 111 may further include: the channel region II is located between the first doped region I and the second doped region III, and the materials of the channel region II, the first doped region I and the second doped region III at least comprise one or more of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide).

The channel region II, the first doping region I, and the second doping region III of the transistor 111 form a semiconductor channel 105 of the transistor 111, in some embodiments, the material of the semiconductor channel 105 is IGZO, and the carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial to improving the carrier mobility of the channel region II, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure. In addition, the IGZO semiconductor channel 105 is formed at a lower temperature, so that the IGZO semiconductor channel can be conveniently formed on a metal structure, and a 3D stacked memory structure can be formed, thereby increasing the integration density of the semiconductor structure and integrating more semiconductor structures in a limited space.

In some embodiments, the first doped region I, the channel region II, and the second doped region III forming the semiconductor channel 105 are an integrated structure, which is beneficial to improve the interface state defect between the first doped region I and the channel region II, and improve the interface state defect between the channel region II and the second doped region III, so as to improve the performance of the semiconductor structure. It is understood that in other embodiments, the semiconductor channel 105 may also have a three-layer structure, and each layer structure is used as the first doped region I, the channel region II, and the second doped region III.

In addition, referring to fig. 8, in some embodiments, the semiconductor channel 105 is a cylindrical structure, so that the side surface of the semiconductor channel 105 is a smooth transition surface, which is beneficial to avoiding the phenomenon of point discharge or current leakage of the semiconductor channel 105, and further improving the electrical performance of the semiconductor structure. It should be noted that, in other embodiments, the semiconductor channel 105 may also be a square pillar structure or other irregular structure. It is understood that when the semiconductor channel 105 is a square column structure, the corner formed by the adjacent surfaces of the sidewalls of the square column structure can be a rounded corner, which can also avoid the problem of the point discharge, and the square column structure can be a square column structure or a rectangular prism structure.

With continued reference to fig. 7 and 8, the transistor 111 structure may further include: the gate dielectric layer 106 is arranged around the channel region II, and the gate dielectric layer 106 is positioned on the side wall surface of the channel region II; and the gate conducting layer 107 is arranged around the channel region II, and is positioned on the side wall surface of the gate dielectric layer 106 corresponding to the channel region II.

In some embodiments, a gate dielectric layer 106 is located on the sidewall surface of the semiconductor channel 105 of the channel region II and the sidewall surface of the semiconductor channel 105 of the second doped region III for isolating the gate conductive layer 107 from the semiconductor channel 105. In addition, the gate dielectric layer 106 on the sidewall surface of the semiconductor channel 105 in the second doped region III can protect the surface of the second doped region III, so as to avoid process damage to the surface of the second doped region III during the process of forming the gate conductive layer 107, thereby further improving the performance of the semiconductor structure. It is understood that in other embodiments, the gate dielectric layer 106 may be only located on the sidewall surface of the semiconductor channel 105 in the channel region II.

The material of the gate dielectric layer 106 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, or other high-k dielectric material. The material of the gate conductive layer 107 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum.

With continued reference to fig. 7, in some embodiments, the transistors 111 may further include interlayer dielectric layers 113, where the interlayer dielectric layers 113 are located between the transistors 111, exposing the top surfaces of the second doped regions III of the transistors 111, and functioning as isolation and support for adjacent transistors 111. And the interlayer dielectric layer 113 includes a first interlayer dielectric 125, a second interlayer dielectric 126, and a third interlayer dielectric 127. The first interlayer dielectric 125 is located on the sidewall surface of the semiconductor channel 105 where the first doped region I is located, the bottom surface of the gate dielectric layer 106 facing the substrate 100, and the bottom surface of the gate conductive layer 107 facing the substrate 100. The second interlayer dielectric 126 is located on the surface of the sidewall of the gate dielectric layer 106 on the sidewall of the second doped region III and the top surface of the gate conductive layer 107 in the direction away from the substrate 100. The third interlayer dielectric 127 is located on the sidewall surface of the gate conductive layer 107, between different sidewalls of the first interlayer dielectric 125, and between different sidewalls of the second interlayer dielectric 126. The first interlayer dielectric 125, the second interlayer dielectric 126 and the third interlayer dielectric 127 may be separately formed structures, and the first interlayer dielectric 125, the second interlayer dielectric 126 and the third interlayer dielectric 127 may be the same insulating material, such as at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon oxycarbonitride, and the same material is favorable for forming a good contact interface and improving the reliability of the semiconductor structure. It is understood that in other embodiments, the first interlayer dielectric 125, the second interlayer dielectric 126, and the third interlayer dielectric 127 may be different insulating materials.

Referring to fig. 7, in some embodiments, the semiconductor structure may further include a bit line 112 and an isolation layer 109, the bit line 112 is located on a portion of the surface of the interlayer dielectric layer 113 and contacts the second doped region III of the transistor 111 and a portion of the top surface of the gate dielectric layer 106 away from the substrate 100, and the isolation layer 109 covers the surface of the bit line 112 to isolate different bit lines 112 and support other stacked semiconductor structures on the bit line 112. The material of the isolation layer 109 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. In addition, the interlayer dielectric layer 113 and the isolation layer 109 are made of the same material, which is beneficial to improving the interface state defect between the interlayer dielectric layer 113 and the isolation layer 109 and the performance of the semiconductor structure, and is beneficial to reducing the processing steps of the semiconductor structure and reducing the manufacturing cost and complexity of the semiconductor structure. It is understood that in other implementations, the material of the interlevel dielectric layer 113 may be different from the material of the isolation layer 109.

Specifically, a portion of the surface of the interlayer dielectric layer 113 may have a plurality of bit lines 112 arranged at intervals, and each bit line 112 may be electrically connected to at least one second doping region III. For example, referring to fig. 9, each bit line 112 contacts 2 second doped regions III. The number of the second doping regions III electrically connected to each bit line 112 may be set according to the actual electrical requirements.

In the semiconductor structure provided by the above embodiment, on the basis that the capacitor structure 110 is a columnar structure, the second electrodes 104 are disposed in the through hole surrounded by the first electrode 102 and on the outer side of the through hole, so that the area of the opposite plates of the capacitor structure 110 is greatly increased, and the capacitance is increased. The electrical connection layer 108 enables the semiconductor structure to have the mutually independent capacitor structures 110, and also enables the first electrode 102 to be electrically connected to an external circuit through the electrical connection layer 108, so that the semiconductor structure has the shared first electrode 102, which is beneficial to simplifying the process and avoiding the waste of space. By adjusting the position relationship between the transistor 111 and the capacitor structure 110, the semiconductor structure meets the condition of multilayer stacking, and the integration density of the semiconductor structure is increased under the same volume. In addition, the arrangement of the transistor 111 on the capacitor structure 110 not only simplifies the formation process of the bit line 112, but also properly increases the size of the single-layer semiconductor structure, which is beneficial to reducing the complexity of manufacturing.

Correspondingly, the embodiment of the present disclosure also provides a manufacturing method of a semiconductor structure, which is used for forming the semiconductor structure. It should be noted that, for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, which will not be repeated herein.

Referring to fig. 10, a method of fabricating a semiconductor structure includes: a substrate 100 is provided.

Wherein, an insulating material is formed on the surface of the substrate 100 or the substrate 100 itself is an insulating material, so that the influence of unstable electrical signals on the semiconductor structure in contact with the substrate 100 to affect the electrical performance of the semiconductor structure can be avoided.

Referring to fig. 11, in some embodiments, an electrical connection layer 108 may be formed on the substrate 100. The electrical connection layer 108 is a conductive film layer on the top surface of the substrate 100 and is electrically connected to the first electrode 102 formed subsequently. In addition, the electrical connection layer 108 can be formed by physical vapor deposition, evaporation, sputtering, and the like. For the materials of the substrate 100 and the electrical connection layer 108, reference may be made to the corresponding descriptions of the foregoing embodiments, and further description is omitted here.

Referring to fig. 12 to 14, a first electrode 102 is formed on a substrate 100, and the first electrode 102 encloses a through hole extending in a direction away from the substrate 100.

Specifically, referring to fig. 14, the first electrodes 102 may be formed independently on the electrical connection layer 108 of the substrate 100, and the bottom surface of the first electrode 102 facing the substrate 100 is in contact with the electrical connection layer 108. Therefore, the first electrode 102 is directly led out through the electrical connection layer 108 without adding other lead layers, which saves space and is beneficial to reducing the size of the semiconductor structure. In addition, the shape of the through hole can refer to the corresponding description of the foregoing embodiments, and is not repeated herein.

With continued reference to fig. 12-14, in some embodiments, the step of forming the first electrode 102 may further include: forming an insulating film on the substrate 100, and having a groove penetrating the thickness of the insulating film in the insulating film; a first electrode 102 is formed, the first electrode 102 being located at the bottom and sidewalls of the recess. The groove in the insulating film defines the position of the first electrode 102, and under the assistance and support of the insulating film, the first electrode 102 of the columnar capacitor with larger capacitance capacity is obtained by forming a conductive material on the side wall and the bottom of the groove. Also, the material of the insulating film may be silicon oxide.

Specifically, an insulating film may be first formed on the electrical connection layer 108 of the substrate 100 by deposition, and the thickness of the insulating film may be determined according to the height of the desired pillar-shaped capacitance. Then, a groove is formed on the insulating film by photolithography, etching, and the like, and the bottom of the groove exposes a portion of the top surface of the electrical connection layer 108. Also, the groove formed here may be a circular hole-shaped groove extending toward the substrate 100. It is understood that in other embodiments, the grooves may be square hole grooves or other shaped grooves. Then, a layer of conductive material is formed on the surface of the electrical connection layer 108 exposed at the bottom of the groove, the side wall of the groove, and the top surface of the insulating film as the first electrode 102, and the conductive material on the top surface of the insulating film is removed by maskless etching, thereby forming the first electrodes 102 independent of each other. In addition, the first electrode 102 may be formed by an atomic layer deposition process.

In some embodiments, the first electrode 102 may also be obtained by covering the via hole with photoresist and removing the first electrode 102 on the top surface of the insulating film. Note that, at this time, the first electrode 102 at the bottom of the via is not consumed by etching under the coverage of the photoresist, and thus remains on the electrical connection layer 108 in the via.

Referring to fig. 15 to 20, after the first electrode 102 is formed, a second electrode 104 and a capacitor dielectric layer 103 are further formed. The second electrode 104 is at least located in the through hole, the capacitor dielectric layer 103 is located between the first electrode 102 and the second electrode 104, the capacitor dielectric layer 103 and the first electrode 102 form a capacitor structure 110. Also, the second electrode 104 may be formed by an atomic layer deposition process.

The method of forming the capacitor dielectric layer 103 and the second electrode 104 is described in detail by the following embodiments.

Referring to fig. 15 to 16, in some embodiments, the remaining insulating film may be used as the insulating layer 101, and thereafter, the capacitor dielectric layer 103 is formed, the capacitor dielectric layer 103 being located at the bottom and the sidewall of the via hole; and forming a second electrode 104 layer, wherein the second electrode 104 layer is positioned on the surface of the capacitance medium layer 103 and fills the through hole. The remaining insulating film is left as the insulating layer 101, and can function as a support when forming the second electrode 104 opposing the inner sidewall of the through-hole.

Specifically, a capacitor dielectric layer 103 is formed on the top surface of the insulating layer 101 away from the substrate 100, the sidewall, the top surface and the bottom of the via hole formed by the first electrode 102. Then, a second electrode 104 is formed on the capacitor dielectric layer 103, and the second electrode 104 fills the via hole formed in the capacitor dielectric layer 103. And removing the second electrode 104 on the capacitor dielectric layer 103 on the top surfaces of the insulating layer 101 and the first electrode 102 by using a planarization process and taking the capacitor dielectric layer 103 as a planarization stop layer to obtain the second electrode 104 which is flush with the top surface of the capacitor dielectric layer 103. Therefore, the process flow can be simplified, and the manufacturing complexity can be reduced. In other embodiments, the second electrode 104 on the capacitor dielectric layer 103 on the top surface of the insulating layer 101 and the top surface of the first electrode 102 may be removed by a mask etching method, i.e., a photoresist is used to cover the top surface of the second electrode 104 in the via hole, and then the remaining second electrode 104 is removed.

Referring to fig. 17 and 18, in some embodiments, the step of forming the capacitor dielectric layer 103 and the second electrode 104 may further include: removing the residual insulating film to expose the outer side wall of the through hole; forming a capacitor dielectric layer 103, wherein the capacitor dielectric layer 103 is positioned at the bottom, the inner side wall and the outer side wall of the through hole; and forming a second electrode 104, wherein the second electrode 104 is positioned on the surface of the capacitance medium layer 103 and is also positioned in the through hole and on the outer side wall of the through hole. Thus, the second electrode 104 can be formed on both the inner side wall and the outer side wall of the through hole of the first electrode 102, and the relative area of the plates is further increased, thereby increasing the capacitance.

Specifically, the insulating films on the electrical connection layer 108 of the substrate 100 and on the outer side wall of the via hole are removed, and the capacitance dielectric layer 103 is formed on the electrical connection layer 108 and on the first electrode 102 by a deposition functional process, thereby forming the second electrode 104 on the capacitance dielectric layer 103. The second electrode 104 is formed by an atomic layer deposition process.

Referring to fig. 19 to 20, in some embodiments, the step of forming the second electrode 104 may further include: forming an insulating layer 101, wherein the insulating layer 101 is positioned on the substrate 100; the process steps for forming the insulating layer 101 and the second electrode 104 include: forming a first main body part 120 and a second main body part 121, wherein the first main body part 120 is positioned in the through hole, the second main body part 121 is positioned on the outer side wall of the through hole, and the material of the second main body part 121 is the same as that of the first main body part 120; forming an insulating layer 101 on the substrate 100, wherein the insulating layer 101 is located on a sidewall of the second body portion 121; an electrical connection portion 122 is formed, the electrical connection portion 122 crosses over the first body portion 120 and the second body portion 121, and contacts with the top surface of the first body portion 120 and the top surface of the second body portion 121, and the electrical connection portion 122, the first body portion 120 and the second body portion 121 together form the second electrode 104.

Specifically, after the second electrode 104 on the capacitor dielectric layer 103 is formed, the second electrode 104 on the top of the through hole of the capacitor dielectric layer 103 and on the surface of the capacitor dielectric layer 103 on the electrical connection layer 108 is removed by a maskless etching method, so as to obtain a first main body part 120 and a second main body part 121 of the second electrode 104. An insulating layer 101 is formed on the outer sidewall of the second body portion 121 to insulate and isolate the second electrodes 104, which are independent of each other, and to support the subsequent semiconductor structure. The insulating layer 101 exposes the top surface of the first body portion 120, the top surface of the second body portion 121, and the top surface of the capacitor dielectric layer 103 away from the substrate 100. Forming an electrical connection part 122 material on the top surface of the insulating layer 101 away from the substrate 100, the top surface of the first main body part 120, the top surface of the second main body part 121 and the top surface of the capacitance medium layer 103 away from the substrate 100, and removing the electrical connection part 122 on the top surface of the insulating layer 101 away from the substrate 100, so that the first main body part 120 and the second main body part 121 of the second electrode 104 are electrically connected, and the mutually independent second electrodes 104 are formed.

In some embodiments, electrical connections 122 are formed by: a layer, such as a conductive material and a mask layer, is formed on the top surface of the insulating layer 101 away from the substrate 100, the top surface of the first body portion 120, the top surface of the second body portion 121, and the top surface of the capacitor dielectric layer 103 away from the substrate 100, and a plurality of first mask patterns are formed in one direction and a plurality of second mask patterns are formed in another direction by an SADP (Self-aligned Double imaging) process. Selectively etching the crossed area of the first mask pattern and the second mask pattern, removing the mask layer and the conductive material under the mask layer until the insulating layer 101 is exposed, removing the residual mask layer, and reserving the residual material of the electric connection part 122 to form the electric connection part 122. The embodiment of the disclosure can precisely control the position and shape of the electrical connection portion 122 to form the electrical connection portion 122 which is independent of each other, and further realize that the first main body portion 120 and the second main body portion 121 are connected through the electrical connection portion 122 to form the second electrode 104 which is independent of each other and is of an integral structure. In other embodiments, the electrical connection portion 122 may be formed by: the electrical connection 122 is formed using a SAQP (Self-aligned Quadruple Patterning) process.

In some embodiments, the second electrode 104 on the outer side wall, the inner side wall, the bottom and the top of the through hole surrounded by the capacitor dielectric layer 103 is covered by photoresist, and the second electrode 104 on the surface of the capacitor dielectric layer 103 on the electrical connection layer 108 outside the through hole is etched away, so that the second electrode 104 including the first body portion 120, the second body portion 121 and the electrical connection portion 122, which are independent of each other, is directly obtained. After the photoresist is removed, the insulating layer 101 is formed, and a planarization process is used to expose the insulating layer 101 to the top surface of the second electrode 104, so that the first doped region I of the transistor 111 formed subsequently is in contact with the second electrode 104.

Referring to fig. 21 to 23, a transistor 111 is formed, the transistor 111 is located on the capacitor structure 110, and the transistor 111 includes a first doped region I and a second doped region III arranged at intervals along a direction perpendicular to the surface of the substrate 100, the first doped region I is electrically connected to the second electrode 104, the doping types of the first doped region I and the second doped region III are either N-type or P-type, and the doping types of the first doped region I and the second doped region III are the same. Note that forming the transistor 111 may further include: forming a channel region II, wherein the channel region II is positioned between the first doping region I and the second doping region III, and the channel region II, the first doping region I and the second doping region III form a semiconductor channel 105 of the transistor 111; forming a gate dielectric layer 106, wherein the gate dielectric layer 106 is arranged around the channel region II and is positioned on the side wall surface of the channel region II; and forming a gate conductive layer 107, wherein the gate conductive layer 107 is arranged around the channel region II and is positioned on the sidewall surface of the gate dielectric layer 106 corresponding to the channel region II.

Before forming the transistor 111, a first interlayer dielectric 125 may be formed, and referring to fig. 21, the first interlayer dielectric 125 is formed on a portion of the surface of the second electrode 104 and the surface of the insulating layer 101, a groove extending toward the top surface of the second electrode 104 is formed in the first interlayer dielectric 125, and a bottom of the groove exposes a portion of the top surface of the second electrode 104. Wherein, the groove can be a round hole-shaped groove. Referring to fig. 22, a semiconductor via 105 is formed in the recess, and then a portion of the thickness of the first interlayer dielectric 125 is removed to form a gate dielectric layer 106, a gate conductive layer 107, and a second interlayer dielectric 126. Since the gate conductive layers 107 of the different transistors 111 are all in a state of being connected to each other at this time, referring to fig. 23, the gate conductive layers 107 are broken by selective etching, thereby forming the gate conductive layers 107 which are independent from each other or have a prescribed connection pattern. And a third interlayer dielectric 127 is formed between the gate conductive layers 107 independent of each other. The first interlayer dielectric 125, the second interlayer dielectric 126 and the third interlayer dielectric 127 form an interlayer dielectric layer 113, and the interlayer dielectric layer 113 is beneficial to enabling the transistor to achieve a better insulation and isolation effect and providing support for a subsequent semiconductor structure.

Referring to fig. 24, a bit line 112 is formed, and the bit line 112 is located on the transistor 111 and electrically connected to the second doped region III.

Specifically, bit lines 112 are formed on the surface of the interlayer dielectric layer 113, the second doping region III of the transistor 111, and the top surface of the gate dielectric layer 106 away from the substrate 100, and patterned to form the bit lines 112 independent from each other or having a designated connection mode. In addition, the isolation layer 109 is formed on the surface of the bit line 112, so that the bit lines 112 independent from each other have a better isolation effect and provide support for the stacked semiconductor structures formed on the bit lines 112.

Referring to fig. 25, the capacitor structure 110, the transistor 111 and the bit line 112 adjacent to the substrate 100 form a memory cell array 130, at least one memory cell array 130 is formed on the isolation layer 109, and the plurality of memory cell arrays 130 extend away from the top surface of the substrate 100.

The method for fabricating the semiconductor structure according to the above embodiment can form the pillar-shaped capacitor structure 110 sharing the first electrode 102, the transistor 111 structure arranged on the capacitor structure 110, and the non-embedded bit line 112. Sharing the first electrode 102 can save space, and the transistor 111 structure disposed on the capacitor structure 110 can realize multi-layer stacking of the memory cell array, thereby facilitating further size reduction while ensuring better performance of the semiconductor structure. In addition, the non-embedded bit lines 112 reduce the manufacturing complexity, and the pillar capacitor structures 110 have a larger relative electrode area, thereby improving the performance of the semiconductor structure.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the disclosure, and it is intended that the scope of the disclosure be limited only by the claims appended hereto.

Claims

1. A semiconductor structure, comprising:

a substrate;

the first electrode is positioned on the substrate and surrounds a through hole extending in the direction far away from the substrate;

a second electrode at least within the via;

the capacitor dielectric layer is positioned between the first electrode and the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure;

the transistor is positioned on the capacitor structure and comprises a first doping area and a second doping area which are arranged at intervals along the direction vertical to the surface of the substrate, the first doping area is electrically connected with the second electrode, the doping type of the first doping area and the doping type of the second doping area are one of N type or P type, and the doping types of the first doping area and the second doping area are the same;

a bit line on the transistor and electrically connected to the second doped region.

2. The semiconductor structure of claim 1, further comprising: the capacitor structure is positioned in the insulating layer, and the insulating layer exposes out of the top surface of the second electrode; the outer side wall of the through hole, which is far away from the second electrode, is in contact with the insulating layer; the through hole is filled by the second electrode and the capacitor dielectric layer together, and the top surface of the second electrode is flush with the top surface of the capacitor dielectric layer.

3. The semiconductor structure of claim 2, wherein said capacitor dielectric layer is further on top of said first electrode and on top of said insulating layer, and said second electrode top surface is flush with said capacitor dielectric layer top surface.

4. The semiconductor structure of claim 1, wherein the second electrode is further located on an outer sidewall of the via and a top surface of the first electrode, and the second electrode comprises:

a first body portion located within the through-hole;

the second main body part is positioned on the outer side wall of the through hole, the material of the second main body part is the same as that of the first main body part, and in the direction parallel to the base surface, the thickness of the first main body part is larger than that of the second main body part;

an electrical connection portion that spans the first and second body portions and contacts the first and second body portion top surfaces.

5. The semiconductor structure of claim 4, wherein the second electrode is a unitary structure for the same capacitor structure.

6. The semiconductor structure of claim 1, wherein the first electrode comprises:

a side edge portion that is a side wall portion of the through-hole;

the bottom connecting part is a bottom surface part of the through hole parallel to the substrate;

the semiconductor structure further includes: and the electric connection layer is positioned on the substrate and is electrically connected with the adjacent bottom connection part.

7. The semiconductor structure of claim 6, wherein the electrical connection layer and the bottom connection portion are integrally formed, and the capacitor dielectric layer is further located on a surface of the electrical connection layer.

8. The semiconductor structure of claim 6, wherein the side edge portion and the bottom connection portion are integrally formed films, and the electrical connection layer is further located between the bottom connection portion and the substrate.

9. The semiconductor structure of claim 1, wherein the transistor further comprises:

the channel region is positioned between the first doped region and the second doped region, and the materials of the channel region, the first doped region and the second doped region at least comprise one or more of IGZO, IWO or ITO;

the gate dielectric layer is arranged around the channel region and is positioned on the surface of the side wall of the channel region;

and the grid conducting layer is arranged around the channel region and is positioned on the surface of the side wall of the grid dielectric layer corresponding to the channel region.

10. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

forming a first electrode on the substrate, wherein the first electrode encloses a through hole extending in a direction away from the substrate;

forming a second electrode, the second electrode being at least located within the via;

forming a capacitor dielectric layer, wherein the capacitor dielectric layer is positioned between the first electrode and the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure;

forming a transistor, wherein the transistor is positioned on the capacitor structure and comprises a first doped region and a second doped region which are arranged at intervals along a direction vertical to the surface of the substrate, the first doped region is electrically connected with the second electrode, the doping type of the first doped region and the doping type of the second doped region are one of N type and P type, and the doping types of the first doped region and the second doped region are the same;

forming a bit line on the transistor and electrically connected to the second doped region.

11. The method of fabricating a semiconductor structure according to claim 10, wherein the step of forming the first electrode comprises:

forming an insulating film on the substrate, wherein a groove penetrating through the thickness of the insulating film is formed in the insulating film;

and forming the first electrode, wherein the first electrode is positioned at the bottom and the side wall of the groove.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein the insulating film is left as an insulating layer; the step of forming the capacitor dielectric layer and the second electrode comprises:

forming the capacitor dielectric layer, wherein the capacitor dielectric layer is positioned at the bottom and the side wall of the through hole;

and forming a second electrode layer which is positioned on the surface of the capacitance medium layer and fills the through hole.

13. The method of fabricating a semiconductor structure of claim 11, wherein the step of forming the capacitor dielectric layer and the second electrode comprises:

removing the residual insulating film to expose the outer side wall of the through hole;

forming the capacitor dielectric layer, wherein the capacitor dielectric layer is positioned at the bottom, the inner side wall and the outer side wall of the through hole;

and forming the second electrode, wherein the second electrode is positioned on the surface of the capacitor dielectric layer and is also positioned in the through hole and on the outer side wall of the through hole.

14. The method of fabricating a semiconductor structure of claim 13, further comprising: forming an insulating layer on the substrate; the process steps for forming the insulating layer and the second electrode include:

forming a first main body part and a second main body part, wherein the first main body part is positioned in the through hole, the second main body part is positioned on the outer side wall of the through hole, and the material of the second main body part is the same as that of the first main body part;

forming the insulating layer on the substrate, wherein the insulating layer is positioned on the side wall of the second main body part;

and forming an electric connection part, wherein the electric connection part crosses the first main body part and the second main body part and is in contact with the top surface of the first main body part and the top surface of the second main body part, and the electric connection part, the first main body part and the second main body part jointly form the second electrode.

15. The method of fabricating a semiconductor structure according to claim 10, further comprising, before forming the first electrode: and forming an electric connection layer on the substrate, wherein the electric connection layer is electrically connected with the first electrode.