CN115483160A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN115483160A CN115483160A CN202211215968.7A CN202211215968A CN115483160A CN 115483160 A CN115483160 A CN 115483160A CN 202211215968 A CN202211215968 A CN 202211215968A CN 115483160 A CN115483160 A CN 115483160A
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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Abstract
The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, wherein a first transistor array comprising a plurality of first semiconductor columns is arranged on the substrate; forming a plurality of first contact structures on the top surface of the first semiconductor pillar; forming a first capacitance, the first capacitance comprising: the first electrode is correspondingly connected with the first contact structure; a first dielectric layer covering the top and sidewalls of the first electrode; a second electrode covering and filling the gap between the first dielectric layers; forming a second capacitor, the second capacitor sharing a second electrode with the first capacitor, the second capacitor further comprising: a second dielectric layer with bottom and side walls in the second electrode; a third electrode filling the gap between the second dielectric layers; and forming a plurality of second contact structures on the top surface of the third electrode, and forming a second transistor array comprising a plurality of second semiconductor columns, wherein the bottoms of the second semiconductor columns are correspondingly connected with the second contact structures so as to improve the integration density of the semiconductor structures.
Description
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
With the trend of miniaturization of various electronic products, the design of Dynamic Random Access Memory (DRAM) cells must meet the requirements of high integration and high density.
In order to improve the performance of the cell and reduce the cell area, a capacitor with a large capacitance value needs to be fabricated on a unit area, but the capacitor usually occupies a large space to have a better charge storage performance.
Therefore, how to increase the integration density of the semiconductor structure, obtain a larger charge storage capability, and reduce the process difficulty is an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof, so as to improve the integration density of the semiconductor structure.
According to some embodiments of the present disclosure, in one aspect, a method for fabricating a semiconductor structure is provided, including: providing a substrate, wherein a first transistor array is arranged on the substrate and comprises a plurality of first semiconductor columns; forming a plurality of first contact structures, the first contact structures being located on top surfaces of the first semiconductor pillars; forming a first capacitance, the first capacitance comprising: the first electrode is correspondingly connected with the first contact structure; a first dielectric layer covering the top and sidewalls of the first electrode; the second electrode covers and fills the gap between the first dielectric layers; forming a second capacitor, the second capacitor sharing a second electrode with the first capacitor, the second capacitor further comprising: the bottom and the side wall of the second dielectric layer are positioned in the second electrode; the third electrode is used for filling gaps among the second dielectric layers; and forming a plurality of second contact structures and a second transistor array, wherein the second contact structures are positioned on the top surfaces of the third electrodes, the second transistor array comprises a plurality of second semiconductor columns, and the bottoms of the second semiconductor columns are correspondingly connected with the second contact structures.
In some embodiments, forming the first electrode comprises: forming an insulating layer which covers and fills gaps between the first contact structures; forming a plurality of first electrode holes in the insulating layer, wherein the first electrode holes expose the top surface of the first contact structure; and filling a conductive material in the first electrode hole to form a first electrode.
In some embodiments, forming the first electrode comprises: forming an insulating layer which covers and fills gaps between the first contact structures; forming a plurality of first electrode holes in the insulating layer, wherein the first electrode holes expose the top surface of the first contact structure; and forming a first electrode, wherein the first electrode covers the side wall of the first electrode hole and the top surface of the first contact structure.
In some embodiments, forming a first dielectric layer comprises: removing part of the insulating layer, wherein the top surface of the rest insulating layer is flush with the top surface of the first contact structure; and forming a first dielectric layer on the top and the side wall of the first electrode, wherein the first dielectric layer also covers the top of the insulating layer.
In some embodiments, forming a first dielectric layer comprises: removing the insulating layer; and forming a first dielectric layer on the top and the side wall of the first electrode, wherein the first dielectric layer also covers the side wall of the first contact structure and the top of the first transistor array.
In some embodiments, forming the second electrode and the second dielectric layer comprises: forming an initial first electrode layer, wherein the initial first electrode layer covers and fills gaps among the first dielectric layers; forming a sacrificial layer, wherein the sacrificial layer covers the top surface of the initial first electrode layer; forming a plurality of dielectric holes in the sacrificial layer, the dielectric holes exposing the top surface of the initial first electrode layer, the projections of the dielectric holes on the substrate being located between the projections of the first electrode on the substrate; filling a conductive material into the dielectric hole to form an initial second electrode layer; and removing the sacrificial layer, and forming a second dielectric layer to cover the top and the side wall of the initial second electrode layer and the exposed top of the initial first electrode layer, wherein the initial first electrode layer and the initial second electrode layer jointly form a second electrode.
In some embodiments, forming a second dielectric layer comprises: forming a plurality of second electrode holes in the second electrode, wherein the second electrode holes correspond to the first electrode; and forming a second dielectric layer at the bottom and the side wall of the second electrode hole.
In some embodiments, the first transistor array further comprises: the first semiconductor pillar extends along a third direction, the bottom of the first semiconductor pillar is connected with the first bit line, the bottoms of the first semiconductor pillars along the first direction are connected with the same first bit line, the first word line surrounds the first semiconductor pillars, and the same first word line surrounds the first semiconductor pillars along the second direction.
In some embodiments, the second semiconductor pillar extends along a third direction, the forming the second transistor array further comprising: forming a plurality of second word lines extending along a fourth direction, wherein the second word lines surround the second semiconductor pillars, and the same second word lines surround the second semiconductor pillars along the fourth direction; and forming a plurality of second bit lines extending along the fifth direction, wherein the tops of the second semiconductor pillars are connected with the second bit lines, and the tops of the plurality of second semiconductor pillars along the fifth direction are connected with the same second bit line.
In some embodiments, the first direction makes an angle of 0 ° to 30 ° with the fifth direction, and the second direction makes an angle of 0 ° to 30 ° with the fourth direction. In some embodiments, forming the second array of transistors further comprises: and forming a plurality of bit line control buses extending along the third direction, wherein one end of each bit line control bus is connected with the first bit line, and the other end of each bit line control bus is connected with the second bit line.
According to some embodiments of the present disclosure, there is also provided in another aspect of the embodiments of the present disclosure a semiconductor structure, including: a substrate on which a first transistor array is disposed, the first transistor array including a plurality of first semiconductor pillars; a plurality of first contact structures located on a top surface of the first semiconductor pillar; a first capacitor, the first capacitor comprising: the first electrode is correspondingly connected with the first contact structure; a first dielectric layer covering the top and sidewalls of the first electrode; the second electrode covers and fills the gap between the first dielectric layers; a second capacitor sharing a second electrode with the first capacitor, the second capacitor further comprising: the bottom and the side wall of the second dielectric layer are positioned in the second electrode; the third electrode is used for filling gaps among the second dielectric layers; a plurality of second contact structures on a top surface of the third electrode; and the second transistor array comprises a plurality of second semiconductor columns, and the bottoms of the second semiconductor columns are correspondingly connected with the second contact structures.
In some embodiments, the first electrode has at least one section that is U-shaped or at least one section that is rectangular, and the third electrode has at least one section that is U-shaped or at least one section that is rectangular.
In some embodiments, the cross-sectional shape of the first electrode is the same as the cross-sectional shape of the third electrode.
In some embodiments, the projection of the first electrode on the substrate coincides with the projection of the third electrode on the substrate.
In some embodiments, the semiconductor structure further comprises: and the support structure is positioned between the adjacent first electrodes and also positioned between the adjacent third electrodes.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: correspondingly connecting the transistor structures in the first transistor array with the first capacitor by forming a first contact structure on the top of the first semiconductor pillar in the first transistor array and correspondingly connecting the first capacitor with the first contact structure; a second capacitor, a second contact structure and a second transistor array which are correspondingly connected with the second capacitor are continuously formed on the first capacitor, so that the transistor structures in the second transistor array are correspondingly connected with the second capacitor, and the transistor structures and the corresponding capacitor structures are arranged in a stacked mode, so that the space utilization rate of the semiconductor structure can be improved, and the integration density of the semiconductor structure can be increased; the second capacitor and the first capacitor share the second electrode, namely the first capacitor and the second capacitor share the upper polar plate, so that the capacitor manufacturing process in the semiconductor structure can be reduced, and the manufacturing efficiency of the semiconductor structure is improved.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, the drawings are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 to fig. 12 are schematic structural views of steps corresponding to a manufacturing method of a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
As can be seen from the background art, how to increase the integration density of a semiconductor structure, obtain a larger charge storage capability, and reduce the process difficulty is an important technical problem to be solved urgently by those skilled in the art.
It is found that, in order to improve the cell performance and reduce the cell area, a capacitor with a large capacitance value needs to be fabricated on a unit area, but the capacitor usually needs to occupy a larger space to have a better charge storage performance. Generally, in order to ensure the storage capacity of the capacitor, it is necessary to extend an electrode in a direction perpendicular to a substrate, for example, to provide a lower electrode having a columnar structure, and on a substrate in a unit area, the integration density of a semiconductor structure may be improved by reducing the size of a transistor structure, but the smaller the size of the transistor structure is, the higher the corresponding manufacturing difficulty is, and the higher the difficulty of the corresponding capacitor structure process is.
According to some embodiments of the present disclosure, an aspect of the present disclosure provides a method for fabricating a semiconductor structure, which improves an integration density of the semiconductor structure.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter may be practiced without these specific details or with various changes and modifications based on the following embodiments.
Fig. 1 to 12 are schematic structural diagrams of steps corresponding to a manufacturing method of a semiconductor structure according to an embodiment of the present disclosure, wherein fig. 2 to 12 are schematic structural diagrams of a cross section of fig. 1 along an AA1 direction, and the manufacturing method of the semiconductor structure according to the embodiment will be described in detail below with reference to the accompanying drawings, specifically as follows:
referring to fig. 1, a substrate 101 is provided, a first transistor array 100 is disposed on the substrate 101, the first transistor array 100 includes a plurality of first semiconductor pillars 203, the first semiconductor pillars 203 extend along a third direction Z, and further includes a plurality of first bit lines 201 extending along a first direction X and a plurality of first word lines 202 extending along a second direction Y, bottoms of the first semiconductor pillars 203 are connected to the first bit lines 201, bottoms of the plurality of first semiconductor pillars 203 along the first direction X are connected to the same first bit line 201, the first word lines 202 surround the first semiconductor pillars 203, and the same first word lines 202 surround the plurality of first semiconductor pillars 203 along the second direction Y.
It should be noted that, in this embodiment, an included angle between the first direction X and the second direction Y is 90 °, a plane where the first direction X and the second direction Y are located is parallel to the surface of the substrate 101, and the third direction Z is perpendicular to the surface of the substrate 101, that is, an included angle between the plane where the first direction and the second direction are located and the third direction is 90 °; in other embodiments, the included angle between the first direction X and the second direction Y may be 30 °, 45 ° or 60 °, and the included angle between the plane in which the first direction and the second direction are located and the surface of the substrate may be 30 °, 45 ° or 90 °, wherein the included angle between the third direction and the surface of the substrate may be 30 °, 45 ° or 60 °, the included angle between the plane in which the first direction and the second direction are located and the third direction may be 30 °, 45 ° or 60 °, and the present embodiment does not constitute a limitation on the included angle between the first direction, the second direction and the third direction.
As for the substrate, a material forming the substrate may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, indium gallium arsenide, or the like.
For the first semiconductor pillar 203, a material forming the first semiconductor pillar 203 includes at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten doped Indium Oxide), or ITO (Indium Tin Oxide). When the first semiconductor column is made of the materials, the carrier mobility of the first semiconductor column is improved, and therefore the first semiconductor column can transmit electric signals more efficiently. For example, when the material of the first semiconductor pillar is IGZO, the carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial to improving the carrier mobility in the first semiconductor pillar, thereby being beneficial to reducing the leakage current when the semiconductor structure works, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure. In addition, the retention time of the memory cell of the full wrap gate transistor configuration formed by forming the first semiconductor pillar from IGZO may exceed 400s, which is advantageous for reducing the refresh rate and power consumption of the memory.
In the present embodiment, the first semiconductor pillar 203 is formed in a cylindrical shape; in other embodiments, the shape of the first semiconductor pillar formed may be an elliptic cylinder or a polygonal cylinder. It can be understood that, when the first semiconductor pillar is a cylinder or an elliptical cylinder, the surface of the first semiconductor pillar is smooth, so that the phenomenon of point discharge or electric leakage can be prevented when the first semiconductor pillar operates, and when the first semiconductor pillar is a polygonal prism, chamfering processing can be performed on the edges and corners of the first semiconductor pillar, so that the angle of the first semiconductor pillar is in gentle transition, and the phenomenon of electric leakage can be avoided.
For the first bit line 201, the material forming the first bit line 201 includes at least one of metal silicide, copper, or tungsten. In some embodiments, the material forming the first bit line may be a single metal, a metal compound, or an alloy. Wherein, the single metal can be copper, aluminum, tungsten, gold or silver, etc.; the metal compound may be tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least 2 of copper, aluminum, tungsten, gold, or silver. The material of the first bit line is set to be a metal material, so that the first bit line has smaller resistivity, the resistance of the first bit line is facilitated, the transmission rate of an electrical signal in the first bit line is improved, the parasitic capacitance of the first bit line is reduced, and the thermal loss is reduced to reduce the power consumption.
For the first word line, in some embodiments, the step of forming the first word line comprises: forming a first gate dielectric layer, wherein the first gate dielectric layer covers the surface of the first semiconductor column; and forming a first gate conductive layer which covers the surface of the first gate dielectric layer and surrounds the first semiconductor column. The first gate dielectric layer covers the surface of the first semiconductor column, so that the first gate conductive layer and the first semiconductor column can be prevented from reacting in the subsequent process, and the damage of a semiconductor structure is avoided.
For the first gate dielectric layer, the material for forming the first gate dielectric layer comprises at least one of silicon oxide, silicon nitride or silicon oxynitride.
For the first gate conductive layer, a material forming the first gate conductive layer includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.
Further, the first transistor array 100 further includes first isolation structures 204, and the first isolation structures 204 cover the surfaces of the substrate 101 and the first bit lines 201, fill gaps between the first semiconductor pillars 203, and are also located between the adjacent first word lines 202. The first isolation structure 204 can isolate the adjacent first semiconductor pillar, the first word line or the first bit line, so as to avoid the damage of the semiconductor structure caused by the mutual communication among the different first semiconductor pillars, the first word lines or the first bit lines, and improve the stability of the semiconductor structure.
For the first isolation structure 204, the material forming the first isolation structure 204 includes silicon oxide, silicon nitride, silicon oxynitride, and the like.
Referring to fig. 2 and 3, a plurality of first contact structures 205 are formed, wherein the first contact structures 205 are located on the top surfaces of the first semiconductor pillars 203.
For the first contact structure 205, the material forming the first contact structure 205 includes copper, titanium nitride, tungsten, or the like.
Referring to fig. 2, in some embodiments, the step of forming the first contact structure 205 comprises: forming a first contact layer covering the surface of the first transistor array 100; the first contact layer is patterned to form a first contact structure 205.
Referring to fig. 3, in other embodiments, the step of forming the first contact structure 205 includes: removing a portion of the high-height first semiconductor pillars 203; a first contact structure 205 is formed on the surface of the first semiconductor pillar 203.
Referring to fig. 4, a first capacitor 110 is formed, the first capacitor 110 including: a first electrode 211 correspondingly connected to the first contact structure 205; a first dielectric layer 212 covering the top and sidewalls of the first electrode 211; and a second electrode 213 covering and filling the gap between the first dielectric layers 212.
For the first electrode 211, a material forming the first electrode 211 includes at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.
For the second electrode 213, a material forming the second electrode 213 includes at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.
In some embodiments, the first electrode 211 is the same material as the second electrode 213; in other embodiments, the material of the first electrode may be different from the material of the second electrode.
For the first dielectric layer, the material forming the first dielectric layer includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.
In some embodiments, forming the first electrode 211 includes: referring to fig. 5, an insulating layer 220 is formed, the insulating layer 220 covering and filling the gap between the first contact structures 205; forming a plurality of first electrode holes in the insulating layer, the first electrode holes exposing a top surface of the first contact structure 205; the first electrode hole is filled with a conductive material to form the first electrode 211. Therefore, the columnar first electrode 211 can be formed, the top surface and the side wall of the columnar first electrode 211 form the lower electrode plate of the first capacitor, the manufacturing process of the columnar first electrode 211 is simple, and the manufacturing efficiency of the semiconductor structure is improved.
In other embodiments, forming the first electrode 211 includes: referring to fig. 6, an insulating layer 220 is formed, the insulating layer 220 covering and filling the gap between the first contact structures 205; forming a plurality of first electrode holes in the insulating layer 220, the first electrode holes exposing the top surface of the first contact structure 205; a first electrode 211 is formed, the first electrode 211 covering the sidewalls of the first electrode hole and the top surface of the first contact structure 205. Therefore, the cup-shaped first electrode 211 can be formed, the outer side wall and the inner side wall of the cup-shaped first electrode 211 and the bottom surface connected with the inner side wall form a lower polar plate of the first capacitor, so that the area of the lower polar plate of the first capacitor is increased, the charge storage capacity of the first capacitor is improved, and the use performance of the semiconductor structure is further improved.
For the insulating layer 220, a material forming the insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, or the like.
Further, referring to fig. 7, in some embodiments, forming the first dielectric layer 212 includes: removing a portion of the insulating layer 220, leaving a top surface of the insulating layer 220 flush with a top surface of the first contact structure 205; a first dielectric layer 212 is formed on top and on the sidewalls of the first electrode 211, and the first dielectric layer 212 further covers the top of the insulating layer 220. The insulating layer 220 fills gaps between different first contact structures 205, so that the semiconductor structure is prevented from being damaged due to the fact that the adjacent first contact structures 205 are communicated with each other, and the stability of the semiconductor structure is improved.
In other embodiments, referring to fig. 8, forming the first dielectric layer 212 includes: removing the insulating layer 220; a first dielectric layer 212 is formed on top and sidewalls of the first electrode 211, the first dielectric layer 212 further covering sidewalls of the first contact structure 205 and a top of the first transistor array. The first dielectric layer 212 also covers the sidewalls of the first contact structure 205, so that the first capacitor formed by the first electrode surrounds the first contact structure 205, thereby increasing the capacitance of the first capacitor.
In this embodiment, the first dielectric layer is a single-layer structure; in other embodiments, the first dielectric layer may be a multi-layer structure, for example, the first dielectric layer may be formed by stacking titanium oxide/zirconium oxide/titanium oxide layers, and the multi-layer structure of the first dielectric layer may prevent the leakage current from increasing, which may result in device failure.
In some embodiments, the first dielectric layer may be further doped with at least one of silicon nitride and silicon oxynitride. The doped silicon nitride or silicon oxynitride only occupies part of vacancies in the first dielectric layer and does not form a complete film, and the doping of the silicon nitride or the silicon oxynitride can further reduce the electric leakage in the first dielectric layer.
Referring to fig. 9, a second capacitor 120 is formed, the second capacitor 120 shares a second electrode 213 with the first capacitor 110, and the second capacitor 120 further includes: a second dielectric layer 222, the bottom and sidewalls of which are located within the second electrode 213; and a third electrode 221 filling the gap between the second dielectric layers 222.
For the third electrode 221, a material forming the third electrode 221 includes at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.
In some embodiments, the material of the third electrode may be the same as the material of the second electrode; in other embodiments, the material of the third electrode may be different from the material of the second electrode. In some embodiments, the material of the third electrode may be the same as the material of the first electrode; in other embodiments, the material of the third electrode may be different from the material of the first electrode.
For the second dielectric layer, the material forming the second dielectric layer includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.
In some embodiments, forming the second electrode 213 and the second dielectric layer 222 includes: referring to fig. 10, an initial first electrode layer 313 is formed, the initial first electrode layer 313 covers and fills the gap between the first dielectric layers 212; forming a sacrificial layer 301, the sacrificial layer 301 covering a top surface of the initial first electrode layer 313; forming a plurality of dielectric holes in the sacrificial layer 301, wherein the dielectric holes expose the top surface of the initial first electrode layer 313, and the projection of the dielectric holes on the substrate 101 is positioned between the projections of the first electrode 211 on the substrate 101; filling a conductive material into the dielectric hole to form an initial second electrode layer 323; referring to fig. 11, the sacrificial layer 301 is removed, and a second dielectric layer 222 is formed to cover the top and sidewalls of the initial second electrode layer 323 and the exposed top of the initial first electrode layer 313, the initial first electrode layer 313 and the initial second electrode layer 323 together constituting the second electrode 213.
As for the sacrificial layer 301, a material forming the sacrificial layer 301 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.
In some embodiments, forming a second dielectric layer comprises: forming a plurality of second electrode holes in the second electrode, wherein the second electrode holes correspond to the first electrode; and forming a second dielectric layer at the bottom and the side wall of the second electrode hole. That is, when the height of the second electrode above the first electrode is high, the second electrode hole may be directly formed in the second electrode, and the second dielectric layer and the second electrode may be formed in the second electrode hole, so as to reduce the steps of the semiconductor structure manufacturing process and improve the manufacturing efficiency of the semiconductor structure.
In this embodiment, the second dielectric layer is a single-layer structure; in other embodiments, the second dielectric layer may be a multi-layer structure, for example, the second dielectric layer may be formed by stacking a titanium oxide/zirconium oxide/titanium oxide layer, and the second dielectric layer with a multi-layer structure may prevent an increase in leakage current, which may result in device failure.
In some embodiments, the second dielectric layer may be further doped with at least one of silicon nitride and silicon oxynitride. The doped silicon nitride or silicon oxynitride only occupies part of vacancies in the second dielectric layer and does not form a complete film, and the doping of the silicon nitride or the silicon oxynitride can further reduce the electric leakage in the second dielectric layer.
In this embodiment, the first electrode is a columnar structure, and the third electrode and the first electrode have the same shape and are of the columnar structure; in other embodiments, the first electrode may also be a cup-shaped structure, the shape of the third electrode may be different from that of the first electrode, and the present embodiment does not constitute a definition of the shape of the first electrode and the shape of the third electrode.
Referring to fig. 12, a plurality of second contact structures 206 and a second transistor array 200 are formed, the second contact structures 206 are located on the top surfaces of the third electrodes 221, the second transistor array 200 includes a plurality of second semiconductor pillars 303 extending along the third direction Z, and the bottoms of the second semiconductor pillars 303 are correspondingly connected to the second contact structures 206.
Further, in some embodiments, forming the second transistor array 200 further comprises: forming a plurality of second wordlines 302 extending along a fourth direction, the second wordlines 302 surrounding the second semiconductor pillars 303, and the same second wordlines 302 surrounding the plurality of second semiconductor pillars 303 along the fourth direction; a plurality of second bit lines 305 extending in the fifth direction are formed, the tops of the second semiconductor pillars 303 are connected to the second bit lines 305, and the tops of the plurality of second semiconductor pillars 303 in the fifth direction are connected to the same second bit line 305.
In some embodiments, the first direction may be at an angle of 0 ° to 30 ° to the fifth direction, in particular, the first direction may be at an angle of 0 °, 20 ° or 30 ° to the fifth direction, the second direction may be at an angle of 0 ° to 30 ° to the fourth direction, in particular, the second direction may be at an angle of 0 °, 20 ° or 30 ° to the fourth direction. It can be understood that the second transistor array is controlled to be turned on by the second word line and the second bit line, and when the extending directions of the second word line and the second bit line are different, the transistors in the second transistor array can be positioned and gated, wherein the second word line can be parallel to the first word line, and can also have a certain included angle with the first word line; the second bit line may be parallel to the first bit line or may have an angle with the first bit line.
In some embodiments, the second transistor array 200 further includes second isolation structures 304, the second isolation structures 304 covering the surface of the second dielectric layer 222, filling gaps between the second semiconductor pillars 303, and further being located between adjacent second word lines 302. The second isolation structure 304 may isolate the adjacent second semiconductor pillar and the second word line, so as to avoid the damage of the semiconductor structure caused by the mutual communication between different second semiconductor pillars or second word lines, and improve the stability of the semiconductor structure.
For the second isolation structure 304, the material forming the second isolation structure 304 includes silicon oxide, silicon nitride, silicon oxynitride, and the like.
For the second semiconductor pillars 303, a material forming the second semiconductor pillars 303 includes at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten doped Indium Oxide), or ITO (Indium Tin Oxide).
In the present embodiment, the material of the second semiconductor pillar is the same as that of the first semiconductor pillar, and is represented by the same feature; in other embodiments, the material of the second semiconductor pillar may be different from the material of the first semiconductor pillar.
For the second word line, in some embodiments, the step of forming the second word line comprises, for the second word line: forming a second gate dielectric layer, wherein the second gate dielectric layer covers the surface of the second semiconductor column; and forming a second gate conducting layer which covers the surface of the second gate dielectric layer and surrounds the second semiconductor column. The second gate dielectric layer covers the surface of the second semiconductor column, so that the second gate conductive layer and the second semiconductor column can be prevented from reacting in the subsequent process, and the damage of the semiconductor structure is avoided.
For the second gate dielectric layer, the material for forming the second gate dielectric layer comprises at least one of silicon oxide, silicon nitride or silicon oxynitride.
For the second gate conductive layer, a material forming the second gate conductive layer includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.
In the present embodiment, the material of the second word line is the same as that of the first word line, and is represented by the same features; in other embodiments, the material of the second word line may be different from the material of the first word line.
For the second bit line, the material forming the second bit line includes at least one of a metal silicide, copper, or tungsten. In some embodiments, the material forming the second bit line may be an elemental metal, a metal compound, or a metal silicide. Wherein, the elementary metal can be copper, aluminum, tungsten, gold or silver, etc.; the metal compound may be tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least 2 of copper, aluminum, tungsten, gold, or silver. The material of the second bit line is set to be a metal material, so that the second bit line has smaller resistivity, the resistance of the second bit line is facilitated, the transmission rate of electrical signals in the second bit line is improved, the parasitic capacitance of the second bit line is reduced, and the thermal loss is reduced to reduce the power consumption.
In the present embodiment, the material of the second bit line is the same as that of the first bit line, and is represented by the same features; in other embodiments, the material of the second bit line may be different from the material of the first bit line.
Further, in some embodiments, after the second transistor array is formed, a third transistor array, a third capacitor, a fourth transistor array, and a fourth capacitor may be further stacked above the second transistor array, where the third transistor array has the same structure as the first transistor array, the third transistor array and the second transistor array share a second bit line, the third capacitor has the same structure as the first capacitor, the fourth capacitor has the same structure as the second capacitor, the third capacitor and the fourth capacitor share an upper plate, and the fourth transistor array and the second transistor array have the same structure. Therefore, repeatedly stacked transistors and capacitor structures can be formed on the substrate, and the capacitor structures corresponding to the adjacent transistor structures can share the upper polar plate, so that the space utilization rate of the semiconductor structure is improved, and the integration density and the use performance of the semiconductor structure are increased.
In some embodiments, a projection of the semiconductor pillars in the third transistor array onto the substrate coincides with a projection of the first semiconductor pillars in the first transistor array onto the substrate, or a projection of the semiconductor pillars in the third transistor array onto the substrate coincides with a projection of the second semiconductor pillars in the second transistor array onto the substrate; in other embodiments, the projection of the semiconductor pillars in the third transistor array on the substrate is not coincident with the projection of the first semiconductor pillars in the first transistor array on the substrate, i.e., the transistor structures in the third transistor array are distributed with a misalignment with the transistor structures in the first transistor array, or the projection of the semiconductor pillars in the third transistor array on the substrate is not coincident with the projection of the second semiconductor pillars in the second transistor array on the substrate, i.e., the transistor structures in the third transistor array are distributed with a misalignment with the transistor structures in the second transistor array. Similarly, the transistor structures in the fourth transistor array may be distributed corresponding to the transistor structures in the first transistor array or the transistor structures in the second transistor array, or the transistor structures in the fourth transistor array may be distributed in a staggered manner from the transistor structures in the first transistor array or the transistor structures in the second transistor array. In some embodiments, after forming the second transistor array, further comprising: and forming a plurality of bit line control buses extending along the third direction, wherein one end of each bit line control bus is connected with the first bit line, and the other end of each bit line control bus is connected with the second bit line. The first bit line of the first transistor array is connected with the second bit line of the second transistor array through the bit line control bus, so that the first bit line and the second bit line can share the same control port, and the control capability of the semiconductor structure is improved.
According to the manufacturing method of the semiconductor structure provided by the embodiment of the disclosure, the first contact structure is formed on the top of the first semiconductor pillar in the first transistor array, and the first capacitor is correspondingly connected with the first contact structure, so that the transistor structure in the first transistor array is correspondingly connected with the first capacitor; a second capacitor, a second contact structure and a second transistor array which are correspondingly connected with the second capacitor are continuously formed on the first capacitor, so that the transistor structures in the second transistor array are correspondingly connected with the second capacitor, and the transistor structures and the corresponding capacitor structures are stacked, so that the space utilization rate of the semiconductor structure can be improved, and the integration density of the semiconductor structure can be increased; the second capacitor and the first capacitor share the second electrode, namely the first capacitor and the second capacitor share the upper polar plate, so that the capacitor manufacturing process in the semiconductor structure can be reduced, and the manufacturing efficiency of the semiconductor structure is improved.
According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure formed by the method for manufacturing a semiconductor structure provided in the above embodiments, for increasing the integration density of the semiconductor structure. It should be noted that, for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the corresponding description of the foregoing embodiments, and detailed description will not be given below.
With continued reference to fig. 12, embodiments of the present disclosure provide a semiconductor structure comprising: a substrate 101, a first transistor array 100 disposed on the substrate 101, the first transistor array 100 comprising a plurality of first semiconductor pillars 203; a plurality of first contact structures 205 on a top surface of the first semiconductor pillars 203; a first capacitor 12, the first capacitor 12 comprising: a first electrode 211 correspondingly connected to the first contact structure 205; a first dielectric layer 212 covering the top and sidewalls of the first electrode 211; a second electrode 213 covering and filling the gap between the first dielectric layers 212; a second capacitor 120, the second capacitor 120 and the first capacitor 110 sharing a second electrode 213, the second capacitor 120 further comprising: a second dielectric layer 222, the bottom and sidewalls being located within the second electrode 213; a third electrode 221 filling a gap between the second dielectric layers 222; a plurality of second contact structures 206 on a top surface of the third electrode 221; the second transistor array 200 includes a plurality of second semiconductor pillars 303, and bottoms of the second semiconductor pillars 303 are correspondingly connected to the second contact structures 206.
The top of a first semiconductor column in the first transistor array is correspondingly connected with the first capacitor through a first contact structure, the bottom of a second semiconductor column in the second transistor array is correspondingly connected with the second capacitor through a second contact structure, the space utilization rate of the transistor structure and the corresponding capacitor structure is improved in a stacking mode, and the integration density of the semiconductor structure is increased; the second capacitor and the first capacitor share the second electrode, namely the first capacitor and the second capacitor share the upper polar plate, so that the utilization rate of the upper polar plate of the capacitor in the semiconductor structure can be improved, the capacitor manufacturing process in the semiconductor structure is reduced, and the manufacturing efficiency of the semiconductor structure is improved.
In some embodiments, the first electrode has at least one section that is U-shaped or at least one section that is rectangular, and the third electrode has at least one section that is U-shaped or at least one section that is rectangular. That is to say, the first electrode may be a cup-shaped structure or a columnar structure, and the third electrode may be a cup-shaped structure or a columnar structure, it can be understood that the top and the side wall of the first electrode of the columnar structure correspondingly form the lower electrode plate of the first capacitor, and the bottom and the side wall of the third electrode of the columnar structure correspondingly form the lower electrode plate of the second capacitor, and the capacitor of the columnar structure has a simple structure, so that the semiconductor structure is convenient for the process manufacturing, and the semiconductor structure manufacturing efficiency is improved; the first electrode of the cup-shaped structure is provided with an inner side wall, an outer side wall and a bottom surface connected with the inner side wall to form a lower electrode plate of the first capacitor, the third electrode of the cup-shaped structure is provided with an inner side wall, an outer side wall and a top surface connected with the inner side wall to form a lower electrode plate of the second capacitor, and the cup-shaped capacitor can increase the relative area of the upper electrode plate and the lower electrode plate of the capacitor, so that the storage capacity of the capacitor is improved.
In this embodiment, the cross-sectional shape of the first electrode is the same as the cross-sectional shape of the third electrode, that is, the first electrode and the third electrode have the same structure; in other embodiments, the cross-sectional shape of the first electrode and the cross-sectional shape of the third electrode may be different. In this embodiment, the projection of the first electrode on the substrate coincides with the projection of the third electrode on the substrate, that is, the first electrode and the third electrode are in a facing manner, and the corresponding first capacitor and the second capacitor are in a facing distribution manner; in other embodiments, the projection of the first electrode on the substrate and the projection of the third electrode on the substrate may not coincide, that is, the first electrode and the third electrode are in a staggered manner, and the corresponding first capacitance and the second capacitance are in a staggered distribution manner.
In some embodiments, the semiconductor structure further comprises: and the support structure is positioned between the adjacent first electrodes and also positioned between the adjacent third electrodes. It can be understood that, when the height of the capacitor is high, in order to prevent the capacitor from toppling over due to a high aspect ratio, the support structures are located between the adjacent first electrodes and between the adjacent third electrodes, so that the stability of the first electrodes and the stability of the third electrodes can be improved, the first electrodes and the third electrodes are prevented from deforming, and the reliability of the semiconductor structure is improved.
In the semiconductor structure provided by the embodiment of the disclosure, in the first transistor array, the top of the first semiconductor pillar is correspondingly connected with the first capacitor through the first contact structure, in the second transistor array, the bottom of the second semiconductor pillar is correspondingly connected with the second capacitor through the second contact structure, and by stacking the first transistor array and the corresponding first capacitor as well as the second transistor array and the second capacitor, the space utilization rate of the transistor structure and the corresponding capacitor structure can be improved, and the integration density of the semiconductor structure is increased; the second capacitor and the first capacitor share the second electrode, namely the first capacitor and the second capacitor share the upper polar plate, so that the utilization rate of the upper polar plate of the capacitor in the semiconductor structure can be improved, the capacitor manufacturing process in the semiconductor structure can be reduced, and the manufacturing efficiency of the semiconductor structure can be improved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice.
Claims (16)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein a first transistor array is arranged on the substrate and comprises a plurality of first semiconductor columns;
forming a plurality of first contact structures on a top surface of the first semiconductor pillar;
forming a first capacitance, the first capacitance comprising: the first electrode is correspondingly connected with the first contact structure; the first dielectric layer covers the top and the side wall of the first electrode; the second electrode covers and fills the gap between the first dielectric layers;
forming a second capacitance that shares the second electrode with the first capacitance, the second capacitance further comprising: the bottom and the side wall of the second dielectric layer are positioned in the second electrode; the third electrode is used for filling gaps among the second dielectric layers;
and forming a plurality of second contact structures and a second transistor array, wherein the second contact structures are positioned on the top surfaces of the third electrodes, the second transistor array comprises a plurality of second semiconductor columns, and the bottoms of the second semiconductor columns are correspondingly connected with the second contact structures.
2. The method of fabricating a semiconductor structure of claim 1, wherein forming the first electrode comprises:
forming an insulating layer covering and filling gaps between the first contact structures;
forming a plurality of first electrode holes in the insulating layer, wherein the first electrode holes expose the top surface of the first contact structure;
and filling a conductive material in the first electrode hole to form the first electrode.
3. The method of fabricating a semiconductor structure according to claim 1, wherein forming the first electrode comprises:
forming an insulating layer covering and filling gaps between the first contact structures;
forming a plurality of first electrode holes in the insulating layer, wherein the first electrode holes expose the top surface of the first contact structure;
forming the first electrode covering the sidewalls of the first electrode hole and the top surface of the first contact structure.
4. The method of fabricating a semiconductor structure according to claim 2 or 3, wherein forming the first dielectric layer comprises:
removing part of the insulating layer, wherein the top surface of the rest insulating layer is flush with the top surface of the first contact structure; and forming the first dielectric layer on the top and the side wall of the first electrode, wherein the first dielectric layer also covers the top of the insulating layer.
5. The method of fabricating a semiconductor structure according to claim 2 or 3, wherein forming the first dielectric layer comprises:
removing the insulating layer;
and forming the first dielectric layer on the top and the side wall of the first electrode, wherein the first dielectric layer also covers the side wall of the first contact structure and the top of the first transistor array.
6. The method of fabricating a semiconductor structure of claim 1, wherein forming the second electrode and the second dielectric layer comprises:
forming an initial first electrode layer, wherein the initial first electrode layer covers and fills gaps among the first dielectric layers;
forming a sacrificial layer covering a top surface of the initial first electrode layer;
forming a plurality of dielectric holes in the sacrificial layer, the dielectric holes exposing a top surface of the initial first electrode layer, a projection of the dielectric holes on the substrate being located between projections of the first electrodes on the substrate;
filling a conductive material into the dielectric hole to form an initial second electrode layer;
and removing the sacrificial layer, and forming a second dielectric layer to cover the top and the side wall of the initial second electrode layer and the exposed top of the initial first electrode layer, wherein the initial first electrode layer and the initial second electrode layer jointly form the second electrode.
7. The method of fabricating a semiconductor structure of claim 1, wherein forming the second dielectric layer comprises:
forming a plurality of second electrode holes in the second electrode, wherein the second electrode holes correspond to the first electrode;
and forming the second dielectric layer at the bottom and the side wall of the second electrode hole.
8. The method of fabricating a semiconductor structure according to claim 1, wherein the first transistor array further comprises: the semiconductor device includes a plurality of first bit lines extending in a first direction and a plurality of first word lines extending in a second direction, the first semiconductor pillars extending in a third direction, bottoms of the first semiconductor pillars being connected to the first bit lines, bottoms of the first semiconductor pillars in the first direction being connected to the same first bit line, the first word lines surrounding the first semiconductor pillars, and the same first word lines in the second direction surrounding the first semiconductor pillars.
9. The method of fabricating a semiconductor structure according to claim 8, wherein the second semiconductor pillar extends in the third direction, and wherein forming the second array of transistors further comprises:
forming a plurality of second wordlines extending along the fourth direction, the second wordlines surrounding the second semiconductor pillars, and the same second wordlines surrounding a plurality of the second semiconductor pillars along the fourth direction;
and forming a plurality of second bit lines extending along the fifth direction, wherein the tops of the second semiconductor pillars are connected with the second bit lines, and the tops of the second semiconductor pillars in the fifth direction are connected with the same second bit line.
10. The method of claim 9, wherein an angle between the first direction and the fifth direction is 0 ° to 30 °, and an angle between the second direction and the fourth direction is 0 ° to 30 °.
11. The method of fabricating a semiconductor structure of claim 9, wherein forming the second array of transistors further comprises: and forming a plurality of bit line control buses extending along the third direction, wherein one end of each bit line control bus is connected with the first bit line, and the other end of each bit line control bus is connected with the second bit line.
12. A semiconductor structure, comprising:
a substrate on which a first transistor array is disposed, the first transistor array including a plurality of first semiconductor pillars;
a plurality of first contact structures located on a top surface of the first semiconductor pillar;
a first capacitance, the first capacitance comprising: the first electrode is correspondingly connected with the first contact structure; the first dielectric layer covers the top and the side wall of the first electrode; the second electrode covers and fills the gap between the first dielectric layers;
a second capacitance sharing the second electrode with the first capacitance, the second capacitance further comprising: the bottom and the side wall of the second dielectric layer are positioned in the second electrode; the third electrode is used for filling gaps among the second dielectric layers;
a plurality of second contact structures on a top surface of the third electrode;
and the second transistor array comprises a plurality of second semiconductor columns, and the bottoms of the second semiconductor columns are correspondingly connected with the second contact structures.
13. The semiconductor structure of claim 12, wherein the first electrode has at least one of a U-shaped cross-section or a rectangular cross-section, and the third electrode has at least one of a U-shaped cross-section or a rectangular cross-section.
14. The semiconductor structure of claim 13, wherein a cross-sectional shape of the first electrode is the same as a cross-sectional shape of the third electrode.
15. The semiconductor structure of claim 12, wherein a projection of the first electrode on the substrate coincides with a projection of the third electrode on the substrate.
16. The semiconductor structure of claim 12, further comprising: a support structure located between adjacent first electrodes and also located between adjacent third electrodes.
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