CN115224032A

CN115224032A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN115224032A
Application number: CN202110429924.3A
Authority: CN
Inventors: 肖德元
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-04-21
Filing date: 2021-04-21
Publication date: 2022-10-21

Abstract

An embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: the substrate is provided with a metal bit line, and the surface of the metal bit line is exposed out of the substrate; the semiconductor channel is positioned on the partial surface of the metal bit line, and comprises a first doping region, a channel region and a second doping region which are sequentially arranged in the direction pointing to the metal bit line along the substrate, wherein the first doping region is contacted with the metal bit line; word lines disposed around the channel region; the dielectric layer is positioned between the metal bit line and the word line and is also positioned on one side of the word line far away from the substrate; and the capacitor structure is positioned on one side of the second doped region far away from the channel region and is in contact with the second doped region. The embodiment of the invention is beneficial to improving the integration density of the semiconductor structure and reducing the power consumption of the semiconductor structure during working.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background

As the demand for high performance and low cost of semiconductor devices increases, the demand for high integration density and low power consumption of semiconductor devices also increases.

However, the increase in integration density of semiconductor devices and the reduction in power consumption when semiconductor devices are operated have placed higher demands on their manufacturing processes. The integration density of two-dimensional (2D) or planar semiconductor devices is largely determined by the area occupied by the individual functional devices (e.g., memory cells) that make up the semiconductor device. The area occupied by the individual functional devices depends to a large extent on the dimensional parameters of the electrical connection structures used to define the individual functional devices and the interconnections between the functional devices. To provide a single functional device and an electrical connection structure with finer dimensions, development costs and use costs for forming the single functional device and the electrical connection structure are high. In order to reduce the power consumption of the semiconductor device during operation, higher requirements are also put forward on the electrical connection mode between single functional devices in the semiconductor device.

Disclosure of Invention

The technical problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are beneficial to improving the integration density of the semiconductor structure and reducing the power consumption of the semiconductor structure during operation.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate is provided with metal bit lines, and the surface of the metal bit lines is exposed out of the substrate; the semiconductor channel is positioned on part of the surface of the metal bit line, and comprises a first doping region, a channel region and a second doping region which are sequentially arranged in the direction pointing to the metal bit line along the substrate, wherein the first doping region is electrically connected with the metal bit line; word lines disposed around the channel region; the dielectric layer is positioned between the metal bit line and the word line and is also positioned on one side of the word line, which is far away from the substrate; and the capacitor structure is positioned on one side of the second doped region far away from the channel region and is in contact with the second doped region.

Correspondingly, an embodiment of the present invention further provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate is internally provided with a metal bit line, and the surface of the metal bit line is exposed out of the substrate; forming a semiconductor channel, wherein the semiconductor channel is positioned on part of the surface of the metal bit line, and comprises a first doped region, a channel region and a second doped region which are sequentially arranged in a direction pointing to the metal bit line along the substrate, and the first doped region is electrically connected with the metal bit line; forming a word line disposed around the channel region; forming a dielectric layer, wherein the dielectric layer is positioned between the metal bit line and the word line and is also positioned on one side of the word line, which is far away from the substrate; and forming a capacitor structure, wherein the capacitor structure is positioned on one side of the second doped region far away from the channel region and is in contact with the second doped region.

Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:

in the above technical solution, the channel region of the semiconductor channel is vertically disposed on the surface of the metal bit line, that is, the extending direction of the channel region is vertical to the surface of the metal bit line, which is favorable for saving the layout space of the semiconductor channel in the direction (usually, the horizontal direction) parallel to the surface of the metal bit line on the premise of not reducing the size of the semiconductor channel, thereby improving the integration density of the semiconductor structure in the horizontal direction. Furthermore, the semiconductor channel is located on the surface of the metal bit line part and is in contact with the metal bit line, and the second doped region is in contact with the capacitor structure, so that the electric connection between the semiconductor channel and the metal bit line and between the semiconductor channel and the capacitor structure can be realized without an additional electric connection structure, the manufacturing cost of the semiconductor structure is favorably reduced, and the power consumption required by the transmission of electric signals among the semiconductor channel, the metal bit line and the capacitor structure is reduced. In addition, the metal bit line has low resistivity and excellent conductivity, and is beneficial to further reducing the energy consumption of the semiconductor structure during working; and the metal bit line is positioned in the substrate, which is beneficial to reducing the whole thickness of the semiconductor structure so as to further reduce the whole size of the semiconductor structure.

In addition, the device formed by the semiconductor channel is a non-junction transistor, the non-junction transistor has no PN junction, the preparation process is simple, the performance is excellent, the reliability of the device is enhanced, particularly the hot carrier injection resistance effect and the noise tolerance are enhanced, and the electrical performance of the semiconductor structure is further improved.

Drawings

One or more embodiments are illustrated by corresponding figures in the drawings, which are not to scale unless specifically noted.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention;

fig. 2 to 16 are schematic cross-sectional views of steps of a method for manufacturing a semiconductor structure according to yet another embodiment of the present invention.

Detailed Description

As is known from the background art, the integration density of the semiconductor device in the prior art needs to be improved, and the power consumption of the semiconductor device during operation needs to be reduced.

As can be seen from the analysis, the integration density of a two-dimensional (2D) or planar semiconductor device is greatly affected by the horizontal area occupied by a single functional device, and is affected by the arrangement of a plurality of functional devices and the connection of functional devices. Therefore, in order to increase the integration density of semiconductor devices, measures to reduce the size of individual functional devices or to reduce the interval between adjacent functional devices are often taken. However, the development cost and the use cost of manufacturing equipment for defining the dimensional parameters of the individual functional devices and the electrical connection structures for the interconnections between the functional devices are high. In addition, the power consumption of the semiconductor device during operation is affected by the connection manner between the functional devices, and the longer the length of the connection structure connecting the functional devices, the greater the power consumption of the semiconductor device during operation.

It can be seen that a significant increase in the integration density of semiconductor devices is achieved with an increase in the manufacturing cost thereof. Therefore, in order to increase the integration density of semiconductor devices, it is necessary to develop three-dimensional (3D) semiconductor devices, i.e., to reduce the footprint of a single functional device in the semiconductor device in the horizontal direction. In order to reduce the power consumption of the semiconductor device during operation, it is necessary to improve the connection mode between functional devices in the semiconductor device.

To solve the above problems, embodiments of the present invention provide a semiconductor structure and a method for fabricating the same. In the semiconductor structure, the arrangement mode of the semiconductor channel on the metal bit line is changed, namely the extending direction of the channel region is vertical to the surface of the metal bit line, on one hand, the first doped region of the semiconductor channel is in contact and electric connection with the metal bit line, and the second doped region is in contact and electric connection with the capacitor structure, so that the electric connection between the semiconductor channel and the metal bit line as well as between the semiconductor channel and the capacitor structure is realized without an additional electric connection structure, the manufacturing cost of the semiconductor structure is favorably reduced, and the power consumption required by the transmission of electric signals among the semiconductor channel, the metal bit line and the capacitor structure is reduced; on the other hand, on the premise that the size of the semiconductor channel does not need to be reduced, the layout space of the semiconductor channel in the direction parallel to the surface of the metal bit line is saved, and therefore the integration density of the semiconductor structure in the horizontal direction is improved. In addition, the resistivity of the metal bit line is low, so that the energy consumption of the semiconductor structure during working is further reduced; and the metal bit line is positioned in the substrate, which is favorable for reducing the overall thickness of the semiconductor structure so as to further reduce the overall size of the semiconductor structure.

To make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

An embodiment of the present invention provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention.

Referring to fig. 1, a semiconductor structure includes: a substrate 100, wherein the substrate 100 has a metal bit line 101 therein, and the substrate 100 exposes the surface of the metal bit line 101; the semiconductor channel 102 is located on a part of the surface of the metal bit line 101, and in a direction pointing to the metal bit line 101 along the substrate 100, the semiconductor channel 102 includes a first doped region I, a channel region II and a second doped region III which are arranged in sequence, and the first doped region I is in contact with the metal bit line 101; a word line 104, the word line 104 disposed around the channel region; a dielectric layer 105, wherein the dielectric layer 105 is located between the metal bit line 101 and the word line 104, and is also located on one side of the word line 104 away from the substrate 100; and the capacitor structure 106, wherein the capacitor structure 106 is located on one side of the second doped region III away from the channel region II, and the capacitor structure 106 is in contact with the second doped region III.

Since the semiconductor structure includes a vertical Gate-All-Around (GAA) transistor and the metal bit line 101 is located between the substrate 100 and the Gate-All-Around transistor, a 3D stacked memory device can be formed, which is beneficial to increasing the integration density of the semiconductor structure.

The semiconductor structure will be described in more detail below with reference to fig. 1.

In this embodiment, the substrate 100 may include: a logic circuit structure layer 110 having a plurality of logic circuits; the interlayer dielectric layer 120, the interlayer dielectric layer 120 is located on the surface of the logic circuit structure layer 110, and the metal bit line 101 is located on the partial surface of the interlayer dielectric layer 120 far away from the logic circuit structure layer 110; and an isolation layer 103, wherein the isolation layer 103 is located on the surface of the interlayer dielectric layer 120 exposed by the metal bit line 101 and covers the sidewall of the metal bit line 101. For ease of illustration, 103 is not indicated in fig. 1 within brackets corresponding to 100.

Specifically, the logic circuit structure layer 110 may be a stacked structure. The surface of the interlayer dielectric layer 120 away from the logic circuit structure layer 110 may have a plurality of metal bit lines 101 arranged at intervals, each metal bit line 101 may be in contact with and electrically connected to at least one first doping region I, and as an example, in fig. 1, each metal bit line 101 is in contact with 2 first doping regions I, and the number of the first doping regions I in contact with and electrically connected to each metal bit line 101 may be set reasonably according to actual electrical requirements. The top surface of the metal bit line 101 may be flush with the top surface of the isolation layer 103, which is advantageous for providing a good support for other structures located on the top surface of the metal bit line 101 and the top surface of the isolation layer 103.

The interlayer dielectric layer 120 is used to insulate the logic circuit structure layer 110 from the metal bit lines 101, and the interlayer dielectric layer 120 is beneficial to preventing leakage between adjacent metal bit lines 101. The material of the interlayer dielectric layer 120 includes at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon oxycarbonitride.

The isolation layer 103 is located between adjacent metal bit lines 101 for achieving insulation between the adjacent metal bit lines 101. Wherein, the material of the isolation layer 103 comprises at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the interlayer dielectric layer 120 and the isolation layer 103 are integrated, so that the interface state defect between the interlayer dielectric layer 120 and the isolation layer 103 is improved, and the performance of the semiconductor structure is improved, and the material of the interlayer dielectric layer 120 is the same as that of the isolation layer 103, which is beneficial to reducing the manufacturing process steps of the semiconductor structure and reducing the manufacturing cost and complexity of the semiconductor structure. In other embodiments, the interlayer dielectric layer and the isolation layer may be of a layered structure, and the material of the interlayer dielectric layer may be different from that of the isolation layer.

It is understood that in other embodiments, the substrate may also include: the metal bit lines are positioned on the substrate, and the adjacent metal bit lines are exposed out of part of the surface of the substrate; and the isolation layer is positioned on the surface of the substrate between the adjacent metal bit lines and used for isolating the adjacent metal bit lines. In addition, the substrate can also be provided with a groove, the position of the groove is opposite to the area between the adjacent metal bit lines, and the groove is filled with the isolation layer. It is also understood that the substrate may be an insulating substrate, or may be a stacked structure of a semiconductor substrate and an interlayer dielectric layer.

The metal bit line 101 is made of metal, and the benefits of this arrangement include: on one hand, the resistivity of the metal bit line 101 made of a metal material is generally low, which is beneficial to reducing the resistance of the metal bit line 101, improving the transmission rate of electrical signals in the metal bit line 101, reducing the parasitic capacitance of the metal bit line 101, and reducing the thermal loss to reduce the power consumption; on the other hand, the semiconductor structure may further include a circuit structure, and the circuit structure has a metal conductive layer for realizing electrical connection, such as an M0 layer, an M1 layer, an M2 layer, etc., which are commonly referred to by those skilled in the art, and the metal bit line 101 may be fabricated while forming the metal conductive layer by using the process steps of the metal conductive layer, so that the process steps of fabricating the semiconductor structure may be saved, and the cost of the semiconductor structure may be reduced.

The material of the metal bit line 101 may be a single metal, a metal compound, or an alloy. Wherein, the single metal can be copper, aluminum, tungsten, gold or silver, etc.; the metal compound may be tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least 2 of copper, aluminum, tungsten, gold, or silver. In addition, the material of the metal bit line 101 may also be at least one of nickel, cobalt, or platinum.

In some embodiments, the material of the metal bit line 101 is copper.

The semiconductor structure may include a plurality of metal bit lines 101 arranged at intervals, and each metal bit line 101 extends along a first direction; each metal bit line 101 may be electrically connected with at least 2 semiconductor channels 102.

The material of the semiconductor channel 102 at least includes one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide), and when the semiconductor channel 102 is made of the above materials, the carrier mobility of the semiconductor channel 102 is improved, so that the semiconductor channel 102 can transmit an electrical signal more efficiently.

In one example, the material of the semiconductor channel 102 is IGZO, and the carrier mobility of IGZO is 20 to 50 times that of polysilicon, which is beneficial to improving the carrier mobility of the channel region II in the semiconductor channel 102, thereby being beneficial to reducing the leakage current when the semiconductor structure works, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure. In addition, the retention time of the memory cell of the all-around gate transistor configuration composed of the IGZO semiconductor channel 102 may exceed 400s, which is advantageous for reducing the refresh rate and power consumption of the memory.

In this embodiment, the semiconductor channel 102 is a cylindrical structure, and the side surface of the semiconductor channel 102 is a smooth transition surface, which is beneficial to avoiding the phenomenon of point discharge or electric leakage of the semiconductor channel 102, and further improving the electrical performance of the semiconductor structure. It should be noted that in other embodiments, the semiconductor channel may also be an elliptic cylindrical structure, a square cylindrical structure, or other irregular structures. It can be understood that, when the semiconductor channel structure is a square columnar structure, the corner formed by the adjacent surfaces of the side walls of the square columnar structure can be a rounded corner, which can also avoid the problem of point discharge, and the square columnar structure can be a square columnar structure or a rectangular columnar structure.

The first doped region I constitutes one of a source or a drain of the transistor device and the second doped region III constitutes the other of the source or the drain of the transistor device. The semiconductor elements in the first doped region I, the channel region II and the second doped region III are the same, namely the first doped region I, the channel region II and the second doped region III are of an integral structure, so that the defect of an interface state between the first doped region I and the channel region II and the defect of an interface state between the channel region II and the second doped region III are improved, and the performance of the semiconductor structure is improved. It is understood that, in other embodiments, the semiconductor channel may also have a three-layer structure, and each layer structure serves as the first doped region, the channel region, and the third doped region.

Wherein, the first doping region I may include: the first metal semiconductor layer 112, the first metal semiconductor layer 112 is in contact with the metal bit line 101, and the resistivity of the first metal semiconductor layer 112 is smaller than that of the first doped region I outside the first metal semiconductor layer 112. Therefore, the resistivity of the first doped region I is favorably reduced, the first metal semiconductor layer 112 and the first doped region I except the first metal semiconductor layer 112 form ohmic contact, schottky barrier contact formed by direct contact between the metal bit line 101 and a semiconductor material is avoided, the ohmic contact is favorable for reducing contact resistance between the first doped region I and the metal bit line 101, and therefore energy consumption of the semiconductor structure during operation is reduced, and the RC delay effect is improved, so that the electrical performance of the semiconductor structure is improved. It is understood that in other embodiments, the semiconductor material of the first doped region may also be directly in contact with the metal bit line, i.e., the first doped region does not include the first metal semiconductor layer.

Specifically, the metal element in the first metal semiconductor layer 112 includes at least one of cobalt, nickel, or platinum. Taking the material of the semiconductor channel 102 as IGZO for example, correspondingly, the material of the first metal semiconductor layer 112 may be IGZO containing nickel, IGZO containing cobalt and nickel, IGZO containing platinum, or the like. In addition, the first metal semiconductor layer 112 may be doped with nitrogen.

The semiconductor element in the first metal semiconductor layer 112 is the same as the semiconductor element in the first doped region I except the first metal semiconductor layer 112, that is, the first doped region I is an integral structure as a whole, and the first metal semiconductor layer 112 is a part of the first doped region I, which is beneficial to improving the interface state defect between the first metal semiconductor layer 112 and the first doped region I except the first metal semiconductor layer 112 and improving the performance of the semiconductor structure. In other embodiments, the semiconductor element in the first metal semiconductor layer may also be different from the semiconductor element in the first doped region other than the first metal semiconductor layer, for example, the semiconductor element in the first metal semiconductor layer may be silicon or germanium, and accordingly, the first doped region has a double-layer structure including the first metal semiconductor layer.

In some embodiments, the semiconductor channel 102 is in contact with the metal bit line 101, i.e., the first doped region I is located on the surface of the metal bit line 101. Further, the semiconductor structure may further include: and a metal layer 108, wherein the metal layer 108 is located on the surface of the metal bit line 101 uncovered by the semiconductor channel 102, and the metal layer 108 is formed by a metal element in the first metal semiconductor layer 112. It is understood that the metal layer 108 is formed simultaneously in the process step of forming the first metal semiconductor layer 112, and the material of the metal layer 108 may be at least one of cobalt, nickel or platinum.

In other embodiments, the material of the metal bit line 101 is at least one of nickel, cobalt or platinum, and accordingly, in the manufacturing process steps of the semiconductor structure, a partial region of the metal bit line 101 in contact with the first doping region I reacts with the first doping region I to form the first metal semiconductor layer 112, so that the metal bit line 101 and the first metal semiconductor layer 112 are an integral structure, which is beneficial to further reduce the contact resistance between the metal bit line 101 and the first metal semiconductor layer 112. That is, the metal bit line 101 may provide a metal element for forming the first metal semiconductor layer 112.

The second doping region III may include: the second metal semiconductor layer 122, the second metal semiconductor layer 122 is in contact with the capacitor structure, and the resistivity of the material of the second metal semiconductor layer 122 is smaller than the resistivity of the second doped region III outside the second metal semiconductor layer 122. Thus, the resistivity of the second doping region III is favorably reduced; and ohmic contact is formed between the second metal semiconductor layer 122 and the capacitor structure, which is beneficial to reducing the contact resistance between the second doping region III and the capacitor structure, thereby reducing the energy consumption of the semiconductor structure during operation and improving the electrical performance of the semiconductor structure.

The metal element in the second metal semiconductor layer 122 includes at least one of cobalt, nickel, or platinum. In this embodiment, the metal element in the first metal semiconductor layer 112 and the metal element in the second metal semiconductor layer 122 may be the same. In other embodiments, the metal element in the first metal semiconductor layer may be different from the metal element in the second metal semiconductor layer.

In addition, the semiconductor element in the second metal semiconductor layer 122 is the same as the semiconductor element in the second doping region III except for the second metal semiconductor layer 122, that is, the second doping region III is an integral structure as a whole, and the second metal semiconductor layer 122 is a part of the second doping region III, which is beneficial to improving the interface state defect between the second metal semiconductor layer 122 and the second doping region III except for the second metal semiconductor layer 122 and improving the performance of the semiconductor structure. In other embodiments, the semiconductor element in the second metal semiconductor layer may also be different from the semiconductor element in the second doped region other than the second metal semiconductor layer, for example, the semiconductor element in the second metal semiconductor layer may be silicon or germanium, and accordingly, the second doped region has a double-layer structure including the second metal semiconductor layer.

Taking the semiconductor element as silicon for example, the second metal semiconductor layer 122 includes at least one of cobalt silicide, nickel silicide or platinum silicide. In addition, the second metal semiconductor layer 122 may be doped with nitrogen.

The semiconductor channel 102 may form a junction-free Transistor (junction Transistor), that is, the type of the doped ions in the first doped region I, the channel region II and the second doped region III is the same, for example, the doped ions are all N-type ions or all P-type ions, and further, the doped ions in the first doped region I, the channel region II and the second doped region III may be the same. Here, "junction-free" refers to no PN junction, i.e., no PN junction is present in the transistor formed by the semiconductor channel 102, and such advantages include: on one hand, the first doping region I and the second doping region III do not need to be doped additionally, so that the problem that the doping process of the first doping region I and the second doping region III is difficult to control is solved, and particularly, as the size of the transistor is further reduced, if the first doping region I and the second doping region III are doped additionally, the doping concentration is difficult to control; on the other hand, the device is a junction-free transistor, so that the phenomenon that an ultra-steep PN junction is manufactured in a nanoscale range by adopting an ultra-steep source-drain concentration gradient doping process is avoided, the problems of threshold voltage drift, leakage current increase and the like caused by doping mutation can be avoided, the short channel effect is inhibited, and the device can still work in the nanoscale range of a few nanometers, so that the integration density and the electrical performance of the semiconductor structure are further improved. It is understood that the additional doping herein refers to doping performed in order to make the doping ion types of the first doping region I and the second doping region III different from the doping ion type of the channel region.

Further, the concentration of the dopant ions of the first doped region I and the concentration of the dopant ions of the second doped region III may both be greater than the dopant concentration of the dopant ions of the channel region II. The doped ions are N-type ions or P-type ions, and specifically, the N-type ions are at least one of arsenic ions, phosphorus ions or antimony ions; the P-type ions are at least one of boron ions, indium ions or gallium ions.

The word line 104 includes: the gate dielectric layer 114 is arranged around the channel region II and is positioned on the side wall surface of the semiconductor channel 102 of the channel region II; and the gate conducting layer 124 is arranged around the channel region II and is located on the surface of the sidewall of the gate dielectric layer 114 corresponding to the channel region II.

The gate dielectric layer 114 may also be disposed around the second doped region III, i.e. on the sidewall surface of the semiconductor channel 102 of the second doped region III, so that the gate dielectric layer 114 is used to isolate the gate conductive layer 124 from the semiconductor channel 102. In addition, the gate dielectric layer 114 on the sidewall surface of the semiconductor channel 102 in the second doped region III can protect the surface of the second doped region III, so as to avoid process damage to the surface of the second doped region III during the manufacturing process, thereby further improving the electrical performance of the semiconductor structure. It is understood that in other embodiments, the gate dielectric layer may be only located on the sidewall surface of the semiconductor channel in the channel region.

The material of the gate dielectric layer 114 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride, and the material of the gate conductive layer 124 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum.

In this embodiment, the semiconductor structure may include a plurality of word lines 104 arranged at intervals, and each word line 104 extends along a second direction, which is different from the first direction, for example, the first direction may be perpendicular to the second direction. In addition, for each word line 104, each word line 104 may be disposed around the channel region II of at least one semiconductor channel 102, and the number of the semiconductor channels 102 surrounded by each word line 104 may be reasonably set according to actual electrical requirements, taking 2 semiconductor channels 102 surrounded by each word line 104 as an example in fig. 1.

Dielectric layer 105 serves to isolate metal layer 108 from word line 104 to isolate metal bit line 101 from word line 104, and also serves to isolate adjacent word line 104 from adjacent metal layer 108. That is, dielectric layer 105 is located between metal layer 108 and word line 104, and is also located in the space of adjacent word lines 104 and in the space of adjacent metal layers 108.

Dielectric layer 105 may include: a first dielectric layer 115, wherein the first dielectric layer 115 is located between the metal layer 108 and the word line 104 and in the space between the adjacent metal layers 108, so as to insulate the metal layers 108 and the word line 104, prevent electrical interference between the metal layers 108 and the word line 104, and further prevent electrical interference between the metal bit line 101 and the word line 104; a second dielectric layer 125, wherein the second dielectric layer 125 is located between the adjacent word lines 104 and is in contact with the first dielectric layer 115, and is used for realizing insulation between the adjacent word lines 104 and preventing electrical interference between the adjacent word lines 104; the second dielectric layer 125 is further disposed on the surface of the word line 104 away from the substrate 100, and is used for supporting other conductive structures on the surface of the second dielectric layer 125 away from the substrate 100 and insulating the word line 104 from other conductive structures.

The top surface of the second dielectric layer 125 may be flush with the top surface of the second doped region III, which is advantageous for providing a good supporting function for other structures located on the top surface of the second dielectric layer 125 and the top surface of the second doped region III.

In this embodiment, the material of the first dielectric layer 115 and the material of the second dielectric layer 125 are the same, and may be at least one of silicon oxide, silicon nitride, silicon oxycarbonitride, or silicon oxynitride. In other embodiments, the material of the first dielectric layer and the material of the second dielectric layer may also be different.

It is understood that in other embodiments, the dielectric layer may be other stacked film structures, and the specific structure of the stacked film structure is related to the manufacturing process steps, so as to ensure that the dielectric layer can serve the isolation purpose.

Further, the semiconductor structure further comprises: and the insulating layer 107 is positioned on one side of the second doped region III away from the substrate 100, and a through hole 10 penetrating through the insulating layer 107 is formed in the insulating layer 107, and the through hole 10 exposes the top surface of the second doped region III.

The capacitor structure 106 is located in the through hole 10, and the insulating layer 107 is used to support the capacitor structure 106, so as to prevent the capacitor structure 106 from collapsing and isolate the lower electrode layer 116 in the adjacent capacitor structure 106. The material of the insulating layer 107 includes at least one of silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon oxide.

It is understood that in other embodiments, the insulating layer may also be a stacked film structure, and the specific structure of the stacked film structure is related to the manufacturing process steps, so as to ensure that the insulating layer can serve the supporting and isolating purposes.

Specifically, the capacitor structure 106 includes: a lower electrode layer 116, wherein the lower electrode layer 116 is positioned at the bottom and the side wall of the through hole 10; a capacitor dielectric layer 126, wherein the capacitor dielectric layer 126 covers the surface of the lower electrode layer 116; and the upper electrode layer 136, wherein the upper electrode layer 136 covers the surface of the capacitance medium layer 126 and fills the through hole 10.

In this embodiment, the lower electrode layers 116 in the adjacent through holes 10 are separated from each other, the capacitor dielectric layers 126 on the surfaces of the adjacent lower electrode layers 116 are also spaced from each other, the capacitor dielectric layers 126 are also located on the partial surfaces of the insulating layers 107 close to the through holes 10, and the surfaces of the insulating layers 107 not covered by the capacitor dielectric layers 126 are covered by the first barrier layers 117. In other embodiments, the capacitor dielectric layer may cover the entire surface of the insulating layer.

The upper electrode layer 136 is also located on the surface of the first barrier layer 117 between the adjacent capacitor dielectric layers 126, that is, the upper electrode layers 136 filling the adjacent through holes 10 are connected with each other in a contact manner, and the upper electrode layers 136 are of an integral structure. In other embodiments, the upper electrode layers in adjacent through holes may have a space therebetween, so that the upper electrode layers in adjacent capacitor structures may be connected to different potentials, which is beneficial to realize diversified control of the adjacent capacitor structures.

The material of the lower electrode layer 116 and the material of the upper electrode layer 136 may be the same, and the material of the lower electrode layer 116 and the material of the upper electrode layer 136 may be at least one of platinum, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer may also be different.

The material of the capacitor dielectric layer 126 includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

In this embodiment, the semiconductor channel 102 is a columnar structure, one end surface of the columnar structure, i.e., the end surface of the first doped region I, is in contact with and electrically connected to the metal bit line 101, a portion of the sidewall of the first doped region I, which is close to the metal bit line 101, is in contact with the metal layer 108, and the other end surface of the columnar structure, i.e., the second doped region III, is in contact with the capacitor structure 106, and more specifically, the second doped region III is in contact with and electrically connected to the lower electrode layer 116.

It should be noted that, in other embodiments, the capacitor structure may also be: the lower electrode layer is filled in the through holes in the insulating layer; the capacitor dielectric layer covers the surface of the lower electrode layer, and the upper electrode layer covers the surface of the capacitor dielectric layer far away from the lower electrode layer.

In addition, the semiconductor structure further includes: and a second barrier layer 127 on a surface of the upper electrode layer 136 and a surface of the first barrier layer 117 not covered by the upper electrode layer 136, for preventing electrical interference between the upper electrode layer 136 and an external conductive structure.

The material of the first barrier layer 117 and the material of the second barrier layer 127 are the same as the material of the insulating layer 107, which is beneficial to reducing the types of materials required by the manufacturing process of the semiconductor structure and reducing the manufacturing cost and complexity of the semiconductor structure. In other embodiments, the material of the first barrier layer and the material of the second barrier layer may both be different from the material of the insulating layer.

In summary, the channel region II of the semiconductor channel 102 is vertically disposed on the metal bit line 101, on one hand, the electrical connection between the semiconductor channel 102 and the metal bit line 101 and the capacitor structure 106 can be achieved without an additional electrical connection structure, which is beneficial to reducing the complexity of the semiconductor structure and reducing the power consumption required for transmitting electrical signals between the semiconductor channel 102 and the metal bit line 101 and the capacitor structure 106; on the other hand, on the premise that the size of the semiconductor channel 102 does not need to be reduced, the layout space of the semiconductor channel 102 in the direction parallel to the surface of the metal bit line 101 is saved, so that the integration density of the semiconductor structure in the horizontal direction is improved. In addition, the metal bit line 101 has low resistivity and excellent conductivity, and is beneficial to further reducing the energy consumption of the semiconductor structure during working; and the metal bit line 101 is located in the substrate 100, which is beneficial to reducing the overall thickness of the semiconductor structure, so as to further reduce the overall size of the semiconductor structure.

In addition, the semiconductor structure provided by the embodiment can be applied to 4F ² F is a characteristic size, the memory may be a DRAM memory or an SRAM memory. Accordingly, another embodiment of the present invention provides a method for fabricating a semiconductor structure, which is used to form the semiconductor structure.

Fig. 2 to 16 are schematic cross-sectional structure diagrams corresponding to steps of a method for manufacturing a semiconductor structure according to another embodiment of the present invention, and the method for manufacturing a semiconductor structure according to this embodiment will be described in detail below with reference to the drawings, and details of the same or corresponding parts as those in the above embodiment will not be repeated below.

Referring to fig. 2 to fig. 3, a substrate 100 is provided, the substrate 100 has a metal bit line 101 therein, and the substrate 100 exposes a surface of the metal bit line 101.

Specifically, the process steps of forming the substrate 100 and the metal bit line 101 include the following steps:

referring to fig. 2, a logic circuit structure layer 110 and an interlayer dielectric layer 120 are provided in a stacked arrangement.

The interlayer dielectric layer 120 covers the entire surface of the logic circuit structure layer 110, and is used for protecting the logic circuit structure layer 110 and preventing electrical interference between the logic circuit structure layer 110 and a metal bit line formed on the interlayer dielectric layer 120.

Referring to fig. 3, a plurality of metal bit lines 101 separated from each other are formed on the surface of the interlayer dielectric layer 120, and the metal bit lines 101 expose a part of the surface of the interlayer dielectric layer 120; and forming an isolation layer 103, wherein the isolation layer 103 is located on the surface of the interlayer dielectric layer 120 exposed by the metal bit line 101 and covers the sidewall of the metal bit line 101.

For the material of the metal bit line 101, reference may be made to the corresponding description of the foregoing embodiments, and further description is omitted here. The substrate 100 may include a logic circuit structure layer 110, an interlayer dielectric layer 120, and an isolation layer 103.

It is understood that in other embodiments, the surface of the logic circuit structure layer may also have an initial dielectric layer; imaging the initial dielectric layer to form a plurality of mutually separated grooves in the initial dielectric layer, wherein the initial dielectric layer positioned below the grooves is used as an interlayer dielectric layer, and the initial dielectric layer positioned between adjacent grooves is used as an isolation layer, so that the isolation layer and the initial dielectric layer are in an integral structure; then, a metal bit line filling the trench is formed.

Referring to fig. 4, a first metal layer 118 is formed on the surface of metal bit line 101.

The first metal layer 118 is used to react with a region of a subsequently formed semiconductor channel near the metal bit line 101, so as to provide a metal element for the subsequently formed first metal semiconductor layer, thereby reducing the resistivity of the semiconductor channel. Wherein the material of the first metal layer 118 includes at least one of cobalt, nickel or platinum.

In this embodiment, the first metal layer 118 covers the entire surface of the metal bit line 101, so that the metal bit line 101 is prevented from being damaged by the etching process of the first metal layer 118. In other embodiments, the first metal layer may be only located on a portion of the surface of the metal bit line, and the location of the first metal layer corresponds to the location of the subsequently formed semiconductor channel.

In other embodiments, the first metal layer may not be formed on the surface of the metal bit line, and the semiconductor channel may be formed directly on a portion of the surface of the metal bit line. In addition, in some embodiments, the material of the metal bit line is at least one of nickel, cobalt or platinum, i.e., the metal bit line can be provided with a metal element by subsequently forming the first metal semiconductor layer, and the first metal layer does not need to be formed on the surface of the metal bit line.

Referring to fig. 5 to 6, a semiconductor channel 102 is formed, the semiconductor channel 102 is located on a portion of the surface of the metal bit line 101, and the semiconductor channel 102 includes a first doped region I, a channel region II and a second doped region III sequentially arranged in a direction pointing to the metal bit line 101 along the substrate 100, wherein the first doped region I is electrically connected to the metal bit line 101.

In this embodiment, semiconductor channel 102 is in contact with first metal layer 118; in other embodiments, the semiconductor channel may be in direct contact with the metal bit line.

Specifically, the process steps for forming the semiconductor channel 102 include the steps of:

referring to fig. 5, an initial channel layer 132 is formed, wherein the initial channel layer 132 is disposed on the metal bit line 101 and the substrate 100.

In some embodiments, with the isolation layer 103 between adjacent metal bit lines 101, the initial channel layer 132 covers the surface of the isolation layer 103.

In this embodiment, a first metal layer 118 is formed on the surface of the metal bit line 101, and the initial channel layer 132 covers the surface of the first metal layer 118. In other embodiments, the initial channel layer may directly cover the metal bit line surface.

Specifically, the method for forming the initial channel layer 132 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic compound chemical vapor deposition. Wherein, the material of the initial channel layer 132 is IGZO, IWO or ITO.

With continued reference to fig. 5, a patterned mask layer 109 is formed on the surface of the initial channel layer 132.

The mask layer 109 is used to define the location and dimensions of the subsequently formed semiconductor channel 102. The material of the mask layer 109 may be silicon nitride, silicon carbonitride or silicon oxycarbonitride. In other embodiments, the material of the mask layer may also be photoresist.

Referring to fig. 6, the initial channel layer 132 (see fig. 5) is patterned using the mask layer 109 as a mask to form the semiconductor channel 102.

The semiconductor channel 102 includes a first doped region I, a channel region II, and a second doped region III arranged in this order.

The first doped region I, the channel region II and the second doped region III in the semiconductor channel 102 are doped with the same type of dopant ions, so that a device formed by the semiconductor channel 102 is a junction-less transistor, the problems of threshold voltage drift and leakage current increase caused by doping mutation are avoided, and the short channel effect is favorably inhibited.

It is understood that the initial channel layer 132 may be doped in advance before the patterning process, and the doping process may be doping N-type ions or P-type ions; the initial channel layer 132 may also be patterned and then doped to form a semiconductor channel 102 with a suitable ion distribution.

In this embodiment, the semiconductor channel 102 may be rounded by thermal oxidation, etching and/or hydrogen annealing to form the semiconductor channel 102 having a cylindrical structure, which is beneficial to avoid the phenomenon of point discharge or current leakage of the semiconductor channel 102 during operation of the semiconductor structure.

Referring to fig. 7, a first dielectric layer 115 is formed, the first dielectric layer 115 being located on a surface of the first metal layer 118 away from the substrate 100 and in a space adjacent to the first metal layer 118.

Specifically, the first dielectric layer 115 is disposed on the surface of the isolation layer 103 and the sidewall surface of the first doped region I (refer to fig. 6) for isolating the first metal layer 118 from the subsequently formed word line. The first dielectric layer 115 is a full-surface film structure for preventing electrical interference between the first metal layer 118 and the metal bit line 101 and a subsequently formed word line.

The step of forming the first dielectric layer 115 includes: forming an initial first dielectric layer on the surface of the metal bit line 101 away from the substrate 100; the initial first dielectric layer is planarized and etched back to a predetermined thickness to form a first dielectric layer 115.

The subsequent steps comprise: word lines are formed, the word lines being disposed around the channel regions. The step of forming the word line includes the steps of:

referring to fig. 8, a gate dielectric layer 114 is formed on the sidewalls of the semiconductor channel 102 in the channel region II (refer to fig. 6) and the second doped region III (refer to fig. 6).

The gate dielectric layer 114 exposes the surface of the first dielectric layer 115 that is directly beneath the semiconductor channel 102. The gate dielectric layer 114 is used to protect the semiconductor channel 102 during a subsequent annealing process to prevent a reaction between the material of the subsequent semiconductor channel 102 and the metal material.

In this embodiment, the gate dielectric layer 114 is located on the end surface of the second doping region III away from the substrate 100, and in the step of forming the second dielectric layer subsequently, the gate dielectric layer 114 located on the end surface of the second doping region III away from the substrate 100 is removed together, so as to form a metal layer on the end surface of the second doping region III away from the substrate 100 subsequently. In other embodiments, the gate dielectric layer covering the end face of the second doped region may be removed by an etching process.

Referring to fig. 9, an initial gate conductive layer 134 is formed on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II (see fig. 6), and the initial gate conductive layer 134 surrounds the channel region II, wherein the initial gate conductive layer 134 is a full-surface film structure.

Specifically, the method for forming the initial gate conductive layer 134 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic compound chemical vapor deposition. In addition, the initial gate conductive layer 134 is planarized and etched, so that the initial gate conductive layer 134 is located on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II.

Referring to fig. 10, an initial gate conductive layer 134 (refer to fig. 9) is patterned to form gate conductive layers 124 spaced apart from each other, so that the gate conductive layers 124 of different semiconductor channels 102 on the same metal bit line 101 can be connected to different potentials, thereby facilitating diversified control of the semiconductor channels. The patterning method includes photolithography.

For each gate dielectric layer 114, each gate dielectric layer 114 may be disposed around the channel region II of at least one semiconductor channel 102, and the number of the semiconductor channels 102 surrounded by each gate dielectric layer 114 may be reasonably set according to actual electrical requirements, taking 2 semiconductor channels 102 surrounded by each gate dielectric layer 114 as an example in fig. 10.

The gate dielectric layer 114 and the gate conductive layer 124 together form the word line 104, and thus the word line 104 is also disposed around the 2 semiconductor channels 102.

Referring to fig. 11, a second dielectric layer 125 is formed, wherein the second dielectric layer 125 is located in the space between the adjacent gate conductive layers 124 for preventing electrical interference between the adjacent gate conductive layers 124, and the second dielectric layer 125 is also located on the surface of the gate conductive layer 124 away from the substrate 100 for supporting other conductive structures formed subsequently on the surface of the second dielectric layer 125 away from the substrate 100 and for achieving insulation between the gate conductive layer 124 and the other conductive structures.

In addition, after the second dielectric layer 125 is formed, the second dielectric layer 125 is planarized, and the gate dielectric layer 114 on the end surface of the mask layer 109 away from the substrate 100 is removed, so that the mask layer 109 on the end surface of the second doping region III away from the substrate 100 is exposed from the second dielectric layer 125.

In this embodiment, the first dielectric layer 115 and the second dielectric layer 125 together form a dielectric layer 105, and the dielectric layer 105 is located between the metal bit line 101 and the word line 104 and is also located on a side of the word line 104 away from the substrate 100. The materials of the first dielectric layer 115 and the second dielectric layer 125 are the same, which is beneficial to reducing the types of materials required by the manufacturing process of the semiconductor structure and reducing the manufacturing cost and complexity of the semiconductor structure. In addition, the dielectric layer 105 also exposes the top surface of the mask layer 109.

Referring to fig. 11 to 12, the mask layer 109 is removed to expose the top surface of the second doped region III (refer to fig. 6), and a second metal layer is formed on the exposed top surface of the second doped region III.

The second metal layer is used for reacting with the second doping area III of the semiconductor channel to provide metal elements for forming a second metal semiconductor layer subsequently so as to reduce the resistivity of the semiconductor channel. Wherein the material of the second metal layer comprises at least one of cobalt, nickel or platinum.

The manufacturing method may further include: the first annealing treatment is performed, and the first metal layer 118 reacts with the first doping region I to transform the partial thickness of the first doping region I towards the metal bit line 101 into the first metal semiconductor layer 112, wherein the resistivity of the material of the first metal semiconductor layer 112 is smaller than that of the material of the first doping region I outside the first metal semiconductor layer 112.

The first metal layer 118 reacting with the first doped region I becomes a part of the first doped region I, and the first metal layer 118 not reacting with the first doped region I serves as the metal layer 108. It is understood that a partial thickness of the first metal layer 118 may also remain between the metal bit line 101 and the first metal semiconductor layer 112, and the remaining first metal layer 118 is used as the metal layer 108, that is, the metal layer 108 may be located on the surface of the metal bit line 101 outside the first metal semiconductor layer 112, or may be located between the first metal semiconductor layer 112 and the metal bit line 101.

In this embodiment, the first annealing treatment is performed and simultaneously the second annealing treatment is performed, the second metal layer reacts with the second doping region III to convert the exposed part of the thickness of the second doping region III into the second metal semiconductor layer 122, and the resistivity of the material of the second metal semiconductor layer 122 is smaller than that of the second doping region III outside the second metal semiconductor layer 122.

Specifically, rapid thermal annealing is adopted for annealing treatment, and the process parameters of the rapid thermal annealing comprise: in N ₂ And annealing the semiconductor structure in the atmosphere, wherein the annealing temperature is 600-850 ℃, and the annealing time is 10-60 seconds. Due to the moderate annealing temperature, it is beneficial to make the first metal layer 118 and the first doping region I sufficiently react, and make the second metal layer and the second doping region III sufficiently react to form the first metal semiconductor layer 112 and the second metal semiconductor layer 122 with relatively small resistivity. In addition, since the annealing temperature is moderate, it is favorable to avoid the diffusion of the metal elements in the first metal layer 118 and the second metal layer into the channel region II. In addition, in N ₂ The annealing process is performed in an atmosphere, which is beneficial to prevent the first metal layer 118, the second metal layer and the semiconductor channel 102 from being oxidized.

In this embodiment, the first annealing treatment and the second annealing treatment are performed simultaneously, which is beneficial to simplifying the manufacturing process of the semiconductor structure. In other embodiments, after the semiconductor channel is formed on the first metal layer, a first annealing process may be performed; and after a second metal layer is formed on the second doping area, second annealing treatment is carried out.

In addition, in some other embodiments, before forming the semiconductor channel, a first semiconductor layer may also be formed on the surface of the first metal layer, the first semiconductor layer is made of silicon or germanium, and the first semiconductor layer reacts with the first metal layer during the first annealing process to form a first metal semiconductor layer; and before forming the second metal layer, forming a second semiconductor layer on the top surface of the second doped region, wherein the second semiconductor layer is made of silicon or germanium, and the second semiconductor layer reacts with the second metal layer in the second annealing treatment process to form a second metal semiconductor layer.

Referring to fig. 1, 13 to 16, a capacitor structure 106 is formed, the capacitor structure 106 is located on a side of the second doped region III (refer to fig. 6) away from the channel region II (refer to fig. 6), and the capacitor structure 106 is in contact with the second doped region III.

The process steps for forming the capacitor structure 106 include the following steps:

referring to fig. 13, an initial insulating layer 137 is formed, and the initial insulating layer 137 covers the word line 104 and the second metal semiconductor layer 122.

Specifically, the initial insulating layer 137 is located on the surface of the second dielectric layer 125 away from the substrate 100 and the surface of the second metal semiconductor layer 122 away from the substrate 100, and the thickness of the initial insulating layer 137 is larger than that of the second dielectric layer 125, so as to facilitate the subsequent formation of the capacitor structure. The material of the initial insulating layer 137 may include at least one of borosilicate glass, borophosphosilicate glass, tetraethoxysilane, silicon oxide, or other low-dielectric-constant materials.

Referring to fig. 14, the preliminary insulating layer 137 (refer to fig. 13) is etched to form the via hole 10 exposing the second doping region III, and the remaining preliminary insulating layer 137 serves as the insulating layer 107.

Specifically, the step of forming the through-hole 10 may include: forming a patterned mask layer on the surface of the initial insulating layer 137; and etching the initial insulating layer 137 by using the patterned mask layer as a mask through a dry etching process until the second doping region III is exposed, so as to form the through hole 10.

Referring to fig. 15, a lower electrode layer 116 is formed, the lower electrode layer 116 being located at the bottom and sidewalls of the via hole 10 (refer to fig. 14).

Specifically, when the lower electrode layer 116 is formed, a portion of the lower electrode layer 116 is formed on the surface of the insulating layer 107 away from the substrate 100, and the lower electrode layer 116 on the surface of the insulating layer 107 away from the substrate 100 is removed by a planarization process or an etching process.

Referring to fig. 16, a capacitance dielectric layer 126 is formed, the capacitance dielectric layer 126 covers the surface of the lower electrode layer 116 and a portion of the surface of the insulating layer 107 near the through hole 10, and the capacitance dielectric layer 126 in the through hole 10 surrounds the groove 11.

Specifically, the step of forming the capacitor dielectric layer 126 includes: forming an initial capacitor dielectric layer, wherein the initial capacitor dielectric layer covers the surface of the lower electrode layer 116 and the surface of the insulating layer 107, and the initial capacitor dielectric layer in the through hole 10 surrounds a groove 11; the initial capacitor dielectric layer is patterned, and the initial capacitor dielectric layer covering the surface of the lower electrode layer 116 and the surface of the portion of the insulating layer 107 near the through hole 10 is remained as the capacitor dielectric layer 126.

In other embodiments, after the initial capacitor dielectric layer is formed, the upper electrode layer may be directly formed on the basis of the initial capacitor dielectric layer without performing etching processing on the initial capacitor dielectric layer.

Referring to fig. 16 and fig. 1 in combination, a first barrier layer 117 is formed, where the first barrier layer 117 is located on the surface of the insulating layer 107 not covered by the capacitor dielectric layer 126, and the top surface of the first barrier layer 117 is flush with the top surface of the capacitor dielectric layer 126, which is beneficial for providing a good supporting effect for other structures located on the top surface of the first barrier layer 117 and the top surface of the capacitor dielectric layer 126.

An upper electrode layer 136 is formed, wherein the upper electrode layer 136 is located on the surface of the capacitor dielectric layer 126 and fills the groove 11 (refer to fig. 16). In this embodiment, the lower electrode layer 116, the capacitor dielectric layer 126 and the upper electrode layer 136 together form the capacitor structure 106.

Further, a second barrier layer 127 is formed, the second barrier layer 127 being located on a surface of the upper electrode layer 136 and a surface of the first barrier layer 117 not covered by the upper electrode layer 136, for preventing electrical interference between the upper electrode layer 136 and an external conductive structure. Wherein the material of the second barrier layer 127 is at least one of silicon oxide, silicon nitride, silicon oxycarbonitride, or silicon oxynitride, and in this embodiment, the material of the second barrier layer 127 is the same as the material of the first barrier layer 117. In other embodiments, the material of the second barrier layer may also be different from the material of the first barrier layer.

In other embodiments, in the process step of forming the lower electrode layer, the lower electrode layer filling the through hole may also be formed, and accordingly, the lower electrode layer is in a columnar structure.

In summary, the channel region II of the semiconductor channel 102 is vertically disposed on the metal bit line 101, on one hand, the electrical connection between the semiconductor channel 102 and the metal bit line 101 and the capacitor structure 106 can be achieved without an additional electrical connection structure, which is beneficial to reducing the complexity of the semiconductor structure; on the other hand, it is beneficial to save the layout space of the semiconductor channel 102 in the direction parallel to the surface of the metal bit line 101, thereby increasing the integration density of the semiconductor structure in the horizontal direction. In addition, the first metal layer 118 in contact with the first doped region I and the second metal layer in contact with the second doped region III are formed, and through the first annealing treatment and the second annealing treatment, a part of the first doped region I is converted into the first metal semiconductor layer 112, a part of the second doped region III is converted into the second metal semiconductor layer 122, and the resistivity of the first doped region I and the second doped region III is reduced, so that power consumption required for transmitting an electric signal between the semiconductor channel 102 and the metal bit line 101 and the capacitor structure 106 is reduced.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

the device comprises a substrate, a first substrate and a second substrate, wherein a metal bit line is arranged in the substrate, and the surface of the metal bit line is exposed out of the substrate;

the semiconductor channel is positioned on part of the surface of the metal bit line, and comprises a first doping region, a channel region and a second doping region which are sequentially arranged in the direction pointing to the metal bit line along the substrate, wherein the first doping region is electrically connected with the metal bit line;

a word line disposed around the channel region;

the dielectric layer is positioned between the metal bit line and the word line and is also positioned on one side of the word line, which is far away from the substrate;

and the capacitor structure is positioned on one side of the second doped region far away from the channel region and is in contact with the second doped region.

2. The semiconductor structure of claim 1, wherein the substrate comprises:

the logic circuit structure layer is provided with a plurality of logic circuits;

the interlayer dielectric layer is positioned on the surface of the logic circuit structure layer, and the metal bit line is positioned on the partial surface of the interlayer dielectric layer far away from the logic circuit structure layer;

and the isolation layer is positioned on the surface of the interlayer dielectric layer exposed out of the metal bit line and covers the side wall of the metal bit line.

3. The semiconductor structure of claim 2, wherein the interlevel dielectric layer is integral with the isolation layer.

4. The semiconductor structure of claim 1, wherein the material of the semiconductor channel comprises at least one or more of IGZO, IWO, or ITO.

5. The semiconductor structure of claim 1, in which the first doped region comprises: the first metal semiconductor layer is in contact with the metal bit line, and the resistivity of the first metal semiconductor layer is smaller than that of the first doping region except the first metal semiconductor layer.

6. The semiconductor structure of claim 5, further comprising: and the metal layer is positioned on the surface of the metal bit line which is not covered by the semiconductor channel, and is formed by metal elements in the first metal semiconductor layer.

7. The semiconductor structure of claim 1, in which the second doped region comprises: the second metal semiconductor layer is in contact with the capacitor structure, and the resistivity of the material of the second metal semiconductor layer is smaller than that of the second doped region except the second metal semiconductor layer.

8. The semiconductor structure of claim 7, wherein the metal element in the second metal semiconductor layer comprises at least one of cobalt, nickel, or platinum.

9. The semiconductor structure according to claim 7, wherein a semiconductor element in the second metal semiconductor layer is the same as a semiconductor element in the second doped region other than the second metal semiconductor layer; or the semiconductor element in the second metal semiconductor layer is silicon or germanium.

10. The semiconductor structure of claim 1, wherein the semiconductor channel constitutes a device that is a junction-less transistor.

11. The semiconductor structure of claim 1, wherein the word line comprises:

the gate dielectric layer is arranged around the channel region, is positioned on the surface of the side wall of the semiconductor channel of the channel region, and is also positioned on the surface of the side wall of the semiconductor channel of the second doped region;

and the grid conducting layer is arranged around the channel region and is positioned on the surface of the side wall of the grid dielectric layer corresponding to the channel region.

12. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a plurality of the word lines that are discrete from one another; the dielectric layer includes:

the first dielectric layer is positioned between the metal bit line and the word line, positioned on the surface of the substrate and the surface of the bit line exposed by the semiconductor channel, and the adjacent word line exposes part of the surface of the first dielectric layer;

and the second dielectric layer is positioned on the surface of the word line and the surface of the exposed first dielectric layer, surrounds the semiconductor channel of the second doped region and exposes the top surface of the second doped region.

13. The semiconductor structure of claim 1, further comprising:

the insulating layer is positioned on one side, far away from the substrate, of the second doping region, a through hole penetrating through the insulating layer is formed in the insulating layer, and the top surface of the second doping region is exposed out of the through hole;

the capacitor structure includes:

the lower electrode layer is positioned at the bottom and the side wall of the through hole;

the capacitor dielectric layer covers the surface of the lower electrode layer;

and the upper electrode layer covers the surface of the capacitor dielectric layer and is filled in the through hole.

14. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein a metal bit line is arranged in the substrate, and the surface of the metal bit line is exposed out of the substrate;

forming a semiconductor channel, wherein the semiconductor channel is positioned on part of the surface of the metal bit line, and comprises a first doped region, a channel region and a second doped region which are sequentially arranged in a direction pointing to the metal bit line along the substrate, and the first doped region is electrically connected with the metal bit line;

forming a word line disposed around the channel region;

forming a dielectric layer, wherein the dielectric layer is positioned between the metal bit line and the word line and is also positioned on one side of the word line, which is far away from the substrate;

and forming a capacitor structure, wherein the capacitor structure is positioned on one side of the second doped region far away from the channel region and is in contact with the second doped region.

15. The method of manufacturing of claim 14, wherein the process steps of forming the substrate and the metal bit line comprise:

providing a logic circuit structure layer and an interlayer dielectric layer which are arranged in a stacked mode;

forming a plurality of mutually-separated metal bit lines on the surface of the interlayer dielectric layer, wherein the metal bit lines are exposed out of the partial surface of the interlayer dielectric layer;

and forming an isolation layer, wherein the isolation layer is positioned on the surface of the interlayer dielectric layer exposed out of the metal bit line and covers the side wall of the metal bit line.

16. The method of manufacturing of claim 14, further comprising, prior to forming the semiconductor channel:

forming a first metal layer on the surface of the metal bit line;

after forming the semiconductor channel, further comprising:

and carrying out first annealing treatment, wherein the first metal layer reacts with the first doping region to convert the first doping region with partial thickness towards the metal bit line into a first metal semiconductor layer, and the resistivity of the material of the first metal semiconductor layer is smaller than that of the material of the first doping region except the first metal semiconductor layer.

17. The method of manufacturing of claim 14, wherein the process step of forming the semiconductor channel comprises:

forming an initial channel layer, wherein the initial channel layer is positioned on the metal bit line and the substrate;

forming a patterned mask layer on the surface of the initial channel layer;

and carrying out patterning treatment on the initial channel layer by taking the mask layer as a mask to form the semiconductor channel.

18. The method of claim 17, wherein the dielectric layer exposes a top surface of the masking layer; after the dielectric layer is formed and before the capacitor structure is formed, the method further includes:

removing the mask layer to expose the top surface of the second doped region;

forming a second metal layer on the exposed top surface of the second doped region;

and performing second annealing treatment, wherein the second metal layer reacts with the second doping region to convert the exposed part of the thickness of the second doping region into a second metal semiconductor layer, and the resistivity of the material of the second metal semiconductor layer is smaller than that of the second doping region except the second metal semiconductor layer.

19. The manufacturing method according to claim 18, wherein the second annealing treatment is performed using rapid thermal annealing; the technological parameters of the rapid thermal annealing comprise: at N ₂ And carrying out annealing treatment in the atmosphere, wherein the annealing temperature is 600-850 ℃, and the annealing time is 10-60 seconds.

20. The method of manufacturing of claim 14, wherein the process step of forming the word line comprises:

forming a gate dielectric layer on the side wall of the semiconductor channel of the channel region and the second doping region;

and forming a gate conducting layer on the surface of the gate dielectric layer in the channel region, wherein the gate conducting layer surrounds the channel region.