CN115224032A - Semiconductor structure and method of making the same - Google Patents

Abstract

An embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: the substrate is provided with a metal bit line, and the surface of the metal bit line is exposed out of the substrate; the semiconductor channel is positioned on the partial surface of the metal bit line, and comprises a first doping region, a channel region and a second doping region which are sequentially arranged in the direction pointing to the metal bit line along the substrate, wherein the first doping region is contacted with the metal bit line; word lines disposed around the channel region; the dielectric layer is positioned between the metal bit line and the word line and is also positioned on one side of the word line far away from the substrate; and the capacitor structure is positioned on one side of the second doped region far away from the channel region and is in contact with the second doped region. The embodiment of the invention is beneficial to improving the integration density of the semiconductor structure and reducing the power consumption of the semiconductor structure during working.

Description

Semiconductor structure and method of making the same

technical field

Embodiments of the present invention relate to the technical field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.

Background technique

As the demand for semiconductor devices to have high performance and low cost increases, so does the demand for high integration density and low power consumption of semiconductor devices.

However, the increase in the integration density of semiconductor devices and the reduction in power consumption during operation of the semiconductor devices have put forward higher requirements on their manufacturing processes. The integration density of two-dimensional (2D) or planar semiconductor devices is mainly determined by the area occupied by individual functional devices (eg, memory cells) that make up the semiconductor device. The area occupied by a single functional device depends to a large extent on the dimensional parameters of the electrical connection structures used to define the single functional device and the interconnections between the functional devices. In order to provide individual functional devices and electrical connection structures with finer dimensions, both the development cost and the use cost for forming the individual functional devices and electrical connection structures are high. In order to reduce the power consumption of the semiconductor device during operation, higher requirements are also placed on the electrical connection between the individual functional devices in the semiconductor device.

SUMMARY OF THE INVENTION

The technical problem solved by the embodiments of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are beneficial to improve the integration density of the semiconductor structure and reduce the power consumption of the semiconductor structure during operation.

In order to solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate having a metal bit line in the substrate, and the substrate exposes the surface of the metal bit line; a semiconductor channel, the semiconductor channel is located in the A part of the surface of the metal bit line, along the direction of the substrate to the metal bit line, the semiconductor channel includes a first doped region, a channel region and a second doped region arranged in sequence, the first doped region a doped region is electrically connected to the metal bit line; a word line, the word line is arranged around the channel region; a dielectric layer, the dielectric layer is located between the metal bit line and the word line, and also is located on the side of the word line away from the substrate; a capacitor structure, the capacitor structure is located on the side of the second doped region away from the channel region, and the capacitor structure is connected to the second doped region area contact.

Correspondingly, an embodiment of the present invention also provides a method for manufacturing a semiconductor structure, including: providing a substrate with a metal bit line in the substrate, and the substrate exposes the surface of the metal bit line; forming a semiconductor channel, the semiconductor A channel is located on a part of the surface of the metal bit line, and in a direction along the substrate to the metal bit line, the semiconductor channel includes a first doped region, a channel region and a second doped region arranged in sequence , the first doped region is electrically connected to the metal bit line; a word line is formed, and the word line is arranged around the channel region; a dielectric layer is formed, and the dielectric layer is located between the metal bit line and the between the word lines, and also on the side of the word line away from the substrate; forming a capacitor structure, the capacitor structure is located on the side of the second doped region away from the channel region, and the capacitor A structure is in contact with the second doped region.

Compared with the prior art, the technical solutions provided by the embodiments of the present invention have the following advantages:

In the above technical solution, the channel region of the semiconductor channel is vertically arranged on the surface of the metal bit line, that is, the extension direction of the channel region is perpendicular to the surface of the metal bit line, which is conducive to saving semiconductors without reducing the size of the semiconductor channel. The layout space of the channel in the direction parallel to the surface of the metal bit line (usually the horizontal direction), thereby improving the integration density of the semiconductor structure in the horizontal direction. Further, the semiconductor channel is located on a part of the surface of the metal bit line and is in contact with the metal bit line, and the second doped region is in contact with the capacitor structure, so that no additional electrical connection structure is required to realize the connection between the semiconductor channel and the metal bit line and the capacitor structure. The electrical connection is beneficial to reduce the manufacturing cost of the semiconductor structure and reduce the power consumption required for the transmission of electrical signals between the semiconductor channel and the metal bit line and the capacitor structure. In addition, the metal bit line has low resistivity and excellent electrical conductivity, which is conducive to further reducing the energy consumption of the semiconductor structure during operation; and the metal bit line is located in the substrate, which is conducive to reducing the overall thickness of the semiconductor structure, so as to further reduce the overall semiconductor structure. size.

In addition, the device composed of the semiconductor channel is a junctionless transistor, and the junctionless transistor has no PN junction, the preparation process is simple, and the performance is excellent, which enhances the reliability of the device, especially the resistance to hot carrier injection effect and noise tolerance, which is conducive to further improvement. Electrical properties of semiconductor structures.

Description of drawings

One or more embodiments are exemplified by the pictures in the accompanying drawings, which do not constitute a scale limitation unless otherwise stated.

FIG. 1 is a schematic cross-sectional structure diagram corresponding to a semiconductor structure provided by an embodiment of the present invention;

2 to 16 are schematic cross-sectional structural diagrams corresponding to each step in a method for fabricating a semiconductor structure according to another embodiment of the present invention.

Detailed ways

It can be known from the background art that the integration density of the semiconductor device in the prior art needs to be improved, and the power consumption of the semiconductor device during operation needs to be reduced.

The analysis shows that the integration density of two-dimensional (2D) or planar semiconductor devices is greatly affected by the horizontal area occupied by a single functional device, and by the arrangement of multiple functional devices and the connection between functional devices. Impact. Therefore, in order to improve the integration density of semiconductor devices, measures are often taken to reduce the size of a single functional device or reduce the interval between adjacent functional devices. However, the development and use costs of manufacturing equipment for defining the dimensional parameters of the individual functional devices and the electrical connection structures interconnecting the functional devices are high. In addition, the power consumption during operation of the semiconductor device is affected by the connection method between the functional devices. The longer the length of the connection structure connecting the functional devices, the greater the power consumption during operation of the semiconductor device.

It can be seen that the significant increase in the integration density of semiconductor devices is achieved under the condition of increasing their manufacturing costs. Therefore, in order to increase the integration density of semiconductor devices, it is necessary to develop three-dimensional (3D) semiconductor devices, that is, to reduce the footprint of a single functional device in a semiconductor device in a horizontal direction. In order to reduce the power consumption of the semiconductor device during operation, it is necessary to improve the connection between functional devices in the semiconductor device.

To solve the above problems, embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, by changing the arrangement of the semiconductor channel on the metal bit line, that is, the extending direction of the channel region is perpendicular to the surface of the metal bit line, on the one hand, the first doped region of the semiconductor channel is connected to the metal bit line. Contact and electrical connection, the second doped region is in contact and electrical connection with the capacitor structure, no additional electrical connection structure is required to realize the electrical connection between the semiconductor channel and the metal bit line and the capacitor structure, which is beneficial to reduce the manufacturing cost of the semiconductor structure and the electrical connection. The power consumption required for signal transmission between the semiconductor channel and the metal bit line and the capacitor structure; on the other hand, without reducing the size of the semiconductor channel, it is beneficial to save the semiconductor channel in the direction parallel to the surface of the metal bit line Therefore, the integration density of the semiconductor structure in the horizontal direction is improved. In addition, the low resistivity of the metal bit line is beneficial to further reduce the energy consumption of the semiconductor structure during operation; and the metal bit line is located in the substrate, which is beneficial to reduce the overall thickness of the semiconductor structure and further reduce the overall size of the semiconductor structure.

In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, each embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can appreciate that, in various embodiments of the present invention, many technical details are provided for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be realized.

An embodiment of the present invention provides a semiconductor structure, and the semiconductor structure provided by an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional structure diagram corresponding to a semiconductor structure provided by an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor structure includes: a substrate 100 having metal bit lines 101 in the substrate 100 and exposing the surface of the metal bit lines 101 from the substrate 100 ; In the direction of the metal bit line 101, the semiconductor channel 102 includes a first doping region I, a channel region II and a second doping region III arranged in sequence, and the first doping region I is in contact with the metal bit line 101; word Line 104, word line 104 is arranged around the channel region; dielectric layer 105, dielectric layer 105 is located between metal bit line 101 and word line 104, and is also located on the side of word line 104 away from substrate 100; capacitor structure 106, capacitor structure 106 is located on the side of the second doped region III away from the channel region II, and the capacitor structure 106 is in contact with the second doped region III.

Since the semiconductor structure includes a vertical gate-all-around (GAA, Gate-All-Around) transistor, and the metal bit line 101 is located between the substrate 100 and the gate-all-around transistor, a 3D stacked memory device can be formed, which is beneficial to improve the The integration density of semiconductor structures.

The semiconductor structure will be described in more detail below with reference to FIG. 1 .

In this embodiment, the substrate 100 may include: a logic circuit structure layer 110 having several logic circuits; an interlayer dielectric layer 120, the interlayer dielectric layer 120 is located on the surface of the logic circuit structure layer 110, and the metal bit lines 101 are located in the interlayer dielectric layer 120 is away from a part of the surface of the logic circuit structure layer 110 ; the isolation layer 103 is located on the surface of the interlayer dielectric layer 120 exposed by the metal bit line 101 and covers the sidewall of the metal bit line 101 . For convenience of illustration, 103 is not marked in brackets corresponding to 100 in FIG. 1 .

Specifically, the logic circuit structure layer 110 may be a stacked structure. A part of the surface of the interlayer dielectric layer 120 away from the logic circuit structure layer 110 may have a plurality of metal bit lines 101 arranged at intervals, and each metal bit line 101 may be electrically connected to at least one first doped region I, as shown in FIG. 1 . Taking each metal bit line 101 in contact with two first doped regions I as an example, the number of first doped regions I that are in contact and electrically connected to each metal bit line 101 can be reasonably set according to actual electrical requirements . The top surface of the metal bit line 101 can be flush with the top surface of the isolation layer 103 , which is beneficial to provide good support for other structures located on the top surface of the metal bit line 101 and the top surface of the isolation layer 103 .

The interlayer dielectric layer 120 is used to achieve insulation between the logic circuit structure layer 110 and the metal bit lines 101 , and the interlayer dielectric layer 120 is beneficial to prevent leakage between adjacent metal bit lines 101 . The material of the interlayer dielectric layer 120 includes at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon oxycarbonitride.

The isolation layer 103 is located between adjacent metal bit lines 101 to achieve insulation between adjacent metal bit lines 101 . The material of the isolation layer 103 includes at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the interlayer dielectric layer 120 and the isolation layer 103 have an integrated structure, so as to improve the interface state defects between the interlayer dielectric layer 120 and the isolation layer 103 , improve the performance of the semiconductor structure, and the material of the interlayer dielectric layer 120 The material of the isolation layer 103 is the same, so it is beneficial to reduce the manufacturing process steps of the semiconductor structure and reduce the manufacturing cost and complexity of the semiconductor structure. In other embodiments, the interlayer dielectric layer and the isolation layer may have a layered structure, and the material of the interlayer dielectric layer and the material of the isolation layer may be different.

It can be understood that, in other embodiments, the substrate may also include: a substrate, where metal bit lines are located on the substrate, and adjacent metal bit lines expose part of the surface of the substrate; an isolation layer, where the isolation layer is located on adjacent metal bit lines The surface of the substrate between bit lines used to isolate adjacent metal bit lines. In addition, the substrate may also have a groove, the position of the groove is directly opposite to the area between adjacent metal bit lines, and the spacer layer fills the groove. It can also be understood that the substrate may be an insulating substrate, or may be a stacked structure of a semiconductor substrate and an interlayer dielectric layer.

The material of the metal bit line 101 is metal, and the advantages of such setting include: on the one hand, the resistivity of the metal bit line 101 made of metal material is generally small, which is beneficial to reduce the resistance of the metal bit line 101 and improve the electrical conductivity in the metal bit line 101 The transmission rate of the signal, the parasitic capacitance of the metal bit line 101 is reduced, and the heat loss is reduced to reduce power consumption; on the other hand, the semiconductor structure may also include a circuit structure, and the circuit structure has a metal conductive layer for realizing electrical connection, For example, the M0 layer, the M1 layer, the M2 layer, etc., which are often called by those skilled in the art, the process steps of the metal conductive layer can be used to form the metal bit line 101 while the metal conductive layer is formed. In this way, the manufacturing process steps of the semiconductor structure can be saved. Reduce the cost of semiconductor structures.

The material of the metal bit line 101 may be a single metal, a metal compound or an alloy. The single metal can be copper, aluminum, tungsten, gold or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold or silver. In addition, the material of the metal bit line 101 may also be at least one of nickel, cobalt or platinum.

In some embodiments, the material of the metal bit line 101 is copper.

The semiconductor structure may include a plurality of metal bit lines 101 arranged at intervals, and each metal bit line 101 extends along the first direction; each metal bit line 101 may be electrically connected to at least two semiconductor channels 102 .

The material of the semiconductor channel 102 includes at least one of IGZO (Indium Gallium ZincOxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide). The semiconductor channel 102 is composed of When the above materials are composed, the carrier mobility of the semiconductor channel 102 can be improved, so that the semiconductor channel 102 can transmit electrical signals more efficiently.

In one example, the material of the semiconductor channel 102 is IGZO, and the carrier mobility of IGZO is 20-50 times that of polysilicon, which is beneficial to improve the carrier mobility of the channel region II in the semiconductor channel 102 Therefore, it is beneficial to reduce the leakage current of the semiconductor structure during operation, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure. In addition, the retention time of the memory cells configured with full surround gate transistors formed by the IGZO semiconductor channel 102 can exceed 400s, which is beneficial to reduce the refresh rate and power consumption of the memory.

In this embodiment, the semiconductor channel 102 has a cylindrical structure, and the side surface of the semiconductor channel 102 is a smooth transition surface, which is beneficial to avoid tip discharge or leakage of the semiconductor channel 102 and further improve the electrical performance of the semiconductor structure. It should be noted that, in other embodiments, the semiconductor channel may also be an elliptical columnar structure, a square columnar structure, or other irregular structures. It can be understood that when the semiconductor channel structure is a square columnar structure, the corners formed by the adjacent surfaces of the sidewalls of the square columnar structure can be rounded corners, which can also avoid the problem of tip discharge, and the square columnar structure can be a cube columnar structure or a cuboid. columnar structure.

The first doped region I constitutes one of the source or the drain of the transistor device, and the second doped region III constitutes the other of the source or the drain of the transistor device. The semiconductor elements in the first doping region I, the channel region II and the second doping region III are the same, that is, the first doping region I, the channel region II and the second doping region III have an integrated structure, which is conducive to improving the The interface state defects between the first doping region I and the channel region II are improved, and the interface state defects between the channel region II and the second doping region III are improved to improve the performance of the semiconductor structure. It can be understood that, in other embodiments, the semiconductor channel may also have a three-layer structure, and each layer structure corresponds to a first doped region, a channel region, and a third doped region.

The first doped region I may include: a first metal semiconductor layer 112, the first metal semiconductor layer 112 is in contact with the metal bit line 101, and the resistivity of the first metal semiconductor layer 112 is smaller than that outside the first metal semiconductor layer 112 The resistivity of the first doped region I. In this way, it is beneficial to reduce the resistivity of the first doped region I, and the first metal semiconductor layer 112 forms an ohmic contact with the first doped region I other than the first metal semiconductor layer 112 to avoid direct contact between the metal bit line 101 and the semiconductor material. The Schottky barrier contact formed by the contact and the ohmic contact are beneficial to reduce the contact resistance between the first doping region I and the metal bit line 101, thereby reducing the energy consumption of the semiconductor structure during operation, and improving the RC delay effect, so that the Improve the electrical properties of semiconductor structures. It can be understood that, in other embodiments, the semiconductor material of the first doped region may also be in direct contact with the metal bit line, that is, the first doped region does not include the first metal semiconductor layer.

Specifically, the metal element in the first metal semiconductor layer 112 includes at least one of cobalt, nickel or platinum. Taking the material of the semiconductor channel 102 as IGZO as an example, correspondingly, the material of the first metal semiconductor layer 112 may be IGZO containing nickel, IGZO containing cobalt, IGZO containing cobalt nickel, or IGZO containing platinum. In addition, the first metal semiconductor layer 112 may also be doped with nitrogen.

The semiconductor elements in the first metal-semiconductor layer 112 are the same as the semiconductor elements in the first doped region I outside the first metal-semiconductor layer 112 , that is, the first doped region I has an integral structure, and the first metal-semiconductor layer 112 is a part of the first doped region I, which is beneficial to improve the interface state defect between the first metal semiconductor layer 112 and the first doped region I except the first metal semiconductor layer 112, and improve the performance of the semiconductor structure. It should be noted that, in other embodiments, the semiconductor element in the first metal-semiconductor layer may also be different from the semiconductor element in the first doped region other than the first metal-semiconductor layer, for example, in the first metal-semiconductor layer The semiconductor element may be silicon or germanium, and correspondingly, the first doped region is a double-layer structure including a first metal semiconductor layer.

In some embodiments, the semiconductor channel 102 is in contact with the metal bit line 101 , that is, the first doped region I is located on the surface of the metal bit line 101 . Further, the semiconductor structure may further include: a metal layer 108 located on the surface of the metal bit line 101 not covered by the semiconductor channel 102 , and the metal layer 108 is composed of metal elements in the first metal semiconductor layer 112 . It can be understood that the metal layer 108 is formed at the same time in the process step of forming the first metal semiconductor layer 112 , and the material of the metal layer 108 can be at least one of cobalt, nickel or platinum.

In addition, in some other embodiments, the material of the metal bit line 101 is at least one of nickel, cobalt or platinum, then correspondingly, in the manufacturing process steps of the semiconductor structure, the material in contact with the first doping region I Part of the metal bit line 101 reacts with the first doping region I to form the first metal semiconductor layer 112. In this way, the metal bit line 101 and the first metal semiconductor layer 112 have an integrated structure, which is beneficial to further reduce the metal bit line. Contact resistance between the line 101 and the first metal semiconductor layer 112 . That is, the metal bit line 101 may provide a metal element for forming the first metal semiconductor layer 112 .

The second doped region III may include: a second metal-semiconductor layer 122 , the second metal-semiconductor layer 122 is in contact with the capacitor structure, and the resistivity of the material of the second metal-semiconductor layer 122 is smaller than that of the material outside the second metal-semiconductor layer 122 The resistivity of the second doped region III. In this way, it is beneficial to reduce the resistivity of the second doped region III; and an ohmic contact is formed between the second metal semiconductor layer 122 and the capacitor structure, which is beneficial to reduce the contact resistance between the second doped region III and the capacitor structure, thereby The power consumption of the semiconductor structure during operation is reduced, so as to improve the electrical performance of the semiconductor structure.

The metal element in the second metal semiconductor layer 122 includes at least one of cobalt, nickel, or platinum. In this embodiment, the metal element in the first metal-semiconductor layer 112 and the metal element in the second metal-semiconductor layer 122 may be the same. In other embodiments, the metal element in the first metal-semiconductor layer and the metal element in the second metal-semiconductor layer may also be different.

In addition, the semiconductor elements in the second metal-semiconductor layer 122 are the same as the semiconductor elements in the second doped region III outside the second metal-semiconductor layer 122 , that is, the second doped region III has an integral structure, and the second metal The semiconductor layer 122 is a part of the second doped region III, which is beneficial to improve the interface state defects between the second metal semiconductor layer 122 and the second doped region III except the second metal semiconductor layer 122, and improve the semiconductor structure. performance. It should be noted that, in other embodiments, the semiconductor element in the second metal-semiconductor layer may also be different from the semiconductor element in the second doped region other than the second metal-semiconductor layer, for example, in the second metal-semiconductor layer The semiconductor element may be silicon or germanium, and correspondingly, the second doped region is a double-layer structure including a second metal-semiconductor layer.

Taking silicon as the semiconductor element as an example, the second metal semiconductor layer 122 includes at least one of cobalt silicide, nickel silicide, or platinum silicide. In addition, the second metal semiconductor layer 122 may also be doped with nitrogen.

The device formed by the semiconductor channel 102 may be a Junctionless Transistor, that is, the doping ions in the first doping region I, the channel region II and the second doping region III are of the same type, for example, the doping ions are all of the same type. Either the N-type ions are all P-type ions, and further, the doping ions in the first doping region I, the channel region II and the second doping region III may be the same. Wherein, "junctionless" here refers to no PN junction, that is, there is no PN junction in the transistor formed by the semiconductor channel 102. Such advantages include: on the one hand, there is no need for the first doping region I and the second doping region. III is additionally doped, so as to avoid the problem that the doping process of the first doping region I and the second doping region III is difficult to control, especially as the transistor size is further reduced, if the first doping region is additionally doped I and the second doping region III are doped, and the doping concentration is more difficult to control; on the other hand, because the device is a junctionless transistor, it is beneficial to avoid the use of ultra-steep source-drain concentration gradient doping process, and fabricate in the nanoscale range The phenomenon of ultra-steep PN junction can avoid the threshold voltage drift and leakage current increase caused by doping mutation, and it is also beneficial to suppress the short channel effect. The integration density and electrical performance of the semiconductor structure are further improved. It can be understood that the additional doping here refers to the doping performed in order to make the doping ion type of the first doping region I and the second doping region III different from the doping ion type of the channel region .

Further, the concentration of the doping ions in the first doping region I and the doping ion concentration in the second doping region III may both be greater than the doping concentration of the doping ions in the channel region II. Doping ions are N-type ions or P-type ions, specifically, N-type ions are at least one of arsenic ions, phosphorus ions or antimony ions; P-type ions are at least one of boron ions, indium ions or gallium ions .

The word line 104 includes: a gate dielectric layer 114, the gate dielectric layer 114 is arranged around the channel region II, and is located on the sidewall surface of the semiconductor channel 102 in the channel region II; a gate conductive layer 124, the gate conductive layer 124 surrounds the channel region II is disposed on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II.

The gate dielectric layer 114 may also be disposed around the second doped region III, that is, located on the sidewall surface of the semiconductor channel 102 in the second doped region III. In this way, the gate dielectric layer 114 is used to connect the gate conductive layer 124 with the semiconductor Channel 102 is isolated. In addition, the gate dielectric layer 114 located on the sidewall surface of the semiconductor channel 102 of the second doped region III can protect the surface of the second doped region III, so as to avoid the surface of the second doped region III during the manufacturing process. The resulting process damage is beneficial to further improve the electrical properties of the semiconductor structure. It can be understood that, in other embodiments, the gate dielectric layer may only be located on the sidewall surface of the semiconductor channel in the channel region.

The material of the gate dielectric layer 114 includes at least one of silicon oxide, silicon nitride or silicon oxynitride, and the material of the gate conductive layer 124 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten or aluminum .

In this embodiment, the semiconductor structure may include a plurality of word lines 104 arranged at intervals, and each word line 104 extends along a second direction, and the second direction is different from the first direction. For example, the first direction may be different from the second direction. vertical. In addition, for each word line 104, each word line 104 may be disposed around the channel region II of at least one semiconductor channel 102. In FIG. 1, each word line 104 is used as an example to surround two semiconductor channels 102. According to actual electrical requirements, the number of semiconductor channels 102 surrounded by each word line 104 is reasonably set.

The dielectric layer 105 is used to isolate the metal layer 108 and the word line 104 to isolate the metal bit line 101 and the word line 104 , and also to isolate the adjacent word line 104 and the adjacent metal layer 108 . That is, the dielectric layer 105 is located between the metal layer 108 and the word line 104 , and is also located in the interval between adjacent word lines 104 and in the interval between adjacent metal layers 108 .

The dielectric layer 105 may include: a first dielectric layer 115 , the first dielectric layer 115 is located between the metal layer 108 and the word line 104 and in the space between the adjacent metal layers 108 , so that the metal layer 108 is insulated from the word line 104 , to prevent the electrical interference between the metal layer 108 and the word line 104, to further prevent the electrical interference between the metal bit line 101 and the word line 104; the second dielectric layer 125, the second dielectric layer 125 is located in the adjacent word line 104 Between and in contact with the first dielectric layer 115 , used to achieve insulation between adjacent word lines 104 and prevent electrical interference between adjacent word lines 104 ; the second dielectric layer 125 is also located on the word lines 104 away from the substrate 100 The surface of the second dielectric layer 125 is used to support other conductive structures on the surface of the second dielectric layer 125 away from the substrate 100 , and to achieve insulation between the word lines 104 and other conductive structures.

The top surface of the second dielectric layer 125 may be flush with the top surface of the second doped region III, which is beneficial to provide good support for other structures located on the top surface of the second dielectric layer 125 and the top surface of the second doped region III.

In this embodiment, the material of the first dielectric layer 115 and the material of the second dielectric layer 125 are the same, and both may be at least one of silicon oxide, silicon nitride, silicon oxycarbonitride or silicon oxynitride. In other embodiments, the material of the first dielectric layer and the material of the second dielectric layer may also be different.

It can be understood that, in other embodiments, the dielectric layer may also be other stacked film layer structures, and the specific structure of the stacked film layer structure is related to the manufacturing process steps, as long as the dielectric layer can serve the purpose of isolation.

Further, the semiconductor structure further includes: an insulating layer 107, the insulating layer 107 is located on the side of the second doped region III away from the substrate 100, and the insulating layer 107 has a through hole 10 penetrating the insulating layer 107, and the through hole 10 exposes the second doped region III. Top surface of doped region III.

The capacitor structure 106 is located in the through hole 10 , and the insulating layer 107 is used to support the capacitor structure 106 to prevent the capacitor structure 106 from collapsing and to isolate the lower electrode layer 116 in the adjacent capacitor structure 106 . The material of the insulating layer 107 includes at least one of silicon nitride, silicon oxynitride, silicon oxycarbonitride or silicon oxide.

It can be understood that, in other embodiments, the insulating layer can also be a stacked film layer structure, and the specific structure of the stacked film layer structure is related to the manufacturing process steps, as long as the insulating layer can serve the purpose of support and isolation.

Specifically, the capacitor structure 106 includes: a lower electrode layer 116, the lower electrode layer 116 is located at the bottom and sidewall of the through hole 10; a capacitor dielectric layer 126, the capacitor dielectric layer 126 covers the surface of the lower electrode layer 116; The electrode layer 136 covers the surface of the capacitor dielectric layer 126 and fills the through hole 10 .

In this embodiment, the lower electrode layers 116 located in the adjacent through holes 10 are separated from each other, and the capacitive dielectric layers 126 located on the surface of the adjacent lower electrode layers 116 are also spaced from each other, and the capacitive dielectric layers 126 are also located on the insulating layer. 107 is close to a part of the surface of the through hole 10 , and the surface of the insulating layer 107 not covered by the capacitive dielectric layer 126 is covered with the first barrier layer 117 . In other embodiments, the capacitive dielectric layer may also cover the entire surface of the insulating layer.

The upper electrode layer 136 is also located on the surface of the first barrier layer 117 between the adjacent capacitor dielectric layers 126 , that is, the upper electrode layers 136 filled with the adjacent through holes 10 are in contact and connected to each other, and the upper electrode layers 136 have an integrated structure. In other embodiments, the upper electrode layers located in the adjacent through holes may have a space between them, so that the upper electrode layers in the adjacent capacitor structures can be connected to different potentials, which is beneficial to realize the diversification of the adjacent capacitor structures control.

Wherein, the material of the lower electrode layer 116 and the material of the upper electrode layer 136 may be the same, and the material of the lower electrode layer 116 and the material of the upper electrode layer 136 may be platinum nickel oxide, titanium, tantalum, cobalt, polysilicon, copper, tungsten, At least one of tantalum nitride, titanium nitride or ruthenium. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer may also be different.

The material of the capacitor dielectric layer 126 includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate. .

In this embodiment, the semiconductor channel 102 is a columnar structure, and one end surface of the columnar structure, that is, the end surface of the first doped region I is in electrical contact with the metal bit line 101, and the part of the first doped region I close to the metal bit line 101 The sidewall is in contact with the metal layer 108 , and the other end surface of the columnar structure, that is, the second doped region III is in contact with the capacitor structure 106 , more specifically, the second doped region III is in contact with the lower electrode layer 116 and electrically connected.

It should be noted that, in other embodiments, the capacitor structure may also be: the lower electrode layer fills the through holes in the insulating layer; the capacitor dielectric layer covers the surface of the lower electrode layer, and the upper electrode layer covers the capacitor dielectric layer away from the lower electrode the surface of the layer.

In addition, the semiconductor structure further includes: a second barrier layer 127 located on the surface of the upper electrode layer 136 and the surface of the first barrier layer 117 not covered by the upper electrode layer 136, for preventing the connection between the upper electrode layer 136 and the external conductive structure electrical interference.

The material of the first barrier layer 117 and the material of the second barrier layer 127 are the same as the material of the insulating layer 107 , which is beneficial to reduce the types of materials required in the fabrication process of the semiconductor structure and reduce the fabrication cost and complexity of the semiconductor structure. In other embodiments, the material of the first barrier layer and the material of the second barrier layer may also be different from the material of the insulating layer.

To sum up, the channel region II of the semiconductor channel 102 is vertically disposed on the metal bit line 101 . On the one hand, the electrical connection between the semiconductor channel 102 and the metal bit line 101 and the capacitor structure 106 can be realized without an additional electrical connection structure. The connection is beneficial to reduce the complexity of the semiconductor structure and reduce the power consumption required for the transmission of electrical signals between the semiconductor channel 102 and the metal bit line 101 and the capacitor structure 106; On the premise of shrinking, it is beneficial to save the layout space of the semiconductor channel 102 in the direction parallel to the surface of the metal bit line 101 , thereby improving the integration density of the semiconductor structure in the horizontal direction. In addition, the metal bit line 101 has low resistivity and excellent electrical conductivity, which is conducive to further reducing the energy consumption of the semiconductor structure during operation; and the metal bit line 101 is located in the substrate 100, which is conducive to reducing the overall thickness of the semiconductor structure, so as to further reduce the semiconductor structure. Overall dimensions of the structure.

In addition, the semiconductor structure provided in this embodiment can be applied to a 4F ² memory, where F is a feature size, and the memory can be a DRAM memory or an SRAM memory. Correspondingly, yet another embodiment of the present invention provides a method for fabricating a semiconductor structure for forming the above-mentioned semiconductor structure.

2 to FIG. 16 are schematic cross-sectional structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present invention. The following will describe in detail the method for manufacturing a semiconductor structure provided by this embodiment with reference to the accompanying drawings. The same or corresponding parts of the examples will not be described in detail below.

Referring to FIG. 2 to FIG. 3 , a substrate 100 is provided, the substrate 100 has metal bit lines 101 therein, and the surface of the metal bit lines 101 is exposed from the substrate 100 .

Specifically, the process steps of forming the substrate 100 and the metal bit lines 101 include the following steps:

Referring to FIG. 2 , a logic circuit structure layer 110 and an interlayer dielectric layer 120 are provided in a stacked arrangement.

The interlayer dielectric layer 120 covers the entire surface of the logic circuit structure layer 110 for protecting the logic circuit structure layer 110 and preventing the logic circuit structure layer 110 and the subsequent metal bit lines formed on the interlayer dielectric layer 120 from forming electrical interference.

Referring to FIG. 3 , a number of mutually separated metal bit lines 101 are formed on the surface of the interlayer dielectric layer 120 , and the metal bit lines 101 expose a part of the surface of the interlayer dielectric layer 120 ; an isolation layer 103 is formed, and the isolation layer 103 is located on the exposed surface of the metal bit line 101 . The surface of the interlayer dielectric layer 120 covers the sidewall of the metal bit line 101 .

For the material of the metal bit line 101 , reference may be made to the corresponding descriptions of the foregoing embodiments, and details are not described herein again. The substrate 100 may include a logic circuit structure layer 110 , an interlayer dielectric layer 120 and an isolation layer 103 .

It can be understood that, in other embodiments, the surface of the logic circuit structure layer may also have an initial dielectric layer; the initial dielectric layer is patterned to form a plurality of mutually discrete trenches in the initial dielectric layer, and the initial dielectric layer located below the grooves is formed. The dielectric layer is used as an interlayer dielectric layer, and the initial dielectric layer between adjacent trenches is used as an isolation layer. In this way, the isolation layer and the initial dielectric layer have an integrated structure; then, metal bit lines that fill the trenches are formed.

Referring to FIG. 4 , a first metal layer 118 is formed on the surface of the metal bit line 101 .

The first metal layer 118 is used for reacting with the subsequently formed semiconductor channel near the metal bit line 101 to provide metal elements for the subsequent formation of the first metal semiconductor layer, so as to reduce the resistivity of the semiconductor channel. The material of the first metal layer 118 includes at least one of cobalt, nickel or platinum.

In this embodiment, the first metal layer 118 covers the entire surface of the metal bit line 101 , which can avoid etching damage to the metal bit line 101 caused by the process of etching the first metal layer 118 . In other embodiments, the first metal layer may only be located on a part of the surface of the metal bit line, and the position of the first metal layer corresponds to the position of the subsequently formed semiconductor channel.

In other embodiments, the first metal layer may not be formed on the surface of the metal bit line, and the semiconductor channel may be directly formed on a part of the surface of the metal bit line subsequently. In addition, in some embodiments, the material of the metal bit line is at least one of nickel, cobalt, or platinum, that is, the metal bit line can be formed later to form the first metal semiconductor layer to provide metal elements, and there is no need to add metal elements on the surface of the metal bit line. A first metal layer is formed.

Referring to FIGS. 5 to 6 , a semiconductor channel 102 is formed, the semiconductor channel 102 is located on a part of the surface of the metal bit line 101 , and in the direction along the substrate 100 to the metal bit line 101 , the semiconductor channel 102 includes first doped regions arranged in sequence I, the channel region II and the second doping region III, the first doping region I is electrically connected to the metal bit line 101 .

In this embodiment, the semiconductor channel 102 is in contact with the first metal layer 118; in other embodiments, the semiconductor channel may be in direct contact with the metal bit line.

Specifically, the process steps of forming the semiconductor channel 102 include the following steps:

Referring to FIG. 5 , an initial channel layer 132 is formed, and the initial channel layer 132 is located on the metal bit line 101 and on the substrate 100 .

In some embodiments, there is an isolation layer 103 between adjacent metal bit lines 101 , and the initial channel layer 132 covers the surface of the isolation layer 103 .

In this embodiment, the first metal layer 118 is formed on the surface of the metal bit line 101 , and the initial channel layer 132 covers the surface of the first metal layer 118 . In other embodiments, the initial channel layer may directly cover the surface of the metal bit line.

Specifically, the method of forming the initial channel layer 132 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic compound chemical vapor deposition. The material of the initial channel layer 132 is IGZO, IWO or ITO.

Continuing to refer to FIG. 5 , a patterned mask layer 109 is formed on the surface of the initial channel layer 132 .

The mask layer 109 is used to define the position and size of the subsequently formed semiconductor channel 102 . The material of the mask layer 109 may be silicon nitride, silicon carbonitride or silicon oxycarbonitride. In other embodiments, the material of the mask layer can also be photoresist.

Referring to FIG. 6 , the initial channel layer 132 (refer to FIG. 5 ) is patterned by using the mask layer 109 as a mask to form the semiconductor channel 102 .

The semiconductor channel 102 includes a first doped region I, a channel region II and a second doped region III arranged in sequence.

Wherein, the first doping region I, the channel region II, and the second doping region III in the semiconductor channel 102 are doped with the same type of doping ions, so the device formed by the semiconductor channel 102 is a junctionless transistor, which avoids The problems of threshold voltage drift and leakage current increase caused by doping mutation are also beneficial to suppress the short-channel effect.

It can be understood that the initial channel layer 132 may be pre-doped before the patterning process, and the doping process may be doped with N-type ions or P-type ions; the initial channel layer 132 may also be subjected to the patterning process. A doping treatment is then performed to form the semiconductor channel 102 with a suitable ion distribution.

In this embodiment, the semiconductor channel 102 may be corner-rounded by thermal oxidation, etching and/or hydrogen annealing to form the semiconductor channel 102 with a cylindrical structure, which is beneficial to avoid the A phenomenon of tip discharge or leakage occurs in the semiconductor channel 102 .

Referring to FIG. 7 , a first dielectric layer 115 is formed, and the first dielectric layer 115 is located on a surface of the first metal layer 118 away from the substrate 100 and in an interval between adjacent first metal layers 118 .

Specifically, the first dielectric layer 115 is located on the surface of the isolation layer 103 and the sidewall surface of the first doped region I (refer to FIG. 6 ), and is used to isolate the first metal layer 118 from the subsequently formed word lines. The first dielectric layer 115 is an integral film structure for preventing electrical interference between the first metal layer 118 and the metal bit lines 101 and subsequently formed word lines.

The step of forming the first dielectric layer 115 includes: forming an initial first dielectric layer on the surface of the metal bit line 101 away from the substrate 100 ; performing a planarization process on the initial first dielectric layer and etching back to a preset thickness to form a first dielectric layer. Dielectric layer 115 .

The subsequent steps include: forming word lines, and the word lines are arranged around the channel region. The step of forming the word lines includes the following steps:

Referring to FIG. 8 , a gate dielectric layer 114 is formed on the sidewalls of the semiconductor channel 102 in the channel region II (refer to FIG. 6 ) and the second doped region III (refer to FIG. 6 ).

The gate dielectric layer 114 exposes the surface of the first dielectric layer 115 other than directly below the semiconductor channel 102 . The gate dielectric layer 114 is used to protect the semiconductor channel 102 during the subsequent annealing process, and prevent the material of the subsequent semiconductor channel 102 from reacting with the metal material.

In this embodiment, the gate dielectric layer 114 is located at the end face of the second doped region III away from the substrate 100 . In the subsequent step of forming the second dielectric layer, the gate dielectric located at the end face of the second doped region III away from the substrate 100 is removed together. The layer 114 facilitates the subsequent formation of a metal layer on the end face of the second doped region III away from the substrate 100 . In other embodiments, the gate dielectric layer covering the end face of the second doped region may be removed by an etching process.

Referring to FIG. 9 , an initial gate conductive layer 134 is formed on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II (refer to FIG. 6 ), and the initial gate conductive layer 134 surrounds the channel region II. Mask layer structure.

Specifically, the method of forming the initial gate conductive layer 134 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic compound chemical vapor deposition. In addition, by planarizing and etching the initial gate conductive layer 134, the initial gate conductive layer 134 is located on the sidewall surface of the gate dielectric layer 114 corresponding to the channel region II.

Referring to FIG. 10 , the initial gate conductive layer 134 (refer to FIG. 9 ) is patterned to form the gate conductive layers 124 spaced apart from each other, so that the gate conductive layers 124 of different semiconductor channels 102 located on the same metal bit line 101 can be connected to different potentials, Therefore, it is beneficial to realize the diversified control of the semiconductor channels. Wherein, the method of patterning includes photolithography.

For each gate dielectric layer 114, each gate dielectric layer 114 may be disposed around the channel region II of at least one semiconductor channel 102. In FIG. 10, each gate dielectric layer 114 is used as an example to surround two semiconductor channels 102. According to actual electrical requirements, the number of semiconductor channels 102 surrounded by each gate dielectric layer 114 is reasonably set.

The gate dielectric layer 114 and the gate conductive layer 124 together form the word line 104 , so the word line 104 is also arranged around the two semiconductor channels 102 .

Referring to FIG. 11 , a second dielectric layer 125 is formed, the second dielectric layer 125 is located in the interval between adjacent gate conductive layers 124 for preventing electrical interference between adjacent gate conductive layers 124 , and the second dielectric layer 125 is also located in The gate conductive layer 124 is away from the surface of the substrate 100 to support other conductive structures formed on the surface of the second dielectric layer 125 away from the substrate 100 and to achieve insulation between the gate conductive layer 124 and other conductive structures.

In addition, after the second dielectric layer 125 is formed, the second dielectric layer 125 is planarized, and the gate dielectric layer 114 located on the end surface of the mask layer 109 away from the substrate 100 is removed, so that the second dielectric layer 125 is exposed on the second dielectric layer 125. The mask layer 109 on the end surface of the second doped region III away from the substrate 100 .

In this embodiment, the first dielectric layer 115 and the second dielectric layer 125 together form the dielectric layer 105 . In addition, the materials of the first dielectric layer 115 and the second dielectric layer 125 are the same, which is beneficial to reduce the types of materials required in the fabrication process of the semiconductor structure, and reduce the fabrication cost and complexity of the semiconductor structure. In addition, the dielectric layer 105 also exposes the top surface of the mask layer 109 .

11 to 12 , the mask layer 109 is removed to expose the top surface of the second doped region III (refer to FIG. 6 ), and a second metal layer is formed on the exposed top surface of the second doped region III.

The second metal layer is used for reacting with the second doped region III of the semiconductor channel to provide metal elements for the subsequent formation of the second metal-semiconductor layer, so as to reduce the resistivity of the semiconductor channel. Wherein, the material of the second metal layer includes at least one of cobalt, nickel or platinum.

The manufacturing method may further include: performing a first annealing treatment, and the first metal layer 118 reacts with the first doped region I, so as to convert a partial thickness of the first doped region I toward the metal bit line 101 into a first metal semiconductor For the layer 112 , the resistivity of the material of the first metal-semiconductor layer 112 is lower than the resistivity of the material of the first doped region I other than the first metal-semiconductor layer 112 .

The first metal layer 118 that reacts with the first doped region I becomes a part of the first doped region I, and the first metal layer 118 that does not react with the first doped region I serves as the metal layer 108 . It can be understood that a partial thickness of the first metal layer 118 may remain between the metal bit line 101 and the first metal semiconductor layer 112 , and the remaining first metal layer 118 serves as the metal layer 108 , that is, the metal layer 108 can be either The surface of the metal bit line 101 located outside the first metal semiconductor layer 112 may also be located between the first metal semiconductor layer 112 and the metal bit line 101 .

In this embodiment, while the first annealing treatment is carried out, the second annealing treatment is carried out, and the second metal layer reacts with the second doping region III, so as to convert the exposed part of the thickness of the second doping region III into the second annealing treatment. Two metal-semiconductor layers 122 , and the resistivity of the material of the second metal-semiconductor layer 122 is lower than the resistivity of the second doped region III outside the second metal-semiconductor layer 122 .

Specifically, rapid thermal annealing is used for the annealing treatment. The process parameters of the rapid thermal annealing include: annealing the semiconductor structure in an N ₂ atmosphere, the annealing temperature is 600°C to 850°C, and the annealing time is 10 seconds to 60 seconds. Since the annealing temperature is moderate, it is favorable for the first metal layer 118 to react sufficiently with the first doping region I, so that the second metal layer and the second doping region III react sufficiently, so as to form a first metal semiconductor with relatively low resistivity layer 112 and the second metal semiconductor layer 122 . In addition, due to the moderate annealing temperature, it is beneficial to prevent the metal elements in the first metal layer 118 and the second metal layer from diffusing into the channel region II. In addition, performing the annealing treatment in an N ₂ atmosphere is beneficial to avoid oxidation of the first metal layer 118 , the second metal layer and the semiconductor channel 102 .

In this embodiment, the first annealing treatment and the second annealing treatment are performed simultaneously, which is beneficial to simplify the manufacturing process of the semiconductor structure. In other embodiments, after the semiconductor channel is formed on the first metal layer, the first annealing treatment may be performed; after the second metal layer is formed on the second doped region, the second annealing treatment may be performed.

In addition, in some other embodiments, before forming the semiconductor channel, a first semiconductor layer may also be formed on the surface of the first metal layer, the material of the first semiconductor layer is silicon or germanium, and during the first annealing process the first semiconductor layer is formed. The semiconductor layer reacts with the first metal layer to form a first metal semiconductor layer; before forming the second metal layer, a second semiconductor layer is formed on the top surface of the second doped region, and the material of the second semiconductor layer is silicon or germanium, And during the second annealing process, the second semiconductor layer reacts with the second metal layer to form the second metal semiconductor layer.

1 , 13 to 16 , a capacitor structure 106 is formed. The capacitor structure 106 is located on the side of the second doped region III (refer to FIG. 6 ) away from the channel region II (refer to FIG. 6 ). The two doped regions III are in contact.

The process steps of forming the capacitor structure 106 include the following steps:

Referring to FIG. 13 , an initial insulating layer 137 is formed, and the initial insulating layer 137 covers the word line 104 and the second metal semiconductor layer 122 .

Specifically, the initial insulating layer 137 is located on the surface of the second dielectric layer 125 away from the substrate 100 and the surface of the second metal semiconductor layer 122 away from the substrate 100 , and the thickness of the initial insulating layer 137 is larger than that of the second dielectric layer 125 . It is large, which is convenient for the subsequent formation of the capacitor structure. The material of the initial insulating layer 137 may include at least one of low dielectric constant materials such as borosilicate glass, borophosphosilicate glass, ethyl orthosilicate or silicon oxide.

Referring to FIG. 14 , the initial insulating layer 137 (refer to FIG. 13 ) is etched to form the through hole 10 exposing the second doped region III, and the remaining initial insulating layer 137 serves as the insulating layer 107 .

Specifically, the step of forming the through hole 10 may include: forming a patterned mask layer on the surface of the initial insulating layer 137; using the patterned mask layer as a mask, using a dry etching process to etch the initial insulating layer 137 until The second doped region III is exposed to form the via hole 10 .

Referring to FIG. 15, a lower electrode layer 116 is formed, and the lower electrode layer 116 is located at the bottom and sidewalls of the through hole 10 (refer to FIG. 14).

Specifically, when the lower electrode layer 116 is formed, part of the lower electrode layer 116 is formed on the surface of the insulating layer 107 away from the substrate 100 , and the lower electrode layer located on the surface of the insulating layer 107 away from the substrate 100 is removed by a planarization process or an etching process 116.

16 , a capacitor dielectric layer 126 is formed. The capacitor dielectric layer 126 covers the surface of the lower electrode layer 116 and a part of the surface of the insulating layer 107 close to the through hole 10 . The capacitor dielectric layer 126 in the through hole 10 surrounds the groove 11 .

Specifically, the step of forming the capacitive dielectric layer 126 includes: forming an initial capacitive dielectric layer, the initial capacitive dielectric layer covers the surface of the lower electrode layer 116 and the surface of the insulating layer 107 , and the initial capacitive dielectric layer located in the through hole 10 surrounds a concave Slot 11 ; pattern the initial capacitive dielectric layer, and retain the initial capacitive dielectric layer covering the surface of the lower electrode layer 116 and the part of the surface of the insulating layer 107 close to the through hole 10 as the capacitive dielectric layer 126 .

In other embodiments, after the initial capacitive dielectric layer is formed, the initial capacitive dielectric layer may not be etched, and subsequently the upper electrode layer is directly formed on the basis of the initial capacitive dielectric layer.

16 and FIG. 1, a first barrier layer 117 is formed, the first barrier layer 117 is located on the surface of the insulating layer 107 not covered by the capacitive dielectric layer 126, and the top surface of the first blocking layer 117 and the top surface of the capacitive dielectric layer 126 Being flush is beneficial to provide good support for other structures located on the top surface of the first barrier layer 117 and the top surface of the capacitive dielectric layer 126 .

An upper electrode layer 136 is formed. The upper electrode layer 136 is located on the surface of the capacitor dielectric layer 126 and fills the groove 11 (refer to FIG. 16 ). In this embodiment, the lower electrode layer 116 , the capacitor dielectric layer 126 and the upper electrode layer 136 together form the capacitor structure 106 .

In this embodiment, the lower electrode layers 116 located in the adjacent through holes 10 are separated from each other, and the capacitive dielectric layers 126 located on the surface of the adjacent lower electrode layers 116 are also spaced from each other, and the capacitive dielectric layers 126 are also located on the insulating layer. 107 is close to a part of the surface of the through hole 10 , and the surface of the insulating layer 107 not covered by the capacitive dielectric layer 126 is covered with the first barrier layer 117 . In other embodiments, the capacitive dielectric layer may also cover the entire surface of the insulating layer.

The upper electrode layer 136 is also located on the surface of the first barrier layer 117 between the adjacent capacitor dielectric layers 126 , that is, the upper electrode layers 136 filled with the adjacent through holes 10 are in contact and connected to each other, and the upper electrode layers 136 have an integrated structure. In other embodiments, the upper electrode layers located in the adjacent through holes may have a space between them, so that the upper electrode layers in the adjacent capacitor structures can be connected to different potentials, which is beneficial to realize the diversification of the adjacent capacitor structures control.

Further, a second barrier layer 127 is formed, and the second barrier layer 127 is located on the surface of the upper electrode layer 136 and the surface of the first barrier layer 117 not covered by the upper electrode layer 136 to prevent the upper electrode layer 136 from interacting with the external conductive structure. electrical interference between. The material of the second barrier layer 127 is at least one of silicon oxide, silicon nitride, silicon oxycarbonitride or silicon oxynitride. In this embodiment, the material of the second barrier layer 127 is the same as the material of the first barrier layer 117 . In other embodiments, the material of the second barrier layer may also be different from the material of the first barrier layer.

It should be noted that, in other embodiments, in the process step of forming the lower electrode layer, a lower electrode layer filled with through holes may also be formed, and correspondingly, the lower electrode layer has a columnar structure.

To sum up, the channel region II of the semiconductor channel 102 is vertically disposed on the metal bit line 101 . On the one hand, the electrical connection between the semiconductor channel 102 and the metal bit line 101 and the capacitor structure 106 can be realized without an additional electrical connection structure. The connection is beneficial to reduce the complexity of the semiconductor structure; on the other hand, it is beneficial to save the layout space of the semiconductor channel 102 in the direction parallel to the surface of the metal bit line 101, thereby improving the integration density of the semiconductor structure in the horizontal direction. In addition, a first metal layer 118 in contact with the first doping region I and a second metal layer in contact with the second doping region III are formed, and through the first annealing treatment and the second annealing treatment, part of the first doping region is formed. The impurity region I transforms the first metal-semiconductor layer 112, and part of the second doped region III transforms the second metal-semiconductor layer 122, thereby reducing the resistivity of the first doped region I and the second doped region III, thereby helping to reduce the The power consumption required for the electrical signal to pass between the semiconductor channel 102 and the metal bit line 101 and the capacitive structure 106 .

Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present invention, and in practical applications, various changes in form and details can be made without departing from the spirit and the spirit of the present invention. scope. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. a semiconductor structure, is characterized in that, comprises: a substrate, wherein the substrate has metal bit lines, and the substrate exposes the surface of the metal bit lines; a semiconductor channel, the semiconductor channel is located on a part of the surface of the metal bit line, and along the direction of the substrate to the metal bit line, the semiconductor channel includes a first doped region, a channel region and a second doped region, the first doped region is electrically connected to the metal bit line; a word line, the word line is arranged around the channel region; a dielectric layer, the dielectric layer is located between the metal bit line and the word line, and is also located on the side of the word line away from the substrate; A capacitor structure, the capacitor structure is located on a side of the second doped region away from the channel region, and the capacitor structure is in contact with the second doped region. 2. The semiconductor structure of claim 1, wherein the substrate comprises: Logic circuit structure layer, with several logic circuits; an interlayer dielectric layer, the interlayer dielectric layer is located on the surface of the logic circuit structure layer, and the metal bit line is located on a part of the surface of the interlayer dielectric layer away from the logic circuit structure layer; an isolation layer, the isolation layer is located on the surface of the interlayer dielectric layer exposed by the metal bit line and covers the sidewall of the metal bit line. 3 . The semiconductor structure of claim 2 , wherein the interlayer dielectric layer and the isolation layer have an integral structure. 4 . 4 . The semiconductor structure of claim 1 , wherein the material of the semiconductor channel comprises at least one or more of IGZO, IWO or ITO. 5 . 5 . The semiconductor structure of claim 1 , wherein the first doped region comprises: a first metal-semiconductor layer, the first metal-semiconductor layer is in contact with the metal bit line, and the The resistivity of the first metal-semiconductor layer is lower than the resistivity of the first doped region other than the first metal-semiconductor layer. 6 . The semiconductor structure of claim 5 , wherein the semiconductor structure further comprises: a metal layer, the metal layer is located on the surface of the metal bit line not covered by the semiconductor channel, and the metal layer It consists of metal elements in the first metal semiconductor layer. 7 . The semiconductor structure of claim 1 , wherein the second doped region comprises: a second metal-semiconductor layer, the second metal-semiconductor layer is in contact with the capacitor structure, and the first metal-semiconductor layer is in contact with the capacitor structure. The resistivity of the material of the two metal-semiconductor layers is smaller than the resistivity of the second doped region other than the second metal-semiconductor layer. 8. The semiconductor structure of claim 7, wherein the metal element in the second metal-semiconductor layer comprises at least one of cobalt, nickel or platinum. 9 . The semiconductor structure of claim 7 , wherein the semiconductor element in the second metal-semiconductor layer is the same as the semiconductor element in the second doped region other than the second metal-semiconductor layer. 10 . or, the semiconductor element in the second metal semiconductor layer is silicon or germanium. 10. The semiconductor structure of claim 1, wherein the device formed by the semiconductor channel is a junctionless transistor. 11. The semiconductor structure of claim 1, wherein the word line comprises: a gate dielectric layer, the gate dielectric layer is disposed around the channel region, and is located on the sidewall surface of the semiconductor channel in the channel region, and is also located on the side of the semiconductor channel in the second doped region wall surface; A gate conductive layer, the gate conductive layer is disposed around the channel region, and is located on the sidewall surface of the gate dielectric layer corresponding to the channel region. 12. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a plurality of the word lines that are separated from each other; the dielectric layer comprises: A first dielectric layer, the first dielectric layer is located between the metal bit line and the word line, and is located on the surface of the substrate and the surface of the bit line exposed by the semiconductor channel, and adjacent to the surface of the bit line. the word line exposes a part of the surface of the first dielectric layer; A second dielectric layer, the second dielectric layer is located on the surface of the word line and the exposed surface of the first dielectric layer, and also surrounds the semiconductor channel of the second doped region, the second dielectric layer The top surface of the second doped region is exposed. 13. The semiconductor structure of claim 1, further comprising: an insulating layer, the insulating layer is located on the side of the second doping region away from the substrate, and the insulating layer has a through hole penetrating the insulating layer, and the second doping region is exposed from the through hole area top; The capacitor structure includes: a lower electrode layer, the lower electrode layer is located at the bottom and sidewall of the through hole; a capacitive dielectric layer, the capacitive dielectric layer covers the surface of the lower electrode layer; an upper electrode layer, the upper electrode layer covers the surface of the capacitor dielectric layer and fills the through holes. 14. A method of manufacturing a semiconductor structure, comprising: providing a substrate, wherein the substrate has metal bit lines, and the substrate exposes the surface of the metal bit lines; forming a semiconductor channel, the semiconductor channel is located on a part of the surface of the metal bit line, and along the direction of the substrate to the metal bit line, the semiconductor channel includes a first doped region, a channel arranged in sequence a region and a second doping region, the first doping region is electrically connected to the metal bit line; forming word lines, the word lines are arranged around the channel region; forming a dielectric layer, the dielectric layer is located between the metal bit line and the word line, and is also located on the side of the word line away from the substrate; A capacitor structure is formed, the capacitor structure is located on a side of the second doped region away from the channel region, and the capacitor structure is in contact with the second doped region. 15. The manufacturing method of claim 14, wherein the process step of forming the substrate and the metal bit line comprises: Provide layered logic circuit structure layers and interlayer dielectric layers; A plurality of mutually separated metal bit lines are formed on the surface of the interlayer dielectric layer, and the metal bit lines are exposed on a part of the surface of the interlayer dielectric layer; An isolation layer is formed, the isolation layer is located on the surface of the interlayer dielectric layer exposed by the metal bit line and covers the sidewall of the metal bit line. 16. The manufacturing method of claim 14, wherein before forming the semiconductor channel, further comprising: forming a first metal layer on the surface of the metal bit line; After forming the semiconductor channel, it also includes: a first annealing treatment is performed, the first metal layer reacts with the first doped region to convert a partial thickness of the first doped region towards the metal bit line into a first metal semiconductor layer, The resistivity of the material of the first metal-semiconductor layer is lower than the resistivity of the material of the first doped region other than the first metal-semiconductor layer. 17. The method of claim 14, wherein the step of forming the semiconductor channel comprises: forming an initial channel layer on the metal bit line and on the substrate; forming a patterned mask layer on the surface of the initial channel layer; The initial channel layer is patterned by using the mask layer as a mask to form the semiconductor channel. 18. The manufacturing method of claim 17, wherein the dielectric layer exposes the top surface of the mask layer; after the dielectric layer is formed and before the capacitor structure is formed, the method further comprises: removing the mask layer to expose the top surface of the second doped region; forming a second metal layer on the exposed top surface of the second doped region; A second annealing process is performed, the second metal layer reacts with the second doped region to convert the exposed partial thickness of the second doped region into a second metal semiconductor layer, and the second The resistivity of the material of the metal-semiconductor layer is lower than the resistivity of the second doped region other than the second metal-semiconductor layer. 19 . The manufacturing method according to claim 18 , wherein the second annealing treatment is performed by using rapid thermal annealing; the process parameters of the rapid thermal annealing include: performing the annealing treatment in an N ₂ atmosphere, annealing The temperature is 600°C to 850°C, and the annealing time is 10 seconds to 60 seconds. 20. The manufacturing method of claim 14, wherein the process step of forming the word line comprises: forming a gate dielectric layer on the channel region and the sidewalls of the semiconductor channel of the second doped region; A gate conductive layer is formed on the surface of the gate dielectric layer in the channel region, and the gate conductive layer surrounds the channel region.

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