KR960035858A - 실리콘에 테이퍼진 개구부를 형성하기 위한 방법 - Google Patents

실리콘에 테이퍼진 개구부를 형성하기 위한 방법 Download PDF

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Publication number
KR960035858A
KR960035858A KR1019960005640A KR19960005640A KR960035858A KR 960035858 A KR960035858 A KR 960035858A KR 1019960005640 A KR1019960005640 A KR 1019960005640A KR 19960005640 A KR19960005640 A KR 19960005640A KR 960035858 A KR960035858 A KR 960035858A
Authority
KR
South Korea
Prior art keywords
silicon
opening
input gas
introducing
processing chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960005640A
Other languages
English (en)
Korean (ko)
Inventor
휴 린 장
Original Assignee
빈센트 비. 인그라시아
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 빈센트 비. 인그라시아, 모토로라 인코포레이티드 filed Critical 빈센트 비. 인그라시아
Publication of KR960035858A publication Critical patent/KR960035858A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
KR1019960005640A 1995-03-06 1996-02-29 실리콘에 테이퍼진 개구부를 형성하기 위한 방법 Withdrawn KR960035858A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39924595A 1995-03-06 1995-03-06
US399,245 1995-03-06

Publications (1)

Publication Number Publication Date
KR960035858A true KR960035858A (ko) 1996-10-28

Family

ID=23578769

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960005640A Withdrawn KR960035858A (ko) 1995-03-06 1996-02-29 실리콘에 테이퍼진 개구부를 형성하기 위한 방법

Country Status (5)

Country Link
US (1) US5651858A (enExample)
JP (1) JPH08250485A (enExample)
KR (1) KR960035858A (enExample)
SG (1) SG40837A1 (enExample)
TW (1) TW297919B (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2644912B2 (ja) 1990-08-29 1997-08-25 株式会社日立製作所 真空処理装置及びその運転方法
USD453402S1 (en) 1990-08-22 2002-02-05 Hitachi, Ltd. Vacuum processing equipment configuration
USRE39756E1 (en) * 1990-08-29 2007-08-07 Hitachi, Ltd. Vacuum processing operating method with wafers, substrates and/or semiconductors
USD473354S1 (en) 1990-08-29 2003-04-15 Hitachi, Ltd. Vacuum processing equipment configuration
US7089680B1 (en) 1990-08-29 2006-08-15 Hitachi, Ltd. Vacuum processing apparatus and operating method therefor
USRE39823E1 (en) * 1990-08-29 2007-09-11 Hitachi, Ltd. Vacuum processing operating method with wafers, substrates and/or semiconductors
TW388100B (en) 1997-02-18 2000-04-21 Hitachi Ulsi Eng Corp Semiconductor deivce and process for producing the same
US6008131A (en) * 1997-12-22 1999-12-28 Taiwan Semiconductor Manufacturing Company Ltd. Bottom rounding in shallow trench etching using a highly isotropic etching step
WO2003001577A1 (fr) * 2001-06-22 2003-01-03 Tokyo Electron Limited Procede de gravure seche
US7514328B2 (en) * 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7332737B2 (en) * 2004-06-22 2008-02-19 Micron Technology, Inc. Isolation trench geometry for image sensors
US8703619B2 (en) * 2012-01-19 2014-04-22 Headway Technologies, Inc. Taper-etching method and method of manufacturing near-field light generator
US9985094B2 (en) * 2013-12-27 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Super junction with an angled trench, transistor having the super junction and method of making the same
US9865471B2 (en) * 2015-04-30 2018-01-09 Tokyo Electron Limited Etching method and etching apparatus
US20250299928A1 (en) * 2022-12-13 2025-09-25 Hitachi High-Tech Corporation Plasma processing method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
JPS62224687A (ja) * 1986-03-25 1987-10-02 Anelva Corp エツチング方法
US5118384A (en) * 1990-04-03 1992-06-02 International Business Machines Corporation Reactive ion etching buffer mask

Also Published As

Publication number Publication date
JPH08250485A (ja) 1996-09-27
US5651858A (en) 1997-07-29
TW297919B (enExample) 1997-02-11
SG40837A1 (en) 1997-06-14

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960229

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid