JPH08250485A - シリコンにテーパ状開口を形成する方法 - Google Patents

シリコンにテーパ状開口を形成する方法

Info

Publication number
JPH08250485A
JPH08250485A JP8073216A JP7321696A JPH08250485A JP H08250485 A JPH08250485 A JP H08250485A JP 8073216 A JP8073216 A JP 8073216A JP 7321696 A JP7321696 A JP 7321696A JP H08250485 A JPH08250485 A JP H08250485A
Authority
JP
Japan
Prior art keywords
opening
process chamber
forming
tapered
introducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8073216A
Other languages
English (en)
Japanese (ja)
Inventor
Jung-Hui Lin
ジャン−ヒュイ・リン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPH08250485A publication Critical patent/JPH08250485A/ja
Pending legal-status Critical Current

Links

Classifications

    • H10P50/242—
    • H10P52/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
JP8073216A 1995-03-06 1996-03-04 シリコンにテーパ状開口を形成する方法 Pending JPH08250485A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39924595A 1995-03-06 1995-03-06
US399245 1995-03-06

Publications (1)

Publication Number Publication Date
JPH08250485A true JPH08250485A (ja) 1996-09-27

Family

ID=23578769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8073216A Pending JPH08250485A (ja) 1995-03-06 1996-03-04 シリコンにテーパ状開口を形成する方法

Country Status (5)

Country Link
US (1) US5651858A (enExample)
JP (1) JPH08250485A (enExample)
KR (1) KR960035858A (enExample)
SG (1) SG40837A1 (enExample)
TW (1) TW297919B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013149944A (ja) * 2012-01-19 2013-08-01 Headway Technologies Inc テーパエッチング方法および近接場光発生器の製造方法
WO2024127535A1 (ja) * 2022-12-13 2024-06-20 株式会社日立ハイテク プラズマ処理方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2644912B2 (ja) * 1990-08-29 1997-08-25 株式会社日立製作所 真空処理装置及びその運転方法
USD453402S1 (en) 1990-08-22 2002-02-05 Hitachi, Ltd. Vacuum processing equipment configuration
USRE39756E1 (en) * 1990-08-29 2007-08-07 Hitachi, Ltd. Vacuum processing operating method with wafers, substrates and/or semiconductors
USD473354S1 (en) 1990-08-29 2003-04-15 Hitachi, Ltd. Vacuum processing equipment configuration
USRE39824E1 (en) * 1990-08-29 2007-09-11 Hitachi, Ltd. Vacuum processing apparatus and operating method with wafers, substrates and/or semiconductors
US7089680B1 (en) 1990-08-29 2006-08-15 Hitachi, Ltd. Vacuum processing apparatus and operating method therefor
TW388100B (en) 1997-02-18 2000-04-21 Hitachi Ulsi Eng Corp Semiconductor deivce and process for producing the same
US6008131A (en) * 1997-12-22 1999-12-28 Taiwan Semiconductor Manufacturing Company Ltd. Bottom rounding in shallow trench etching using a highly isotropic etching step
KR100702723B1 (ko) * 2001-06-22 2007-04-03 동경 엘렉트론 주식회사 드라이 에칭 방법
US7514328B2 (en) * 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7332737B2 (en) * 2004-06-22 2008-02-19 Micron Technology, Inc. Isolation trench geometry for image sensors
US9985094B2 (en) * 2013-12-27 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Super junction with an angled trench, transistor having the super junction and method of making the same
US9865471B2 (en) * 2015-04-30 2018-01-09 Tokyo Electron Limited Etching method and etching apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
US4855017A (en) * 1985-05-03 1989-08-08 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
JPS62224687A (ja) * 1986-03-25 1987-10-02 Anelva Corp エツチング方法
US5118384A (en) * 1990-04-03 1992-06-02 International Business Machines Corporation Reactive ion etching buffer mask

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013149944A (ja) * 2012-01-19 2013-08-01 Headway Technologies Inc テーパエッチング方法および近接場光発生器の製造方法
WO2024127535A1 (ja) * 2022-12-13 2024-06-20 株式会社日立ハイテク プラズマ処理方法
JPWO2024127535A1 (enExample) * 2022-12-13 2024-06-20

Also Published As

Publication number Publication date
TW297919B (enExample) 1997-02-11
KR960035858A (ko) 1996-10-28
US5651858A (en) 1997-07-29
SG40837A1 (en) 1997-06-14

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