KR960030334A - Method for forming titanium silicide layer of semiconductor device - Google Patents

Method for forming titanium silicide layer of semiconductor device Download PDF

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Publication number
KR960030334A
KR960030334A KR1019950000075A KR19950000075A KR960030334A KR 960030334 A KR960030334 A KR 960030334A KR 1019950000075 A KR1019950000075 A KR 1019950000075A KR 19950000075 A KR19950000075 A KR 19950000075A KR 960030334 A KR960030334 A KR 960030334A
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KR
South Korea
Prior art keywords
silicide layer
titanium
semiconductor device
titanium silicide
silicon substrate
Prior art date
Application number
KR1019950000075A
Other languages
Korean (ko)
Other versions
KR0168153B1 (en
Inventor
박민우
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950000075A priority Critical patent/KR0168153B1/en
Publication of KR960030334A publication Critical patent/KR960030334A/en
Application granted granted Critical
Publication of KR0168153B1 publication Critical patent/KR0168153B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

본 발명은 반도체 소자의 티타늄 실리사이드층 형성방법에 관한 것으로, 실리콘 기판온도를 액화 질소온도로 유지시킨 상태에서 티타늄을 증착하여 비정질계의 티타늄 박막을 형성한 후 이를 실리콘 기판 원자와 반응시키므로서 N+접합영역상의 티타늄 실리사이드층의 두께를 증가시킬 수 있는 반도체 소자의 텅스텐 실리사이드층 형성방법에 관한 것이다.The present invention relates to a method for forming a titanium silicide layer of a semiconductor device, wherein an amorphous titanium thin film is formed by depositing titanium while maintaining a silicon substrate temperature at a liquefied nitrogen temperature, and reacting it with a silicon substrate atom by N +. A method of forming a tungsten silicide layer of a semiconductor device capable of increasing the thickness of a titanium silicide layer on a junction region.

Description

반도체 소자의 티타늄 실리사이드층 형성방법Method for forming titanium silicide layer of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1C도는 본 발명에 따른 반도체 소자의 티타늄 실리사이드층 형성방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method for forming a titanium silicide layer of a semiconductor device according to the present invention.

Claims (3)

반도체 소자의 티타늄 실리사이드층 형성방법에 있어서, 접합영역 및 게이트 전극이 형성된 실리콘 기판을 극저온 상태로 유지시킨 상태에서 티타늄을 증착한 후 열처리공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 티타늄 실리사이드층 형성방법.A method for forming a titanium silicide layer of a semiconductor device, the method comprising: depositing titanium in a state in which a silicon substrate having a junction region and a gate electrode formed thereon is kept at a cryogenic state, and then performing a heat treatment process. Layer formation method. 제1항에 있어서, 상기 티타늄은 물리증착법에 의해 증착되는 것을 특징으로 하는 반도체 소자의 티타늄 실리사이드층 형성방법.The method of claim 1, wherein the titanium is deposited by physical vapor deposition. 제1항에 있어서, 상기 티타늄은 상기 실리콘 기판을 액화질소 온도로 유지시킨 상태에서 증착되는 것을 특징으로 하는 반도체 소자의 티타늄 실리사이드층 형성방법.The method of claim 1, wherein the titanium is deposited while the silicon substrate is maintained at a liquid nitrogen temperature. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950000075A 1995-01-05 1995-01-05 Forming method of titanium silicide layer KR0168153B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950000075A KR0168153B1 (en) 1995-01-05 1995-01-05 Forming method of titanium silicide layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950000075A KR0168153B1 (en) 1995-01-05 1995-01-05 Forming method of titanium silicide layer

Publications (2)

Publication Number Publication Date
KR960030334A true KR960030334A (en) 1996-08-17
KR0168153B1 KR0168153B1 (en) 1999-02-01

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ID=19406383

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950000075A KR0168153B1 (en) 1995-01-05 1995-01-05 Forming method of titanium silicide layer

Country Status (1)

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KR (1) KR0168153B1 (en)

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Publication number Publication date
KR0168153B1 (en) 1999-02-01

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