KR910020813A - Method of Forming Fine Metal Wiring in Semiconductor Manufacturing - Google Patents

Method of Forming Fine Metal Wiring in Semiconductor Manufacturing Download PDF

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Publication number
KR910020813A
KR910020813A KR1019900007706A KR900007706A KR910020813A KR 910020813 A KR910020813 A KR 910020813A KR 1019900007706 A KR1019900007706 A KR 1019900007706A KR 900007706 A KR900007706 A KR 900007706A KR 910020813 A KR910020813 A KR 910020813A
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South Korea
Prior art keywords
oxide film
semiconductor manufacturing
metal wiring
fine metal
depositing
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KR1019900007706A
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Korean (ko)
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KR930002662B1 (en
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경상현
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경상현
재단법인 한국전자통신연구소
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Priority to KR1019900007706A priority Critical patent/KR930002662B1/en
Publication of KR910020813A publication Critical patent/KR910020813A/en
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Publication of KR930002662B1 publication Critical patent/KR930002662B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

반도체 제조에서 미세 금속 배선의 형성방법Method of Forming Fine Metal Wiring in Semiconductor Manufacturing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가)∼(라)는 본 발명의 제조공정을 나타낸 단면도.(A)-(d) of FIG. 2 is sectional drawing which shows the manufacturing process of this invention.

Claims (2)

반도체 소자의 제조에 있어서, 실리콘기판(1)위에 금속층(2)을 증착하고, 그 상면에 산화막(3)을 플라즈마 화학 기상 증착 방법으로 증착하는 단계와, 산화막(3)을 상면에 증착한 상태에서 금속층(2)의 합금 공정을 수행한 다음에 산화막(3)을 제거하는 단계와, 합금공정을 수행한 금속배선(4)을 원하는 모양으로 패터닝하는 단계들에 의하여 힐록이 발생하지 않는 금속배선을 형성하도록한 반도체 제조에서 미세 금속 배선의 형성방법.In manufacturing a semiconductor device, depositing a metal layer 2 on a silicon substrate 1, depositing an oxide film 3 on the upper surface by a plasma chemical vapor deposition method, and depositing an oxide film 3 on the upper surface. Metallization with no heel lock by performing the alloying process of the metal layer 2 and then removing the oxide film 3 and patterning the metallization 4 subjected to the alloying process to a desired shape. Method for forming a fine metal wiring in the semiconductor manufacturing to form a. 제1항에 있어서, 금속층(2)의 상면에 산화막(3)을 플라즈마 화학 기상 증착하는 공정조건은 산화막(3)의 두께가 5000Å∼10000Å이고, 증착온도는 450℃이하이며, 증착전 가열시간은 1분이내 이고, 증착속도는 30Å/sec이상으로 수행하도록한 반도체 제조에서 미세 금속 배선의 형성방법.The process conditions for plasma chemical vapor deposition of the oxide film 3 on the upper surface of the metal layer 2 are as follows: The thickness of the oxide film 3 is 5000 kPa-10000 kPa, the deposition temperature is 450 占 폚 or less, and the heating time before deposition. Is less than 1 minute, and the deposition rate is 30 Å / sec or more to form a fine metal wiring in the semiconductor manufacturing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900007706A 1990-05-28 1990-05-28 Fine metal wiring building method KR930002662B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900007706A KR930002662B1 (en) 1990-05-28 1990-05-28 Fine metal wiring building method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900007706A KR930002662B1 (en) 1990-05-28 1990-05-28 Fine metal wiring building method

Publications (2)

Publication Number Publication Date
KR910020813A true KR910020813A (en) 1991-12-20
KR930002662B1 KR930002662B1 (en) 1993-04-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900007706A KR930002662B1 (en) 1990-05-28 1990-05-28 Fine metal wiring building method

Country Status (1)

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KR (1) KR930002662B1 (en)

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Publication number Publication date
KR930002662B1 (en) 1993-04-07

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